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Dissertations / Theses on the topic 'CMOS circuit'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 July 2025

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1

Madhyastha, Sadhana. "Design of circuit breakers for large area CMOS VLSI circuits." Thesis, McGill University, 1989. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=59551.

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Large-area ICs require adequate defect-tolerance to achieve a reasonable yield. One concern is that the power distribution network is shared by a number of modules, and any single short between the supply (V$ sb{dd}$) and ground can disable all these modules. The object of this thesis is to evaluate the feasibility of incorporating circuit breakers in large area ICs, which provide protection against such defects by disconnecting the defective modules from the array. A critical analysis and comparison of MOS transistors and parasitic bipolar transistors as circuit breakers are carried out. It i

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2

Ramirez, Ortiz Rolando. "Circuit design rules for mixed static and dynamic CMOS logic circuits." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp03/NQ37076.pdf.

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3

Ramirez, Ortiz Rolando Carleton University Dissertation Engineering Electronics. "Circuit design rules for mixed static and dynamics CMOS logic circuits." Ottawa, 1999.

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4

Zell, Christopher William. "Electrical effects of CMOS circuit packaging." Diss., The University of Arizona, 1996. http://hdl.handle.net/10150/187456.

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Integrated systems are becoming so complex, it is extremely difficult for designers to simulate full systems, particularly early in the design process. What the designer needs is a methodology to quickly look at where he/she is going, and determine if there are any potential packaging related problems. If so, where did the problem originate, and what can be done about it? The designer wants a quick, easy to use and understand methodology which consistently yields reasonably accurate results. This dissertation is limited to CMOS circuits interfacing with metal interconnects. Of particular inter

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Buttar, Alistair George. "CMOS process simulation." Thesis, University of Edinburgh, 1986. http://hdl.handle.net/1842/13282.

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6

He, Lizhong. "1-Ghz CMOS Analog Signal Squaring Circuit." Wright State University / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=wright1472476550.

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7

Yang, Hong. "Circuit Design and Reliability of a CMOS Receiver." Doctoral diss., University of Central Florida, 2004. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2102.

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This dissertation explores CMOS RF design and reliability for portable wireless receivers. The objective behind this research is to achieve an increase in integration level, and gain more understanding for RF reliability. The fields covered include device, circuit and system. What is under investigation is a multi-band multi-mode receiver with GSM, DCS-1800 and CDMA compatibility. To my understanding, GSM and CDMA dual-mode mobile phones are progressively investigated in industries, and few commercial products are available. The receiver adopts direct conversion architecture. Some improved cir

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Jin, Yalin. "Radio-frequency integrated-circuit design for CMOS single-chip UWB systems." Thesis, [College Station, Tex. : Texas A&M University, 2008. http://hdl.handle.net/1969.1/ETD-TAMU-2724.

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9

Rodnunsky, Nelson Lawrence. "Analysis of power dissipations in CMOS circuit designs." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0005/MQ34409.pdf.

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10

Phang, Khoman S. "CMOS optical preamplifier design using graphical circuit analysis." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/NQ58961.pdf.

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Yu, Chuanzhao. "STUDY OF NANOSCALE CMOS DEVICE AND CIRCUIT RELIABILITY." Doctoral diss., University of Central Florida, 2006. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3551.

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The development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability issues caused by voltage and/or temperature stress are gate oxide breakdown (BD), hot carrier effects (H

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12

Ghahroodi, Massoud. "Variation and reliability in digital CMOS circuit design." Thesis, University of Southampton, 2014. https://eprints.soton.ac.uk/365136/.

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The silicon chip industry continues to provide devices with feature sizes at Ultra-Deep-Sub-Micron (UDSM) dimensions. This results in higher device density and lower power and cost per function. While this trend is positive, there are a number of negative side effects, including the increased device parameter variation, increased sensitivity to soft errors, and lower device yields. The lifetime of next- generation devices is also decreasing due to lower reliability margins and shorter product lifetimes. This thesis presents an investigation into the challenges of UDSM CMOS circuit design, with

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13

Clavelier, Daniel. "Synthèse automatique d'amplificateurs opérationnels CMOS : choix du schéma électrique." Grenoble INPG, 1995. http://www.theses.fr/1995INPG0086.

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La conception de circuits integres sur mesure specifiques d'une application (en anglais: full custom asic) exige de nombreuses competences de la part du concepteur ; c'est pourquoi de nombreux outils de cao sont utilises pour simplifier son travail dans un certain nombre de taches. Dans le domaine analogique, l'amplificateur operationnel est une cellule de base strategique pour la conception de circuits integres. Au cours du travail de these, nous avons developpe un logiciel de cao permettant de realiser automatiquement la premiere tache de synthese d'un amplificateur operationnel cmos en micr

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Hincapié, Jorge Armando Oliveros. "Aplicação da programação geométrica no projeto de filtros Gm-C para receptores RF CMOS." Universidade de São Paulo, 2010. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-19012011-131843/.

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A tendência do mercado da microeletrônica é integrar em um mesmo chip sistemas eletrônicos completos, incluindo simultaneamente circuitos analógicos, digitais e RF. Por causa da complexidade do problema de projeto, a parte analógica e RF desses sistemas é o gargalo do desenvolvimento. Uma alternativa de projeto para circuitos analógicos é formular o projeto como um problema de otimização matemática conhecido como programação geométrica. As vantagens são: o ótimo global é obtido eficientemente, e é possível fazer automatização do projeto. A principal desvantagem é que não todos os parâmetros e

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Dandache, Abbas. "Conception de PLA CMOS." Phd thesis, Grenoble 2 : ANRT, 1986. http://catalogue.bnf.fr/ark:/12148/cb37596962j.

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Vaidyanadeswaran, Arvind. "Circuit Techniques on Improving Timing and Noise in Dynamic CMOS." Wright State University / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=wright1302048032.

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Biswas, Shampa. "Integrated CMOS Doppler Radar : System Specification & Oscillator Design." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-129222.

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This thesis report presents system specification, such as frequency and output power level, and selection topology of an oscillator circuit suitable for a CMOS Integrated Doppler radar application, in order to facilitate short range target detection within 5-15 m range, using a 0.35 μm CMOS process. With this selected CMOS process, the frequency band at 2.45 GHz or 5 GHz, with a maximum output power level of 25 mW (e.i.r.p), is found to be appropriate for the whole system to obtain a good performance. In this thesis work, a Ring VCO with pseudo-differential architecture has been designed and o

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Buchanan, Brent E. "A mixed-signal CMOS VLSI image convolution circuit using error spectrum shaping." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15420.

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Hung, Chin-Chung, and 洪志忠. "A CMOS Multiplier Circuit using a 1.5V CMOS Logic Circuit." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/66188657075161112912.

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碩士<br>國立臺灣大學<br>電機工程學系<br>85<br>This thesis reports a 1.5V high-speed 8X8 multiplier circuit usingthe Wallace tree reduction architecture and true-single- phase bootstrappeddyanmic and static circuit techniques. Based on a 0.8um CMOS technology, the CLA circuit speed performance of this 8X8 dynamic multiplier circuit is improved by 39% as compared to the CMOS Manchester carry look-aheadcircuit without using the bootstrapped technique. In the whole dynamicmultiplier circuit, it is improved b

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Yeh, Cheng-Chung, and 葉政忠. "1.5V CMOS divider & adiabatic circuit using a 1.5V CMOS dynamic logic circuit." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/79552986844586122048.

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碩士<br>國立臺灣大學<br>電機工程學系<br>85<br>This thesis reports a 1.5V high-speed 16-bit/8-bit divider circuit usingthe quotient-select architecture and true-single- phase bootstrapped dynamic circuit techniques [2.13],[2.14]. Based on a 0.8um CMOS technology, thespeed performance of this 16-bit/8-bit divider circuit is improved by 45%as compared to the divider using the non-restoring iterative architecture andthe domino dynamic logic circuits without the bootstrapped technique. Thisdivider circuit, wh

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Nandyala, Venkata Ramakrishna. "Leakage Power Minimization in CMOS VLSI Circuits: Circuit level Approaches." Thesis, 2022. http://ethesis.nitrkl.ac.in/10305/1/2022_PhD_VRNandyala_512EC107_Leakage.pdf.

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An electronic system/appliance/portable device with high speed, low power, and feasible area has become the finest choice for the consumer. CMOS technology has been continuously scaled down to meet the increasing demand of such kind. Nonetheless, the extent of scaling is constrained by physical limitations such as short-channel effects. The problem has taken a serious turn as the scaling extends into ultra-deep-submicron (UDSM) regime. The main consequences are the leakage currents contributing to massive static power dissipation. Hence the power dissipation has become the critical issue in th

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Lee, Guo-hua, and 李國華. "CMOS Charge Pump Circuit Design." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/78496786707113258946.

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碩士<br>國立雲林科技大學<br>電子與資訊工程研究所<br>99<br>As the technology advancs, the CMOS VLSI chip becomes smaller and the power supply voltage scales down. However,some SOC circuits still need to be operated with high voltage . Thus, CMOS charge pump circuit is becoming more and more important. Take USB-OTG for instance, the charge pump for USB-OTG requires not only the high voltage level, but also high current drivability. Besides, the output ripple voltage should be small and the power efficiency should be high. Thus, a High efficiency heavy-load CMOS charge pump circuit is designed and implemented. The

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Yan, Sheng-Hung, and 顏昇宏. "CMOS RF Transceiver Circuit Design." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/41889247875833739850.

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碩士<br>國立臺灣大學<br>電信工程學研究所<br>89<br>ABSTRACT Standard CMOS process has advantages of high integration ability of base-band, IF and RF modules into a single chip with low cost. In this thesis, several RF front-end circuits operated at 2.4GHz are designed using the standard CMOS process. The RF components are designed based on direct-modulation transmitter and direct-conversion receiver architectures. In Chapter 2, CMOS RF model is studied and compared with the traditional BSIM3 model which has been widely used in analog and digital circuit design. By properly adding resistor

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Chen, Ting-Hao, and 陳鼎豪. "CMOS PWM Signal Generating Circuit." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/9k4ue6.

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碩士<br>國立虎尾科技大學<br>電子工程系碩士班<br>100<br>A PWM generator, which uses a level-shifting triangular wave generator to adjust the pulse-width of the output waveform, has been proposed in this thesis. The proposed PWM generator is suitable for class D amplifier. Also, a novel approach to correct the distorted output waveform, which is due to the limited input-range or nonlinearity of the comparator, of the PWM generator has been introduced. The proposed approach is to shift the dc level of the triangular wave up and down to increase the voltage difference at the input terminals of the comparator. As a

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Yu, Ben, and 游象斌. "CMOS Current-Mode Geometric-Mode Circuit and Gamma-Correction Circuit." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/58151601328479149792.

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碩士<br>中華大學<br>電機工程學系(所)<br>97<br>In this thesis, we have proposed two CMOS current-mode circuits. One is a geometric-mean circuit, and another is a gamma-correction circuit. The geometric-mean circuit is composed of n logarithm-circuits and one exponential-circuit. The logarithm-circuits and the exponential-circuit are designed by second-order polynomial circuits which are approximated by Taylor’s series. The proposed geometric-mean circuit has n inputs. The gamma value of the gamma-correction circuit could be varied through different input currents. Moreover, we have large input-range and les

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Huang, Chih-Wei, and 黃智偉. "CMOS wirless communication RF circuit design." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/77304606820835526556.

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碩士<br>國立中央大學<br>電機工程研究所<br>90<br>Abstract In these years, CMOS technology has better performance in radio frequency (RF) circuit design by improving the process. The thesis bases on the RF circuit design. In the chapter 2, we introduce the principles and methods of the power amplifier circuit design, and we design a two-stage power amplifier. In the chapter 3, we introduce the RF up-conversion mixer. The linearity of the up-conversion mixer is very important, so we design three kinds of up-conversion mixer to compare their performance. In the chapter 4, we introduce the principles and circuit

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Chen, Yi-Hua, and 陳奕樺. "CMOS Current-Mode Quadratic Circuit Synthesizer." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/69820082314677793655.

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碩士<br>中華大學<br>電機工程學系碩士班<br>98<br>This thesis discusses the circuits of quadratic synthesized with CMOS current mode. The users only need to set the coefficients of quadratic they want, will generate the circuit W/L ratio of MOS and others parameters. These data are supplied to user to reduce a great deal of time and money, and understanding the problems and solutions of Circuit design. The circuits of quadratic in this thesis utilize 0.35um CMOS process in TSMC to simulate which the situation is in real chip manufacture. After layout of proposed circuit, the results show that the area is 0.32x

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Chang, Yo-Wei, and 張育瑋. "5.8GHz CMOS Front-End Circuit Design." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/62993036363760539268.

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碩士<br>華梵大學<br>電子工程學系碩士班<br>94<br>This thesis presents a 802.11a WLAN 5.8GHz CMOS Front-End circuit design in UMC 0.18um CMOS process. The chip contains Low Noise Amplifier, Passive Balun, Active Inductor, Gilbert Cell Mixer and Single-Ended Amplifier. The RF spectrum specification is from 5.725~5.825GHz, the LO is from 5.237GHz~5.337GHz, and the IF is at 488MHz. The low noise amplifier exhibits a gain of 18.26dB, noise figure of 2.38dB, input P1dB at -26.5dBm, and output P1dB at -9.69dBm. The Gilbert cell mixer exhibits a conversion gain of 33.62dB, noise figure of 15.38dB, input P1dB at -31.

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Chiang, Tzung-Yin, and 江宗殷. "Temperature-compensated CMOS voltage reference circuit." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/07003708814603618036.

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碩士<br>國立清華大學<br>工程與系統科學系<br>93<br>Reference circuits have been studying for many years. Following the vigorous development of portable electronic products, integrated circuits with low voltage and small area have become the core part of the recent research. Parasitic vertical bipolar junction transistors are commonly used in CMOS voltage reference circuits for a better stability. Recently, MOS reference circuits have been used to replace BJT ones in order to reduce the chip area and supply voltage. Whether BJT or MOS is utilized, the problem that resistances parallelizing on either side of BJT

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Hsu, Chun-Chen, and 許鈞程. "CMOS Analog Circuit Layout Design Automation." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/62541285242114704365.

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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>91<br>Layout design is a very important step in the analog CMOS IC design flow. Good layout quality should feature low susceptibility to digital noise and low sensitivity to process variation. It has historically been a time-consuming, manual task. The fast growth of complexity of VLSI systems and recent advances in System-On-Chip (SOC) developments, make it necessary to have powerful Computer-Aided-Design (CAD) tools to speed up the design process. This issue is especially important for analog circuit layout design. In this thesis, we present a tool to auto

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Liu, Zhiyu. "Multi-voltage nanoscale CMOS circuit techniques." 2008. http://www.library.wisc.edu/databases/connect/dissertations.html.

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CHEN, YOU-ZHENG, and 陳有正. "A novel cmos neural network circuit." Thesis, 1990. http://ndltd.ncl.edu.tw/handle/11024682375182064769.

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阮張榮. "Circuit extraction and recognition for the CMOS gate array integrated circuit." Thesis, 1989. http://ndltd.ncl.edu.tw/handle/12827538599964414587.

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Wu, Chia-Ching, and 吳嘉靖. "CMOS Circuit Design of Displacement Capacitive Sensors." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/57376664169850539566.

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碩士<br>國立臺灣大學<br>應用力學研究所<br>96<br>The purpose of this dissertation is to realize the design and layout of CMOS capacitive sensing circuit, and in this case to compare the differences before and after layout. In this dissertation use the two-stage amplifier to be the principal. Furthermore, layout the dispersed elements, and modify that after layout to satisfy our requirement. This dissertation is applying 0.35μm Mixed-Signal 2P4M Polycide 3.3/5V manufacture process of TSCM which is provided by NSC Chip Implementation Center. Finally, using Hspice software designed by Synopsys co. to simulate a

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Fu, Chien-Cheng, and 傅建程. "CMOS BIOSENSOR READOUT CIRCUIT WITH TEMPERATURE SENSOR." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/61626205578424005036.

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碩士<br>國立高雄師範大學<br>電子工程學系<br>101<br>The ion-sensitive field effect transistor (ISFET), introduced first by Bergveld in 1970, combined the chemical-sensitive membrane with the metal-oxide-semiconductor field effect transistor. For the past many years, various sensing membrane, readout circuits and calibration methods have been presented. In this thesis, a novel temperature sensor, ISFET structures with built-in gold (Au) reference electrode, and several readout circuits with multiple inputs and an offset sub-circuit are presented. Our laboratory has confirmed previously that the native alumi

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Chen, Yu-Shen, and 陳育紳. "Multi-Standard CMOS RFPower Amplifier Circuit Design." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/96779658719098198977.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>100<br>As the demand of wireless system increases rapidly, more and more wireless communication standards are used simultaneously in our lives. Therefore, a multi-standard communication system that can be integrated into a single wireless transceiver becomes an important research issue. The dominant technique to achieve highly-integrated transmitter architecture is the wideband power amplifier circuit design. This Thesis is focused on a broadband and multi-standard RF power amplifier for 2.45GHz ISM 802.11b, 802.11g/n, Bluetooth, 3.5G UWB-WiMAX 802.16a, and 5GHz U-N

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Lin, Lang. "Cryptographic circuit design in nanometer CMOS technologies." 2012. https://scholarworks.umass.edu/dissertations/AAI3498403.

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As increasingly important modules in modern embedded systems, cryptographic circuits rely on provable theorems to guarantee hardware security and information privacy. However, perfect security on silicon is very difficult to achieve because traditional implementations of cryptographic circuits are vulnerable to various physical attacks and especially power side-channel analysis attacks. With the rapid advances of complementary metal-oxide-semiconductor (CMOS) technologies reaching nanometer regimes, more security threats on the hardware level occur due to increased data-dependent leakage power

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Tsou, Wen An, and 鄒文安. "The study of CMOS radio frequency circuit." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/53148295743454197749.

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碩士<br>國立臺灣科技大學<br>電子工程系<br>90<br>The explosion of interest in radio frequency integrated circuit(RFIC's) in the last decade has been driven by the expansion of the market foruntethered communications in a variety of forms @ from pagers and cordlesstelephones to analog and digital cellular telephones and personal commun-ication system (PCS's). CMOS technology is expected to possess a significantedge in final wafer production costs @ measured in a dollars per square milli-meter @for the foreseeable future, and this presents an attractive opportunity toleverage CMOS technology into the RF regime.

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Chen, Hung-chieh, and 陳宏傑. "Mixed-Mode Simulator for CMOS Integrated Circuit." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/93539905144639371714.

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碩士<br>國立中央大學<br>電機工程學系<br>85<br>In this thesis, a mixed-mode simulator is implemented. First, one partition method for dividing a mixed-signal circuit into several loosely coupled analog and digital modules is proposed. Secondly, these loosely coupled modules will be simulated with different settings SPICE. Analog modules are simulated with the default setting, whereas digital modules are simulated with a less accuracy setting. Thirdly, our simulation backplane, controller, is responsibl

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Chien, Ming Chu, and 簡旻助. "The study of ESD protection circuit in deep submicron CMOS and RF circuits." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/48305409296750658216.

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碩士<br>國立清華大學<br>電子工程研究所<br>90<br>In order to ensure IC products can go to the market smoothly and on time, function faultless and reliability are very important. But as we know, the key point is if they can pass ESD testing or not. Although some advanced processes help prompting IC performance with processes scaling down, it pays the expense of reducing ESD performance also. How to invent novel devices or circuits to provide a whole chip ESD protection in deep sub-micron technology is the main point in this thesis. In this thesis, a new ESD protection methodology for high freque

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Hung, Chien-Ming, and 洪健珉. "A Circuit Level Variability Model of Basic Logic Circuits in Trigate CMOS Devices." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/759g7c.

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碩士<br>國立交通大學<br>電子工程學系電子研究所<br>103<br>In order to improve the drive current, the most efficient way is scaling down the channel length. As channel length continues scaling down below 100 nm, the short channel effects, such as Vth variation and DIBL leakage, become increasingly important. To overcome these challenges, high-k gate dielectric layers, metal gate, III-V material for channel, and 3D structures are the most possible solutions. Among all these new solutions, the tri-gate MOSFET devices exhibit excellent I-V characteristics and manufacturing ability, which is believed to be able to c

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Kalani, Sarthak. "Voltage and Time-Domain Analog Circuit Techniques for Scaled CMOS Technologies." Thesis, 2020. https://doi.org/10.7916/d8-8ch2-7e04.

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CMOS technology scaling has resulted in reduced supply voltage and intrinsic voltage gain of the transistor. This presents challenges to the analog circuit designers due to lower signal swing and achievable signal to noise ratio (SNR), leading to increased power consumption. At the same time, device speed has increased in lower design nodes, which has not been directly beneficial for analog circuit design. This thesis presents voltage-domain and time-domain circuit scaling friendly circuit architectures that minimize the power consumption and benefit from the increasing transistor speeds. In

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Chang, Ming-Hui. "Mechanism and Circuit Design of CMOS Electrostatic Micromotors." 2004. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2707200416193500.

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Chang, Yueh-Huang, and 張岳煌. "1.2 V CMOS Switched Capacitor Integrated Circuit Technique." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/12861229683034722806.

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碩士<br>國立交通大學<br>電子研究所<br>83<br>There are more and more portable battery-operated equipments . The most important objectives of portable battery-operated equipment are low-power consumption and low-voltage supply to increase battery liftime and to reduce weight of instruments. So ,the trend of analog/digital circuits is toward the low- voltage operation. The proposed low-voltage switched capacitor system with fully differential topology is operated by 1.2 V and an extra high voltage

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Chi-Chin, Hu, and 胡奇智. "2.4GHz CMOS Receiver Front-end Circuit for WLAN." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/86785696435293642974.

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碩士<br>國立臺北科技大學<br>電腦通訊與控制研究所<br>91<br>Recently, the technologies of wireless communication are applied extensively to such as GSM, GPRS, Bluetooth, and WLAN. Therefore, WLAN becomes an important solution to the development of internet, and then has gradually become essential to life and create another rise for the opportunity of commerce. The main purpose of this thesis is to adopt the double balance Gilbert cell mixer, proving better conversion gain, even order harmonics elimination and isolation enhancement of LO port to RF port. Furthermore, a low noise amplifier incorporating a

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Liu, Ping, and 劉坪. "BIST Burn-in Methodology for the CMOS Circuit." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/z7qbsb.

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碩士<br>國立交通大學<br>電子工程系所<br>94<br>This thesis proposes and studies a BIST burn-in methodology which is aimed to finding early failure in CMOS SOC testing. It is to, on-chip, apply a set of patterns which maximizes the power dissipation to burn-in test the CUT without resorting to the conventional burn-in furnace testing. The thesis first studies the test generation for the combinational circuit and then apply the result to the sequential circuit. Also, we derive the patterns for the PLA type of circuits to achieve the maximal switching, i.e., the maximal power consumption. Moreover, we propose a

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Lin, Jeng-Chuan, та 林政筌. "0.18μm 5GHz CMOS-MEMS RF filter circuit design". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/48387508273752697453.

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碩士<br>東海大學<br>電機工程學系<br>97<br>With mobile communication products popularizing, the communication products expand speedily. For convenience to user, it is needed extremely to lighten and shrink the mobile productions. The system on a chip (SOC) is a solution to satisfy the need. Therefore, the SOC is a current trend of the development. In past years, silicon-base semiconductor process, computer-aided design tools, and circuit design skills have all made great progress, and it makes the high integration between digital and analog circuits. However, it is difficult to integrate with radio frequen

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Liu, Chungn-Tai, та 劉中泰. "Study on 0.18μm 2GHz CMOS RF Switch Circuit". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/24220140773372491302.

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碩士<br>東海大學<br>電機工程學系<br>97<br>In past years, silicon-base semiconductor process, computer-aided design tools, and circuit design skills have all made great progress, and it makes the high integration between digital and analog circuits. However, it is difficult to integrate with radio frequency (RF) circuits, such as RF filter, RF power amplifier, and RF switch. Among those RF circuits, the reasons of that RF switch could not be integrated in system are high insertion loss and low power handling. Those issues occur because the silicon substrate is conductance material inducing power loss. This

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Chan, Feng-Lin, and 詹豐林. "An Electrochemical Dopamine Sensor with CMOS Detection Circuit." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/52743442072710908424.

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Cheng, Shih-Ming, and 石明正. "CMOS RFIC Front-end circuit design for Bluetooth." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/15674271016428896651.

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碩士<br>國立中正大學<br>通訊工程研究所<br>92<br>This paper describes the radio receiver for Bluetooth application operation at 2.4GHz ISM band. Bluetooth is designed to be a low-cost, low-power, and short-range radio technology. The LNA, Mixer and VCO implemented with TSMC CMOS process. We use high frequency circuit simulation tools - advanced design system to design.

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