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Journal articles on the topic 'CMOS circuit'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 July 2025

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1

He, Xinyu. "Design of CMOS circuits through transistor sizing techniques." Applied and Computational Engineering 12, no. 1 (2023): 1–12. http://dx.doi.org/10.54254/2755-2721/12/20230279.

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With the increasingly diverse functional requirements of contemporary electronic products, the complexity of CMOS circuits often used in chips becomes higher and the number of transistors used increases. To solve the resulting performance problems of CMOS circuits, researchers have searched for many transistor sizing technologies. This paper summarizes three methods of CMOS circuit optimization. The paper introduces these three methods in terms of principle, effect, and application scenarios, and compares them respectively. Through analysis and simulation, it can be found that the use of these

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Prajapati, Pankaj P., Anilkumar J. Kshatriya, Sureshbhai L. Bharvad, and Abhay B. Upadhyay. "Performance analysis of CMOS based analog circuit design with PVR variation." Bulletin of Electrical Engineering and Informatics 12, no. 1 (2023): 141–48. http://dx.doi.org/10.11591/eei.v12i1.4357.

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Process, supply voltage, and temperature (PVT) are three important factors which contribute to performance variation of the complementary metal–oxide–semiconductor (CMOS) based analog circuits. In this paper, CMOS based analog circuit design with the PVT variation effects are explored. The effects of the PVT variation on the performance of CMOS based analog circuits are introduced. The optimization of CMOS based analog circuits such as differential amplifier (DA) and two-stage operational amplifier (op amp) circuits with PVT variations with different algorithms such as cockoo search (CS), part

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3

KIM, JEONG BEOM. "CURRENT MODE CMOS QUATERNARY LOGIC FULL-ADDER." Journal of Circuits, Systems and Computers 18, no. 01 (2009): 199–208. http://dx.doi.org/10.1142/s0218126609005022.

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This paper proposes a quaternary-to-binary logic decoder, a quaternary current buffer, and a quaternary full-adder using current-mode multiple-valued logic (MVL) CMOS circuits. The proposed full-adder is superior to the previous MVL CMOS circuit in both the circuit occupied area and the performance. Comparing with the binary logic full-adder, the proposed full-adder is superior in the circuit occupied area. However, the circuit performance is inferior to the binary logic full-adder. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.25 μm stan

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Oktay, Aytar. "The Investigation of Auto-Zero Comparator Performance of Common Gate Differential Amplifier Based CMOS Inverter Circuit." Journal of Scientific, Technology and Engineering Research (JSTER) 1, no. 2 (2020): 25–32. https://doi.org/10.5281/zenodo.4069563.

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<strong>The Investigation of Auto-Zero Comparator Performance of Common Gate Differential Amplifier Based CMOS Inverter Circuit</strong> <em><strong>Abstract</strong> - In this study, the performance of the common gate difference amplifier cmos inverter circuit as an auto-zero comparator circuit was investigated using 0.18μm CMOS process model in the NCSU Design Kit of the Cadence IC5141 design program. The performance of the proposed structure was compared with traditional inverter circuit and darlington cmos inverter circuit. In accordance with the results of DC analysis, the voltage gain

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Chen, Jiahao. "Integrated circuit design based on CMOS technology principle and its application in GPU." Theoretical and Natural Science 12, no. 1 (2023): 141–46. http://dx.doi.org/10.54254/2753-8818/12/20230454.

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In today's society, the application of integrated circuit technology can be seen everywhere, especially in the past two decades. This paper mainly studies the principle and design of CMOS devices in IC technology and discusses the research and analysis of the acceleration algorithm of IC design. This paper adopts the research method of literature review and analysis to summarize the existing research results. This paper first introduces the development background of integrated circuit technology and the importance of CMOS technology. Subsequently, the concept and interconnection principle of C

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6

HURST, S. L. "Open-circuit testing of CMOS circuits." International Journal of Electronics 62, no. 2 (1987): 161–65. http://dx.doi.org/10.1080/00207218708920964.

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7

Bae, Woorham. "CMOS Inverter as Analog Circuit: An Overview." Journal of Low Power Electronics and Applications 9, no. 3 (2019): 26. http://dx.doi.org/10.3390/jlpea9030026.

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Since the CMOS technology scaling has focused on improving digital circuit, the design of conventional analog circuits has become more and more difficult. To overcome this challenge, there have been a lot of efforts to replace conventional analog circuits with digital implementations. Among those approaches, this paper gives an overview of the latest achievement on utilizing a CMOS inverter as an analog circuit. Analog designers have found that a simple resistive feedback pulls a CMOS inverter into an optimum biasing for analog operation. Recently developed applications of the resistive-feedba

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WANG, WEIZHI, and DONGMING JIN. "CMOS DESIGN OF ANALOG FUZZY SYSTEM." Journal of Circuits, Systems and Computers 14, no. 06 (2005): 1101–12. http://dx.doi.org/10.1142/s0218126605002830.

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This paper proposes several improved CMOS analog integrated circuits for fuzzy inference system as the general modules, including voltage-mode implementations of minimization circuit, programmable Gaussian-like membership function circuit, and centroid algorithm normalization circuit without using division. A two-input/one-output fuzzy system composed of these circuits is implemented and testified as a nonlinear function approximator. HSPICE simulation results show that the proposed circuits provide characteristics of high operation capacity, simple inference, low power dissipation, and high p

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9

SOLIMAN, AHMED M., and AHMED H. MADIAN. "MOS-C KHN FILTER USING VOLTAGE OP AMP, CFOA, OTRA AND DCVC." Journal of Circuits, Systems and Computers 18, no. 04 (2009): 733–69. http://dx.doi.org/10.1142/s021812660900523x.

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MOS-C realizations of the Kerwin–Huelsman–Newcomb (KHN) circuit using the commercially available Voltage Operational Amplifier (VOA) and the Current Feedback Operational Amplifier (CFOA) are reviewed in this paper. Additional MOS-C KHN realizations using the Operational Transresistance Amplifier (OTRA) and the Differential Current Voltage Conveyor (DCVC) are also included. MOS-C realizations of the KHN circuit using CMOS operational amplifier, CMOS current feedback operational amplifier and CMOS operational transresistance amplifier are also given. Spice simulation results using 0.18 CMOS tech

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10

M. Surekha, V. HariKrishna, B. MadhuSudhan Reddy, G.Tejaswini, I.Rajasekhar, and K.Divya. "Efficient Approaches to Design Full Adder Using Domino Logic Technique." international journal of engineering technology and management sciences 7, no. 2 (2023): 283–88. http://dx.doi.org/10.46647/ijetms.2023.v07i02.033.

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Static CMOS and Domino CMOS Circuits are significantly used in high performance VLSI system. Designing a circuit with low power, high speed performance is one of the challenging aspects. In modern VLSI systems area efficient devices are utmost popular because most of the devices are becoming portable. This paper proposes One- bit full adder circuit is designed using CMOS based on mirror logic and Domino CMOS also designed based on same logic with LTSPICE at 180nm technology with 1.8V supply. This method provides better power and delay.

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Sedaghat, Mahsa, and Mahdi Salimi. "Evaluation and Comparison of CMOS logic circuits with CNTFET." Journal of Research in Science, Engineering and Technology 3, no. 04 (2019): 1–9. http://dx.doi.org/10.24200/jrset.vol3iss04pp1-9.

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In this paper, a comparison between CMOS and MOSFET base circuits HSPICE is done with software. 0.13 CMOS transistor model for simulation and CNTFET Model of Stanford University used. In simulations amounts of power, circuit delay and PDP is calculated and these values were compared at the end. And tried to CNTFET applications of transistors in circuit design, including memory and logic circuits Ternary be expressed.

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12

Bundalo, Dusanka, Zlatko Bundalo, and Branimir Ðordjevic. "Design of quaternary logic systems and circuits." Facta universitatis - series: Electronics and Energetics 18, no. 1 (2005): 45–56. http://dx.doi.org/10.2298/fuee0501045b.

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The principles and possibilities of design of fully quaternary multiple valued combinational logic systems and circuits are described and proposed in the paper. Different ways of design of fully quaternary combinational logic systems and circuits are considered and described first. Then algorithm for automated computerized design of such systems and circuits is considered and proposed. The algorithm gives possibility for synthesis and optimization of quaternary logic systems and circuits. It is applied on design of CMOS quaternary multiple valued logic systems and circuits. The algorithm inclu

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Shinghal, Deepti, Amit Saxena, and Arti Noor. "Comparative Analysis of Conventional CMOS and Adiabatic Logic Gates." MIT International Journal of Electronics and Communication Engineering 4, no. 1 (2014): 39–43. https://doi.org/10.5281/zenodo.5406915.

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This paper deals with comparative study of conventional CMOS circuits with CMOS based reversible logic circuits employing Adiabatic switching methods. The power dissipation an important characteristic is tested by means of SPICE circuit simulation techniques for a CMOS AND-OR-INVERTER (AOI) gate. Results from both conventional and adiabatic logic switching simulations are compared. The breakdown of adiabatic operation for these reversible circuits, due to the finite threshold voltages, is tested by checking the logic circuit node current/voltage transient waveform during the logic switching tr

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14

Prajapati, Pankaj P., and Mihir V. Shah. "Automatic Circuit Design of CMOS Miller OTA Using Cuckoo Search Algorithm." International Journal of Applied Metaheuristic Computing 11, no. 1 (2020): 36–44. http://dx.doi.org/10.4018/ijamc.2020010103.

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The circuit design of the CMOS based analog part of a mixed-signal integrated circuit (IC) needs a large fraction of the overall design cycle time. The automatic design of an analog circuit is inevitable, seeing recently development of System-on-Chip (SOC) design. This brings about the need to develop computer aided design (CAD) tools for automatic design of CMOS based analog circuits. In this article, a Cuckoo Search (CS) algorithm is presented for automatic design of a CMOS Miller Operational Transconductance Amplifier (OTA). The source code of the CS algorithm is developed using the C langu

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15

Dash, Sandeep K., Bishnu Prasad De, Pravin K. Samanta, et al. "Optimal Design of Voltage Reference Circuit and Ring Oscillator Circuit Using Multiobjective Differential Evolution Algorithm." Journal of Electrical and Computer Engineering 2023 (August 8, 2023): 1–11. http://dx.doi.org/10.1155/2023/7621594.

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This paper deals with the optimal design of different VLSI circuits, namely, the CMOS voltage reference circuit and the CMOS ring oscillator (RO). The optimization technique used here is the multiobjective differential evolution algorithm (MDEA). All the circuits are designed for 90 nm technology. The main objective of the CMOS voltage reference circuit is to minimize the voltage variation at the output. The targeted value of the reference voltage is 550 mV. A CMOS ring oscillator (RO) is designed depending on the performance parameters such as power consumption and phase noise. The optimal tr

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SOLIMAN, AHMED M., and AHMED H. MADIAN. "MOS-C TOW-THOMAS FILTER USING VOLTAGE OP AMP, CURRENT FEEDBACK OP AMP AND OPERATIONAL TRANSRESISTANCE AMPLIFIER." Journal of Circuits, Systems and Computers 18, no. 01 (2009): 151–79. http://dx.doi.org/10.1142/s0218126609004995.

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Several MOS-C realizations of the Tow-Thomas circuit using the commercially available voltage operational amplifier and the current feedback operational amplifier are reviewed in this paper. Additional MOS-C Tow-Thomas realizations using the operational transresistance amplifier and the differential current voltage conveyor are also included. MOS-C realizations of the Tow-Thomas circuit using CMOS operational amplifier, CMOS current feedback operational amplifier and CMOS operational transresistance amplifier are also given. Spice simulation results using 0.18 CMOS technology model from MOSIS

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17

Kushwah, Ravindra Singh, and Shyam Akashe. "FinFET Based Tunable Analog Circuit: Design and Analysis at 45 nm Technology." Chinese Journal of Engineering 2013 (October 24, 2013): 1–8. http://dx.doi.org/10.1155/2013/165945.

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We included a designing of low power tunable analog circuits built using independently driven FinFETs devices, where the controlling of the back gate provide the output on the front gate. We show that this could be an effective solution to conveniently tune the output of bulk CMOS analog circuits particularly for Schmitt trigger and operational transconductance amplifier circuits. FinFET devices can be used to increase the performance by reducing the leakage current and power dissipation, because front and back gates both are independently controlled. FinFET device has a higher controllability

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18

Tiwari, Ayush. "Leakage Power Reduction in CMOS VLSI Circuits using Advance Leakage Reduction Method." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (2021): 962–66. http://dx.doi.org/10.22214/ijraset.2021.35065.

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Recently, consumption of power is key problem of logic circuits based on Very Large Scale Integration. More potentiality consumption isn’t considered an appropriate for storage cell life for the use in cell operations and changes parameters such as optimality, efficiency etc, more consumption of power also provides for minimization of cell storage cycle. In present scenario static consumption of power is major troubles in logic circuits based on CMOS. Layout of drainage less circuit is typically complex. Several derived methods for minimization of consumption of potentiality for logic circuits

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19

Xu, Haoran, Jianghua Ding, and Jian Dang. "Design and Characteristics of CMOS Inverter based on Multisim and Cadence." Journal of Physics: Conference Series 2108, no. 1 (2021): 012034. http://dx.doi.org/10.1088/1742-6596/2108/1/012034.

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Abstract Known as complementary symmetrical metal oxide semiconductor (cos-mos), complementary metal oxide semiconductor is a metal oxide semiconductor field effect transistor (MOSFET) manufacturing process, which uses complementary and symmetrical pairs of p-type and n-type MOSFETs to realize logic functions. CMOS technology is used to build integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including CMOS BIOS) and other digital logic circuits. CMOS technology is also used in analog circuits, such as image sensors (CMOS sensors), data converters, RF cir

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20

Li, Shuo, Nan Pan, Sen Gao, and Lei Li. "Three State Output Module and Digital Switch Circuit Based on Threshold Memristor." Journal of Physics: Conference Series 2395, no. 1 (2022): 012021. http://dx.doi.org/10.1088/1742-6596/2395/1/012021.

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Abstract A memristor is a new electronic device with small volumes and small fluctuations. As a two-terminal device, it is mainly characterized by non-volatility and nanoscale characteristic size. Memristors can also calculate and store at the same time, which has a broad application prospect in logic circuits. Traditional integrated circuit technology has been very mature. And CMOS technology has almost reached the limit of physical size. Compared with traditional circuit components, memristor devices are compatible with CMOS circuits with their fast computing speed, low power consumption, an

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21

Moritz, P. S., and L. M. Thorsen. "CMOS circuit testability." IEEE Journal of Solid-State Circuits 21, no. 2 (1986): 306–9. http://dx.doi.org/10.1109/jssc.1986.1052520.

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22

Riezenman, M. J. "Wanlass's CMOS circuit." IEEE Spectrum 28, no. 5 (1991): 44. http://dx.doi.org/10.1109/6.83438.

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23

Ki, Donghan, Minwoong Lee, Namho Lee, and Seongik Cho. "Design and Validation of a V-Gate n-MOSFET-Based RH CMOS Logic Circuit with Tolerance to the TID Effect." Electronics 12, no. 15 (2023): 3331. http://dx.doi.org/10.3390/electronics12153331.

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This study designed a radiation-hardened (RH) complementary metal oxide semiconductor (CMOS) logic circuit based on an RH variable-gate (V-gate) n-MOSFET that was resistant to the total ionizing dose (TID) effect and evaluated its tolerance to radiation. Among the different CMOS logic circuits, NOT, NAND, and NOR gates were designed using V-gate n-MOSFETs by employing layout transformation techniques and standard p-MOSFETs. Before the process design, we predicted the radiation damage using modeling and simulation techniques and validated the tolerance by conducting actual radiation tests after

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Kamde, Shilpa, Jitesh Shinde, Sanjay Badjate, and Pratik Hajare. "Comparative Analysis Domino Logic Based Techniques For VLSI Circuit." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 12, no. 8 (2014): 3803–8. http://dx.doi.org/10.24297/ijct.v12i8.2998.

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Domino logic is a CMOS-based evolution of the dynamic logicÂ techniques Â basedÂ onÂ eitherÂ PMOSÂ orÂ NMOS transistors. Domino logic technique is widely used in modern digital VLSI circuit. Dynamic logic is twice as fast as static CMOS logic because it uses only N fast transistors. The Dynamic (Domino) logic circuit are often favored in high performance designs because of the high speed and low area advantage.Four different dynamic circuit techniques including Basic domino logic circuit are compared in this paper for low power consumption and speed of domino logic circuits. For digital circui

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Mahnoor Maghroori and Mehdi Dolatshahi. "Design of low-power CMOS VLSI circuits using multi-objective optimization in genetic algorithms." World Journal of Advanced Research and Reviews 12, no. 1 (2021): 215–24. http://dx.doi.org/10.30574/wjarr.2021.12.1.0427.

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This paper presents a design CAD tool for automated design of digital CMOS VLSI circuits. In order to fit the circuit performance into desired specifications, a multi-objective optimization approach based on genetic algorithms (GA) is proposed and the transistor sizes are calculated based on the analytical equations describing the behavior of the circuit. The optimization algorithm is developed in MATLAB and the performance of the designed circuit is verified using HSPICE simulations based on 0.18µm CMOS technology parameters. Different digital integrated circuits were successfully designed an

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Mahnoor, Maghroori, and Dolatshahi Mehdi. "Design of low-power CMOS VLSI circuits using multi-objective optimization in genetic algorithms." World Journal of Advanced Research and Reviews 12, no. 1 (2021): 215–24. https://doi.org/10.5281/zenodo.5594256.

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This paper presents a design CAD tool for automated design of digital CMOS VLSI circuits. In order to fit the circuit performance into desired specifications, a multi-objective optimization approach based on genetic algorithms (GA) is proposed and the transistor sizes are calculated based on the analytical equations describing the behavior of the circuit. The optimization algorithm is developed in MATLAB and the performance of the designed circuit is verified using HSPICE simulations based on 0.18µm CMOS technology parameters. Different digital integrated circuits were successfully desig

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27

Saini, Jitendra Kumar, Avireni Srinivasulu, and Renu Kumawat. "High-Performance Low-Power 5:2 Compressor With 30 CNTFETs Using 32 nm Technology." International Journal of Sensors, Wireless Communications and Control 9, no. 4 (2019): 462–67. http://dx.doi.org/10.2174/2210327909666190206144601.

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Background: The advent of High Performance Computing (HPC) applications and big data applications has made it imparitive to develop hardware that can match the computing demands. In such high performance systems, the high speed multipliers are the most sought after components. A compressor is an important part of the multiplier; it plays a vital role in the performance of multiplier, also it contributes to the efficiency enhancement of an arithmetic circuit. The 5:2 compressor circuit design proposed here improves overall performance and efficiency of the arithmetic circuits in terms of power

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AL-Qaysi, Hayder Khaleel, Musaab Mohammed Jasim, and Siraj Manhal Hameed. "Design of very low-voltages and high-performance CMOS gate-driven operational amplifier." Indonesian Journal of Electrical Engineering and Computer Science 20, no. 2 (2020): 670. http://dx.doi.org/10.11591/ijeecs.v20.i2.pp670-679.

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This paper presents the description and analysis of the design and HSPICE-based simulation results of very low-voltages (LVs) power supplies and high-performance specifications CMOS gate-driven (GD) operational amplifier (Op-Amp) circuit. The very LVs CMOS GD Op-Amp circuit designed using 90nm CMOS technology parameters and the folded cascode (FC) technique employed in the differential input stage. The HSPICE simulation results demonstrate that the overall gain is 73.1dB, the unity gain bandwidth is 14.9MHz, the phase margin is , the total power dissipation is 0.91mW, the output voltage swing

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Hayder, Khaleel AL-Qaysi, Mohammed Jasim Musaab, and Manhal Hameed Siraj. "Design of very low-voltages and high-performance CMOS gate-driven operational amplifier." Indonesian Journal of Electrical Engineering and Computer Science 20, no. 2 (2020): 670–79. https://doi.org/10.11591/ijeecs.v20.i2.pp670-679.

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This paper presents the description and analysis of the design and HSPICEbased simulation results of very low-voltages (LVs) power supplies and highperformance specifications CMOS gate-driven (GD) operational amplifier (OpAmp) circuit. The very LVs CMOS GD Op-Amp circuit designed using 90nm CMOS technology parameters and the folded cascode (FC) technique employed in the differential input stage. The HSPICE simulation results demonstrate that the overall gain is 73.1dB, the unity gain bandwidth is 14.9MHz, the phase margin is , the total power dissipation is 0.91mW, the output voltage swing is

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30

WAWRYN, KRZYSZTOF. "AN ARTIFICIAL INTELLIGENCE APPROACH TO ANALOG CIRCUIT DESIGN." Journal of Circuits, Systems and Computers 01, no. 02 (1991): 149–76. http://dx.doi.org/10.1142/s0218126691000033.

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This article deals with a new approach to an intelligent analog circuit design. The iterative closed loop design methodology adopts an expert system approach to provide topological synthesis, the SPICE circuit simulator to evaluate the circuit performance and a new approach of the diagnostic expert system to provide advice on how to improve the design. Unlike previous design methods, this approach introduces formal circuit representation for both numerical and heuristic knowledge of the design system. The predicate logic circuit representation is proposed to introduce a new concept of a formal

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Mirković, Dejan D., Predrag M. Petković, Ilija Dimitrijević, and Igor Mirčić. "Operational Transconductance Amplifier in 350nm CMOS technology." Electronics ETF 19, no. 1 (2015): 32. http://dx.doi.org/10.7251/els1519032m.

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This paper presents transistor level design ofoperational transconductance amplifier in CMOS technology.Custom designed, circuit is to be built-in into the mixed-signal,switched capacitor circuit. Amplifier targets relatively high slewrateand moderate open loop gain with megahertz order gainbandwidth.Adopted architecture is discussed appreciatingapplication in switched capacitor circuits. Circuit behavior isexamined through set of simulations. Obtained results confirmeddesired behavior. Target technology process is TSMC 350nm.

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Setiabudi, Agung, Hiroki Tamura, and Koichi Tanno. "High Speed and Low Pedestal Error Bootstrapped CMOS Sample and Hold Circuit." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 6 (2018): 4148. http://dx.doi.org/10.11591/ijece.v8i6.pp4148-4156.

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<p>A new high speed, low pedestal error bootstrapped CMOS sample and hold (S/H) circuit is proposed for high speed analog-to-digital converter (ADC). The proposed circuit is made up of CMOS transmission gate (TG) switch and two new bootstrap circuits for each transistor in TG switch. Both TG switch and bootstrap circuits are used to decrease channel charge injection and on-resistance input signal dependency. In result, distortion can be reduced. The decrease of channel charge injection input signal dependency also makes the minimizing of pedestal error by adjusting the width of NMOS and

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Setiabudi, Agung, Hiroki Tamura, and Koichi Tanno. "High Speed and Low Pedestal Error Bootstrapped CMOS Sample and Hold Circuit." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 6 (2018): 4148–56. https://doi.org/10.11591/ijece.v8i6.pp4148-4156.

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A new high speed, low pedestal error bootstrapped CMOS sample and hold (S/H) circuit is proposed for high speed analog-to-digital converter (ADC). The proposed circuit is made up of CMOS transmission gate (TG) switch and two new bootstrap circuits for each transistor in TG switch. Both TG switch and bootstrap circuits are used to decrease channel charge injection and on-resistance input signal dependency. In result, distortion can be reduced. The decrease of channel charge injection input signal dependency also makes the minimizing of pedestal error by adjusting the width of NMOS and PMOS of T

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Kumar, Manish, Md Anwar Hussain, and Sajal K. Paul. "Effective Circuit Design Methodologies for Standby Leakage Power Reduction." Advanced Science, Engineering and Medicine 12, no. 2 (2020): 168–72. http://dx.doi.org/10.1166/asem.2020.2484.

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This paper presents circuit level design methodologies for significantly reducing the standby leakage power. Layout of different CMOS logic circuits such as a 2-input XOR, a 2-input XNOR, and a 4-input XNOR are designed and simulated by using BSIM4 MOS transistor model parameters. Layout simulations are done at a supply voltage of 0.4 V in 45 nm CMOS technology. Logic circuits designed by using the proposed circuit design methodologies proved to be effective in minimizing the standby leakage power. All layout design and simulation of the circuits are carried out by using Microwind EDA software

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O, K. K., S. SANKARAN, C. CAO, et al. "MILLIMETER WAVE TO TERAHERTZ IN CMOS." International Journal of High Speed Electronics and Systems 19, no. 01 (2009): 55–67. http://dx.doi.org/10.1142/s0129156409006084.

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The feasibility of CMOS circuits operating at frequencies in the upper millimeter wave and low sub-millimeter frequency regions has been demonstrated. A 140-GHz fundamental mode VCO in 90-nm CMOS, a 410-GHz push-push VCO in 45-nm CMOS, and a 180-GHz detector circuit in 130-nm CMOS have been demonstrated. With the continued scaling of MOS transistors, 1-THz CMOS circuits will be possible. Though these results are significant, output power of signal generators must be increased and acceptable noise performance of detectors must be achieved in order to demonstrate the applicability of CMOS for im

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Lee, Hyung K., and Dong S. Ha. "An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits." VLSI Design 2, no. 3 (1994): 199–207. http://dx.doi.org/10.1155/1994/71941.

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In this paper, we describe a highly efficient automatic test pattern generator for stuck-open (SOP) faults, called SOPRANO, in CMOS combinational circuits. The key idea of SOPRANO is to convert a CMOS circuit into an equivalent gate level circuit and SOP faults into the equivalent stuck-at faults. Then SOPRANO derives test patterns for SOP faults using a gate level test pattern generator. Several techniques to reduce the test set size are introduced in SOPRANO. Experimental results performed on eight benchmark circuits show that SOPRANO achieves high SOP fault coverage and short processing tim

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GABARA, THAD. "PULSED LOW POWER CMOS." International Journal of High Speed Electronics and Systems 05, no. 02 (1994): 159–77. http://dx.doi.org/10.1142/s0129156494000097.

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A simple CMOS circuit technique called PPS (Pulsed Power Supply) CMOS is used to reduce the power dissipation of Conventional 0.9 μm CMOS by 10X when operated at 32 MHz. Combinational and sequential logic can utilize this technique including the I/O (input/output) buffers. Thus, PPS CMOS offers a full chip solution for low power dissipation CMOS. In addition, several advantages occur in this new circuit technique: (1) low power signal propagation through several gates in series can occur during each evaluation cycle; (2) crowbar current does not occur; (3) additional placed devices, i.e. bipol

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Cai, Houzhi, Zhaoyang Xie, Youlin Ma, and Lijuan Xiang. "A 209 ps Shutter-Time CMOS Image Sensor for Ultra-Fast Diagnosis." Sensors 25, no. 12 (2025): 3835. https://doi.org/10.3390/s25123835.

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A conventional microchannel plate framing camera is typically utilized for inertial confinement fusion diagnosis. However, as a vacuum electronic device, it has inherent limitations, such as a complex structure and the inability to achieve single-line-of-sight imaging. To address these challenges, a CMOS image sensor that can be seamlessly integrated with an electronic pulse broadening system can provide a viable alternative to the microchannel plate detector. This paper introduces the design of an 8 × 8 pixel-array ultrashort shutter-time single-framing CMOS image sensor, which leverages sili

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FLYNN, MICHAEL P., SUNGHYUN PARK, and CHUN C. LEE. "ACHIEVING ANALOG ACCURACY IN NANOMETER CMOS." International Journal of High Speed Electronics and Systems 15, no. 02 (2005): 255–75. http://dx.doi.org/10.1142/s0129156405003193.

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This paper reviews causes of and trends in MOS transistor mismatch, and assesses the implications for analog circuit design in the nanometer régime. The current understanding of MOS transistor mismatch is reviewed. In most cases, transistor mismatch is dominated by threshold voltage mismatch. Although, there is strong evidence that VT matching is improving as CMOS technology evolves, these improvements are countered by reductions in power supply that also accompany process scaling. In fact, the power consumption of analog circuits based on current design styles will increase with scaling to fi

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Shokrani, Mohammad Reza, Mojtaba Khoddam, Mohd Nizar B. Hamidon, Noor Ain Kamsani, Fakhrul Zaman Rokhani, and Suhaidi Bin Shafie. "An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor." Scientific World Journal 2014 (2014): 1–11. http://dx.doi.org/10.1155/2014/963709.

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This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier’s output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is expl

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Kompitaya, Pantre, and Khanittha Kaewdang. "An Ultra-Low-Voltage Low-Power Current-Mode True RMS-to-DC Converter." Journal of Circuits, Systems and Computers 25, no. 06 (2016): 1650066. http://dx.doi.org/10.1142/s0218126616500663.

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A current-mode CMOS true RMS-to-DC (RMS: root-mean-square) converter with very low voltage and low power is proposed in this paper. The design techniques are based on the implicit computation and translinear principle by using CMOS transistors that operate in the weak inversion region. The circuit can operate for two-quadrant input current with wide input dynamic range (0.4–500[Formula: see text]nA) with an error of less than 1%. Furthermore, its features are very low supply voltage (0.8[Formula: see text]V), very low power consumption ([Formula: see text]0.2[Formula: see text]nW) and low circ

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Kushwaha, Dinesh, and D. K. Mishra. "Nano Power Current Reference Circuit consisting of Sub-threshold CMOS Circuits." Circulation in Computer Science 2, no. 1 (2017): 1–4. http://dx.doi.org/10.22632/ccs-2016-251-36.

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This paper proposes a low voltage CMOS Nano power current reference circuit and presents its performance with circuit simulation in 180- nm UMC CMOS technology. The proposed circuit consists of start-up, Bias-voltage, current-source sub-circuits with most of the MOSFETs operating in sub-threshold region. Simulation results shows that the circuit generates a stable reference current of 4-nA in supply voltage range 1 V- 1.8 V with line sensitivity of 0.203%/V.The temperature coefficient of the current was 7592ppm/°C at 1.8 V in the range of 0°C-100°C. The power dissipation was 380 NW at 1.8 V Su

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Maheshwari, Sudhanshu. "Realization of Simple Electronic Functions Using EXCCII." Journal of Circuits, Systems and Computers 26, no. 11 (2017): 1750171. http://dx.doi.org/10.1142/s0218126617501717.

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The paper presents a simple circuit for the realization of two digital modulation schemes: BPSK and ASK simultaneously, with the advantage of high input impedance at the signal input nodes and use of grounded resistors. The new circuits are based on the use of extra-[Formula: see text] current conveyor. Detailed analysis is given and circuit verification is carried out through simulations with a supply voltage of [Formula: see text][Formula: see text]V and [Formula: see text]m CMOS parameters to support the proposed circuit. Nonideal study is also given. An extended application of the circuit

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Upadhyay, Shipra, R. A. Mishra, R. K. Nagaria, and S. P. Singh. "DFAL: Diode-Free Adiabatic Logic Circuits." ISRN Electronics 2013 (February 10, 2013): 1–12. http://dx.doi.org/10.1155/2013/673601.

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The manufacturing advances in semiconductor processing (continually reducing minimum feature size of transistors, increased complexity and ever increasing number of devices on a given IC) change the design challenges for circuit designers in CMOS technology. The important challenges are low power high speed computational devices. In this paper a novel low power adiabatic circuit topology is proposed. By removing the diode from the charging and discharging path, higher output amplitude is achieved and also the power dissipation of the diodes is eliminated. A mathematical expression has been dev

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Tripathi, S. K., Mohd Samar Ansari, and Amit M. Joshi. "Carbon Nanotubes-Based Digitally Programmable Current Follower." VLSI Design 2018 (January 17, 2018): 1–10. http://dx.doi.org/10.1155/2018/1080817.

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The physical constraints of ever-shrinking CMOS transistors are rapidly approaching atomistic and quantum mechanical limits. Therefore, research is now directed towards the development of nanoscale devices that could work efficiently in the sub-10 nm regime. This coupled with the fact that recent design trend for analog signal processing applications is moving towards current-mode circuits which offer lower voltage swings, higher bandwidth, and better signal linearity is the motivation for this work. A digitally controlled DVCC has been realized using CNFETs. This work exploited the CNFET’s pa

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Agung, Setiabudi, Tamura Hiroki, and Tanno Koichi. "CMOS Temperature Sensor with Programmable Temperature Range for Biomedical Applications." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 2 (2018): 946–53. https://doi.org/10.11591/ijece.v8i2.pp946-953.

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A CMOS temperature sensor circuit with programmable temperature range is proposed for biomedical applications. The proposed circuit consists of temperature sensor core circuit and programmable temperature range digital interface circuit. Both circuits are able to be operated at 1.0 V. The proposed temperature sensor circuit is operated in weak inversion region of MOSFETs. The proposed digital interface circuit converts current into time using Current-to-Time Converter (ITC) and converts time to digital data using counter. Temperature range can be programmed by adjusting pulse width of the trig

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Sadhana, Sharma1 Abhay Vidyarthi2 and Shyam Akashe3. "A RAIL-TO-RAIL HIGH SPEED CLASS-AB CMOS BUFFER WITH LOW POWER AND ENHANCED SLEW RATE." International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013 4, no. 3 (2019): 01–12. https://doi.org/10.5281/zenodo.3349854.

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A rail-to-rail class-AB CMOS buffer is proposed in this paper to drive large capacitive loads. A new technique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamic power dissipation .The name of applied technique is LECTOR, which gives the high speed buffer with the reduced low power dissipation (1.05%) and reduced area (2.8%). The proposed buffer is simulated at 45nm CMOS technology and the circuit is operated at 3V supply with cadence software. This analog circuit is performed with extremely low leakage current as well as high current driving capabil

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Xiang-jie, Niu, and Li Hua. "Lower Power Design for UHF RF CMOS Circuits Based on the Power Consumption Acuity." Mathematical Problems in Engineering 2014 (2014): 1–8. http://dx.doi.org/10.1155/2014/512398.

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Excessive energy consumption of UHF tag is the bottleneck of energy saving in its wide range of applications. To address this issue, a lower power design for UHF RF CMOS circuits based on power consumption acuity is proposed in this paper. Through in-depth analysis of the static and dynamic power generation principle of UHF RF circuits in the work, the power consumption acuity can be calculated by using the correlation of circuit power and input vector. Subsequently, under the guide of this acuity, the UHF RF CMOS circuits with better energy saving can be designed. Furthermore, according to th

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Lau, K. T., W. Y. Wang, and K. W. Ng. "Adiabatic-CMOS/CMOS-adiabatic logic interface circuit." International Journal of Electronics 87, no. 1 (2000): 27–32. http://dx.doi.org/10.1080/002072100132417.

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Soeleman, H., K. Roy, and Tan-Li Chou. "Estimating circuit activity in combinational CMOS digital circuits." IEEE Design & Test of Computers 17, no. 2 (2000): 112–19. http://dx.doi.org/10.1109/54.844340.

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