Relevant bibliographies by topics / Design Rule Check (DRC)

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Design Rule Check (DRC)'

Author: Grafiati
Published: 2 June 2025
Last updated: 31 July 2025

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Journal articles on the topic "Design Rule Check (DRC)"

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Nandy, S. K. "Geometric Design Rule Check of VLSI Layouts in Distributed Computing Environment." VLSI Design 1, no. 2 (1994): 155–67. http://dx.doi.org/10.1155/1994/54126.

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In this paper we provide a distributed solution to perform Design Rule Checking (DRC) of a layout by exploiting either spatial independence or layer independence in layout data. We show that the former approach to DRC can result in reasonable speedup only for large layouts, whereas, the latter approach shows a better performance for smaller layouts. We also provide an algorithm to optimally partition a layout and a scheme to allocate DRC tasks to idle processors in a Distributed Computing Environment (DCE) to attain load balancing.
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Nandy, S. K., and R. B. Panwar. "Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors." VLSI Design 1, no. 2 (1994): 127–54. http://dx.doi.org/10.1155/1994/96830.

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Design Rule Checking is a compute-intensive VLSI CAD tool. In this paper we propose a parallel algorithm to perform Design Rule Check (DRC) of Layout geometries in a VLSI layout. The algorithm assumes the parallel architecture to be a two-dimensional mesh of processors. The algorithm is based on a linear quadtree representation of the layout. Through a complexity analysis it is shown that it is possible to achieve a linear speedup in DRC with respect to the number of processors.
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Luo, Zhen, Margaret Martonosi, and Pranav Ashar. "An Edge-endpoint-based Configurable Hardware Architecture for VLSI Layout Design Rule Checking." VLSI Design 10, no. 3 (2000): 249–63. http://dx.doi.org/10.1155/2000/71046.

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Previous efforts to build hardware accelerators for VLSI layout Design Rule Checking (DRC) were hobbled by the fact that it is often impractical to build a different rulechecking ASIC each time design rules or fabrication processes change. In this paper, we propose a configurable hardware approach to DRC. It can garner impressive speedups over software approaches, while retaining the flexibility needed to change the rule checker as rules or processes change.Our work proposes an edge-endpoints-based method for performing Manhattan geometry checking and a general scalable architecture for DRC. W
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Rajapriyadharshini, B., V. Renisha, S. Shivani, Kumar S. Bharath, and P. Latha. "Analog / Full Custom IC Design of Wilson Current Mirror." International Journal of Microsystems and IoT 2, no. 12 (2024): 1440–46. https://doi.org/10.5281/zenodo.15455573.

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This paper presents the design and implementation of an analog integrated circuit (IC) based on the Wilson current mirror topology. The design process was carried out using the Cadence Virtuoso tool suite. The initial phase involved creating the schematic in the Schematic Editor and generating a corresponding symbol to represent the circuit. A test bench was subsequently constructed using this symbol to enable simulation and performance evaluation. Input and output waveforms were obtained and analyzed to validate the functionality of the design. Additionally, the layout was generated and modif
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Jun, Shi. "Deep sub-micron ESD GGNMOS layout design and optimization." MATEC Web of Conferences 198 (2018): 04009. http://dx.doi.org/10.1051/matecconf/201819804009.

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In the field of integrated circuits, ESD (Electro Static Discharge) has always been a rather serious problem of reliability. Enhanced ESD tolerance of IC chips became a focus of research on IC failure protection design. The thesis is better to solve the multi-fingered non-uniform conduction of ESD devices under electrostatic pulse. Layout parameters DCGS (Drain-Contact to Gate Spacing), SCGS (Source-Contact to Gate Spacing) and BS (Substrate-source spacing) size in the paper can be used as reference for ESD GGNMOS (Gated Ground NMOS) layout design. Also this paper provides setting the DRC (Des
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Huang, Chih-Yi, Lihong Cao, Keng-Tuan Chang, and Chen-Chao Wang. "High Density Package Design Platform and Assembly Design Kit." International Symposium on Microelectronics 2021, no. 1 (2021): 000234–38. http://dx.doi.org/10.4071/1085-8024-2021.1.000234.

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Abstract With the miniaturization of integrated circuit technology and process, chips are getting smaller and smaller, and thus it results in fan-out packaging with RDL process was derived to extend the ball grid array design space. The applicable range of RDL now includes products in the fields of Networking, HPC, AI and even SiPh. And the new package types comprised of the RDL process include e-WLB, chip first FOCoS, chip last FOCoS, FO-PoP and 2.5D IC etc. The total pin count in FOCoS packaging can be more than ten times than that the pin counts in a large FCBGA packaging; the FOCoS package
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Белявцев, А. В., А. В. Русанов, and Т. С. Шайкина. "RC OSCILLATOR FOR A DOMESTIC TECHNOLOGICAL PROCESS." ВЕСТНИК ВОРОНЕЖСКОГО ГОСУДАРСТВЕННОГО ТЕХНИЧЕСКОГО УНИВЕРСИТЕТА 20, no. 1 (2024): 45–50. http://dx.doi.org/10.36622/1729-6501.2024.20.1.007.

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предложен сложно-функциональный (СФ/IP) блок RC-генератора, построенный на МОП-транзисторах. Генератор является блоком тактирования для большого числа электронных устройств, не требовательных к стабильности частоты, но чувствительных к размеру. Данный блок предназначен для применения в составе интегральных схем стабилизаторов напряжения. Приведено описание электрической схемы генератора, его основные электрические характеристики и результаты моделирования (зависимости частоты генератора и его тока потребления от температуры и напряжения питания схемы, получены значения нестабильности частоты и
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Белявцев, А. В., А. В. Русанов та Д. О. Лялин. "СФ‑БЛОКИ ПРИЕМНИКА И ПЕРЕДАТЧИКА LVDS ДЛЯ ТЕХНОЛОГИЧЕСКОГО ПРОЦЕССА 180 НМ". ВЕСТНИК ВОРОНЕЖСКОГО ГОСУДАРСТВЕННОГО ТЕХНИЧЕСКОГО УНИВЕРСИТЕТА 21, № 1 (2025): 107–13. https://doi.org/10.36622/1729-6501.2025.21.1.016.

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представлены два сложно-функциональных (СФ/IP) блока для интегральных схем: приемник и передатчик низковольтной дифференциальной передачи сигналов (Low voltage differntial signal - LVDS). Раздел статьи, посвященный передатчику LVDS, содержит подробное описание структурной схемы СФ‑блока и электрических схем его составных частей, результаты моделирования, временные диаграммы работы и основные электрические параметры устройства. Отдельное внимание уделено особенностям схемотехнических решений, использованных при проектировании. Раздел, посвященный СФ‑блоку приемника LVDS, содержит краткое описан
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Poluektov, Aleksandr, Dmitriy Shehovcov, I. Skorkin, and Pavel Chubunov. "Integrating the Calibre software product into the Cadence Virtuoso environment and increasing the intelligent properties of CAD IC design." Modeling of systems and processes 16, no. 4 (2023): 71–80. http://dx.doi.org/10.12737/2219-0767-2023-16-4-71-80.

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The article discusses the technology for integrating Caliber into the Cadence Virtuoso environment and describes the impact of this integration on the productivity of engineers. The possibility of ensuring optimal interaction between developers and increasing the overall efficiency of the design team is considered, leading to end-to-end design optimization. The integration of Caliber and Cadence Virtuoso represents an important step in Electronic Design Development (EDA) and can solve a number of problems while improving the efficiency of the verification and analysis process. Here are a few a
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Русанов, А. В., Л. В. Сопина, and А. В. Бунина. "BANDGAP REFERENCE VOLTAGE SOURCE FOR A DOMESTIC TECHNOLOGICAL PROCESS." ВЕСТНИК ВОРОНЕЖСКОГО ГОСУДАРСТВЕННОГО ТЕХНИЧЕСКОГО УНИВЕРСИТЕТА 19, no. 4 (2023): 71–76. http://dx.doi.org/10.36622/vstu.2023.19.4.009.

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предложены два сложнофункциональных (СФ/IP) блока операционных усилителей (ОУ), построенных на n-канальной и р-канальной дифференциальных парах. ОУ являются универсальными блоками, на основе которых можно построить множество различных электронных узлов. В настоящее время ОУ получили широкое применение как в виде отдельных чипов, так и в виде IP-блоков в составе более сложных интегральных схем. Разработанные IP-блоки ОУ предназначены для применения в интегральных схемах линейных стабилизаторов напряжения в качестве усилителей ошибки. В стабилизаторах напряжения усилитель ошибки выполняет ключев
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Dissertations / Theses on the topic "Design Rule Check (DRC)"

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Antunes, Flávio da Cunha. "Prevenção de riscos na fase de projeto com recurso à metodologia BIM." Master's thesis, Universidade de Aveiro, 2016. http://hdl.handle.net/10773/18044.

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Mestrado em Engenharia Civil<br>A utilização da metodologia BIM tem vindo a aumentar no setor da AEC, implicando um novo paradigma de trabalho, com o uso de modelos tridimensionais paramétricos. No entanto, as vantagens desta metodologia não têm sido utilizadas pelos projetistas para a prevenção de riscos profissionais e para o planeamento das respetivas medidas de segurança, tendo em consideração que na fase de projeto se tem o maior potencial para aplicar eliminar/minimizar os perigos e, consequentemente influenciar a segurança em obra e nas fases posteriores à sua conclusão. Apoiado na rev
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Book chapters on the topic "Design Rule Check (DRC)"

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Meier, W. "Hierarchical Netlist Extraction and Design Rule Check." In Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme. Springer Berlin Heidelberg, 1990. http://dx.doi.org/10.1007/978-3-642-84304-4_2.

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Meier, W. "Hierarchical Design Rule Check for Full Custom Designs." In Esprit ’89. Springer Netherlands, 1989. http://dx.doi.org/10.1007/978-94-009-1063-8_11.

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Ng, Wan Yeen, and Xhiang Rhung Ng. "The Design and Modeling of 30 GHz Microwave Front-End." In Advances in Monolithic Microwave Integrated Circuits for Wireless Systems. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-60566-886-4.ch009.

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This chapter aims to discuss a millimeter wave integrated circuit (MMWIC) in frequency of 30 GHz especially switch (SPDT), medium power amplifier (MPA) and low noise amplifier (LNA). The switch is developed using a commercial 0.15 µm GaAs pHEMT technology. It achieves low loss and high isolation for millimeter wave applications. The circuit and layout drawing of SPDT switch are done by using Advanced Design System (ADS) software. The layout is verified by running the Design Rules Check (DRC) to check and clear all the errors. At the operating frequency of 30 GHz, the reported SPDT switch has 1
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Parau, Cristina E. "Thesis and antithesis: To check or not to check the Judiciary." In Transnational Networking and Elite Self-Empowerment. British Academy, 2018. http://dx.doi.org/10.5871/bacad/9780197266403.003.0005.

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This chapter analyses Network Community discourses in order to better expose the causal role of its hegemonic norms. Key assumptions held by the Community about the qualities of their agenda are brought to light. Classical Anglo-Saxon conceptions of the separation of powers, checks and balances, judicial independence, and the rule of law, the utility of which has stood the test of time, are compared to the theory and practice of the Network Community’s Judiciary institutional design Template. The Network conceives of the separation of powers, checks and balances, judicial independence, and the
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Singh, Asheesh K., and Rambir Singh. "Power Quality Improvement using Improved Approximated Fuzzy Logic Controller for Shunt Active Power Filter." In Advances in Systems Analysis, Software Engineering, and High Performance Computing. IGI Global, 2014. http://dx.doi.org/10.4018/978-1-4666-6098-4.ch011.

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This chapter presents the design approach of an Improved Approximated Simplest Fuzzy Logic Controller (IASFLC). A cascade combination of simplest 4-rule Fuzzy Logic Controller (FLC) and an nth degree polynomial is proposed as an IASFLC to approximate the control characteristics of a 49-rule FLC. The approximation scheme is based on minimizing the sum of square errors between the control outputs of a 49-rule FLC and a simplest 4-rule FLC in the entire range of Universe Of Discourse (UOD). The coefficients of compensating polynomial are evaluated by solving instantaneous square error equations a
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Panigrahi, Niranjan. "An Expert System-Assisted AI Approach for Awareness and Prevention of Crimes against Women in India." In Advancements in Artificial Intelligence and Machine Learning. BENTHAM SCIENCE PUBLISHERS, 2025. https://doi.org/10.2174/9789815322583125010013.

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The incorporation of Artificial Intelligence (AI) and its sub-domains for women's safety and security is a major requirement in the present technology-driven world. Most of the works in this context focus on leveraging Machine Learning (ML) technologies to predict harassment, violence, and other women-related crimes. However, ML approaches are mostly data-driven. In many poor and developing countries like India, where criminals’ data are not well-documented and publicly unavailable, other alternative ways must be planned to prevent crimes against women. One feasible way is to spread awareness
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Gams, Matjaz, and Matej Ozek. "Use of Data Mining Techniques for Process Analysis on Small Databases." In Dynamic and Advanced Data Mining for Progressing Technological Development. IGI Global, 2010. http://dx.doi.org/10.4018/978-1-60566-908-3.ch017.

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The pharmaceutical industry was for a long time founded on rigid rules. With the new PAT initiative, control is becoming significantly more flexible. The Food and Drug Administration is even encouraging the industry to use methods like machine learning. The authors designed a new data mining method based on inducing ensemble decision trees from which rules are generated. The first improvement is specialization for process analysis with only a few examples and many attributes. The second innovation is a graphical module interface enabling process operators to test the influence of parameters on
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Conference papers on the topic "Design Rule Check (DRC)"

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Wang, Lynn T. N., Fadi Batarseh, Ivan Tanev, et al. "Machine learning-assisted pattern optimizations for fixing design for manufacturability (DFM) rule check violations." In DTCO and Computational Patterning IV, edited by Neal V. Lafferty and Harsha Grunes. SPIE, 2025. https://doi.org/10.1117/12.3051488.

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Zhou, Yifei, Zijian Wang, and Chao Wang. "E2E-Check: End to End GPU-Accelerated Design Rule Checking with Novel Mask Boolean Algorithms." In 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 2024. http://dx.doi.org/10.1109/asp-dac58780.2024.10473843.

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Godovitsyn, Maxim, Julia Zhivchikova, Nickolay Starostin, and Anton Shtanyuk. "Algorithm for Implementing Logical Operations on Sets of Orthogonal Polygons." In 31th International Conference on Computer Graphics and Vision. Keldysh Institute of Applied Mathematics, 2021. http://dx.doi.org/10.20948/graphicon-2021-3027-1088-1097.

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As part of the development CAD for design rule checks (DRC), it is necessary to use logical operations on orthogonal polygons that form the layout of an integrated circuit. Such operations as union, intersection, subtraction are performed over layers that contain orthogonal polygons. These operations are subject to stringent execution time requirements. The traditional representation of polygons in the form of bitmaps does not provide a quasi-linear dependence of time on the processed data size and requires development of new algorithms and polygon representation approaches. This paper contain
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Shang, Shumay, Hongxin Zhang, Rui Wu, et al. "Combinational optical rule check on hotspot detection." In Design-Process-Technology Co-optimization for Manufacturability XII, edited by Jason P. Cain and Chi-Min Yuan. SPIE, 2018. http://dx.doi.org/10.1117/12.2297425.

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Iov, Catalin J., and Mihaela Hnatiuc. "Design Rule Checking. Current Challenges Approached With HyperLynx DRC." In 2018 IEEE 24th International Symposium for Design and Technology in Electronic Packaging (SIITME). IEEE, 2018. http://dx.doi.org/10.1109/siitme.2018.8599277.

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Kundu, Santanu, Chetan Suryakant Padharia, and Ravi Sankar Kerla. "MLTDRC: Machine Learning Driven Faster Timing Design Rule Check Convergence." In 2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID). IEEE, 2023. http://dx.doi.org/10.1109/vlsid57277.2023.00047.

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Matsuyama, Takayoshi, Kenichi Kobayashi, Daikichi Awamura, Katsuyoshi Nakashima, and Yasunori Hada. "Novel inspection system with design rule check for high-accuracy reticles." In Photomask and X-Ray Mask Technology VI, edited by Hiroaki Morimoto. SPIE, 1999. http://dx.doi.org/10.1117/12.360228.

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Tsai, Kun-Han, and Shuo Sheng. "Design rule check on the clock gating logic for testability and beyond." In 2013 IEEE International Test Conference (ITC). IEEE, 2013. http://dx.doi.org/10.1109/test.2013.6651930.

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Saito, Shoko, Masaru Miyazaki, Mitsuo Sakurai, et al. "A study of applications scribe frame data verifications using design rule check." In Photomask and NGL Mask Technology XX, edited by Kokoro Kato. SPIE, 2013. http://dx.doi.org/10.1117/12.2028330.

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Pettazzi, Stefano, Andrew Plews, Anatoly Rudenko, and Ahmed Nejim. "Development of 3D space partitioning and design rule check for smart system solutions." In 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE, 2014. http://dx.doi.org/10.1109/ddecs.2014.6868755.

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