Academic literature on the topic 'DIGITAL SYSTEM DESIGN TEST AND VERIFICATION'

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Journal articles on the topic "DIGITAL SYSTEM DESIGN TEST AND VERIFICATION"

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Wei, Chi Pin, Zhao Lin Li, Hao Liu, and Zhi Xiang Chen. "Design of a Random Test Platform for DSP Serials Used in Embedded Systems." Advanced Materials Research 267 (June 2011): 98–103. http://dx.doi.org/10.4028/www.scientific.net/amr.267.98.

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Embedded systems with digital signal processor (DSP) become more and more popular for the increasing requirement of supercomputing these days. Efficient development of DSP serials used in embedded systems shortens the embedded system R&D cycle. Functional verification is one of the most complex and expensive tasks during DSP serials design process. A random test platform which is urged for DSP serials verification is proposed in this paper. The platform can automatically generate the random test program. The platform also realized the recording and checking of simulation results, which mak
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Sandi, Anuradha. "VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH." International Journal of Engineering Technologies and Management Research 6, no. 6 (2020): 40–50. http://dx.doi.org/10.29121/ijetmr.v6.i6.2019.392.

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In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The performance depends on power consumption and delay. Adders are not only used for arithmetic operations, but also for calculating addresses and indices. In digital design we have half adder and full adder, by using these adders we can implement ripple carry adder (RCA). RCA is used to perform any number of additions. In this RCA is serial adder and it has propagation delay problem. With increas
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Dr., Anuradha M. Sandi. "VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH." International Journal of Engineering Technologies and Management Research 6, no. 6 (2019): 40–50. https://doi.org/10.5281/zenodo.3245207.

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In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The performance depends on power consumption and delay. Adders are not only used for arithmetic operations, but also for calculating addresses and indices. In digital design we have half adder and full adder, by using these adders we can implement ripple carry adder (RCA). RCA is used to perform any number of additions. In this RCA is serial adder and it has propagation delay problem. With increas
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Sharma, N., P. Kumar, N. Singh, and U. Mehta. "Digital energy monitor: design, simulations and prototype." South Pacific Journal of Natural and Applied Sciences 35, no. 2 (2017): 45. http://dx.doi.org/10.1071/sp17005.

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This paper demonstrates the design and implementation of a GSM based digital energy monitoring device. Firstly fuzzy based model is developed to replicate the characteristic of current and voltage sensors. The entire system is also studied and simulated in terms of utility side supply, load, microcontroller digitization and GSM communication. A virtual data sharing technic is also studied for the proposed system using state flow logic. A prototype system is verified real-time with its test and verification phase results. In this work, remote monitoring of electricity has been made easier for t
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Chen, Fu Long, Zhao Xia Zhu, and Xiao Ya Fan. "FPGA-Based In-Circuit Verification of Digital Systems." Advanced Materials Research 187 (February 2011): 362–67. http://dx.doi.org/10.4028/www.scientific.net/amr.187.362.

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In general hardware designers design integrated circuit with hardware description languages or schematic diagram. However the growth of circuit complexity makes circuit design error prone and time consuming. The resulting descriptions tend to be lengthy and hard to reason about. Therefore functional simulation, timing simulation and in-circuit test are three essential steps to ensure that the designed circuit is correct. This paper presents a method of in-circuit verification on FPGA using UART communication between the computer and the FPGA board. Through UART, designers can convert the paral
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Zhang, Xu, Zhiguang Deng, Jun Li, Youwei Yang, Quan Ma, and Mingming Liu. "Design and Verification of Reactor Power Control Based on Stepped Dynamic Matrix Controller." Science and Technology of Nuclear Installations 2019 (November 3, 2019): 1–11. http://dx.doi.org/10.1155/2019/4973120.

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As key equipment in nuclear power plant, the reactor power control system is adopted to strictly control and regulate the reactor power of a PWR (pressurized water reactor) in a nuclear power plant. A well-optimized predictive control algorithm based on SDMC (stepped dynamic matrix controller) is developed and introduced in this paper and applied to the power regulation of a reactor power model. In addition, the test and verification of this application is conducted by two different methods and devices: the virtual verification platform and the physical DCS (digital control system). The result
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Krebs, Andreas, and Jürgen Ruf. "Optimized Temporal Logic Compilation." JUCS - Journal of Universal Computer Science 9, no. (2) (2003): 120–37. https://doi.org/10.3217/jucs-009-02-0120.

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Verification and validation are the major tasks during the design of digital hardware/software systems. Often more than 70% of the development time is spent for locating and correcting errors in the design. Therefore, many techniques have been developed to support the debugging process. Recently, simulation and test methods have been accompanied by formal methods such as equivalence checking and property checking. However, their industrial applicability is currently restricted to small or medium sized designs or to a specific phase in the design process. Therefore, simulation is still the most
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Sun, Peng, Qi Shao, Ying Yu Liu, and Wei Ping Chen. "A New Method of Design and Verification of Digital Silicon Gyroscopes Closed-Loop Driving System Based on MicroBlaze." Key Engineering Materials 645-646 (May 2015): 771–76. http://dx.doi.org/10.4028/www.scientific.net/kem.645-646.771.

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The article brings out a digital silicon gyroscopes closed-loop driving system using the phase relationship of the input driving signal and the signal of the forced motion of the mass block in sensor structure based on analyzing the working principle and phase characters of digital silicon gyroscopes. We make a low-cost, simple and high precision measurement technique for resonant frequency of silicon micro-machinery gyroscopes by the whole digital locked loop system designed with MicroBlaze method. Dichotomy and Fourier transform spectrometry method constitute the algorithm of the system and
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Ramirez, Clara, and Amy Thompson. "Verification and Validation Test Framework Using a Model‐Based Systems Engineering Approach." INCOSE International Symposium 33, no. 1 (2023): 1091–116. http://dx.doi.org/10.1002/iis2.13072.

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AbstractThis paper describes a test framework for verification and validation (V&V) planning and execution using a model‐based system engineering (MBSE) approach that is suitable for large‐scale cyber‐physical systems. The test framework (TF) is defined using the systems modeling language (SysML) and an MBSE tool and describes and links to external test plans, test procedures, and other relevant test documents. This test framework approach includes the following considerations: level of abstraction of systems for testing, multiple types of testing across the development lifecycle, design v
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Wang, Jianyuan, Zhuochen Hu, Jinbao Chen, Jian Wang, and Yiling Zhou. "Design and Signal-Decoding Test Verification of Dual-Channel Round Inductosyn Decoding Circuit." Applied Sciences 14, no. 21 (2024): 9801. http://dx.doi.org/10.3390/app14219801.

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During the in-orbit operation of spacecraft, permanent magnet synchronous motors are commonly used as power sources in the drive mechanisms of solar panel arrays and the high-precision servo control systems based on satellites. Apart from the performance of the motors themselves and the software control algorithms, the accuracy of the entire control system is also influenced by angle sensors used to detect the rotor position of the motors. As a high-precision angular measuring instrument, the inductosyn possesses excellent environmental adaptability and long service life. Effectively utilizing
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Dissertations / Theses on the topic "DIGITAL SYSTEM DESIGN TEST AND VERIFICATION"

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VALLERO, ALESSANDRO. "Cross layer reliability estimation for digital systems." Doctoral thesis, Politecnico di Torino, 2017. http://hdl.handle.net/11583/2673865.

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Forthcoming manufacturing technologies hold the promise to increase multifuctional computing systems performance and functionality thanks to a remarkable growth of the device integration density. Despite the benefits introduced by this technology improvements, reliability is becoming a key challenge for the semiconductor industry. With transistor size reaching the atomic dimensions, vulnerability to unavoidable fluctuations in the manufacturing process and environmental stress rise dramatically. Failing to meet a reliability requirement may add excessive re-design cost to recover and may have
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Zhou, Jing 1959. "LOVERD--a logic design verification and diagnosis system via test generation." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/291686.

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The development of cost-effective circuits is primarily a matter of economy. To achieve it, design errors and circuit flaws must be eliminated during the design process. To this end, considerable effort must be put into all phases of the design cycle. Effective CAD tools are essential for the production of high-performance digital systems. This thesis describes a CAD tool called LOVERD, which consists of ATPG, fault simulation, design verification and diagnosis. It uses test patterns, developed to detect single stuck-at faults in the gate-level implementation, to compare the results of the fun
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Kim, Seokjin. "High-speed analog-to-digital converters for modern satellite receivers design verification test and sensitivity analysis /." College Park, Md.: University of Maryland, 2008. http://hdl.handle.net/1903/7864.

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Thesis (Ph. D.) -- University of Maryland, College Park, 2008.<br>Thesis research directed by: Dept. of Electrical and Computer Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
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Bougan, Timothy B. "Flexible Intercom System Design for Telemetry Sites and Other Test Environments." International Foundation for Telemetering, 1996. http://hdl.handle.net/10150/611449.

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International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California<br>Testing avionics and military equipment often requires extensive facilities and numerous operators working in concert. In many cases these facilities are mobile and can be set up at remote locations. In almost all situations the equipment is loud and makes communication between the operators difficult if not impossible. Furthermore, many sites must transmit, receive, relay, and record telemetry signals. To facilitate communication, most telemetry and
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Ruddy, Marcus A. "Pico-Satellite Integrated System Level Test Program." DigitalCommons@CalPoly, 2012. https://digitalcommons.calpoly.edu/theses/688.

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Testing is an integral part of a satellite’s development, requirements verification and risk mitigation efforts. A robust test program serves to verify construction, integration and assembly workmanship, ensures component, subsystem and system level functionality and reduces risk of mission or capability loss on orbit. The objective of this thesis was to develop a detailed test program for pico-satellites with a focus on the Cal Poly CubeSat architecture. The test program established a testing baseline from which other programs or users could tailor to meet their needs. Inclusive of the tes
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Aalto, Alve, and Ali Jafari. "Automatic Probing System for PCB : Analysis of an automatic probing system for design verification of printed circuit boards." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-174865.

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The purpose of this thesis is to conduct an analysis of whether the printed circuit boards from Ericsson can be tested using an automatic probing system or what changes in the design are required, to be a viable solution. The main instrument used for analyzing the printed circuit board was an oscilloscope. The oscilloscope was used to get the raw data for plotting the difference between the theoretical and actual signals. Connected to the oscilloscope was a 600A-AT probe from LeCroy. The programs used for interpreting the raw data extracted from the oscilloscope included Python, Matlab and Exc
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Ioannides, Charalambos. "Investigating the potential of machine learning techniques for feedback-based coverage-directed test genreation in simulation-based digital design verification." Thesis, University of Bristol, 2013. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.618315.

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A consistent trend in the semiconductor industry has been the increase of embedded functionality in new designs. As a result, the verification process today requires significant resources to cope with these increasingly complex designs. In order to alleviate the problem, industrialists and academics have proposed and improved on many formal, simulation-based and hybrid verification techniques. To dale, none of the approaches proposed have been ab le to present a convincing argument warranting their unconditional adoption by the industry. In an attempt to further automate design verification (D
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Aluru, Gunasekhar. "Exploring Analog and Digital Design Using the Open-Source Electric VLSI Design System." Thesis, University of North Texas, 2016. https://digital.library.unt.edu/ark:/67531/metadc849770/.

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The design of VLSI electronic circuits can be achieved at many different abstraction levels starting from system behavior to the most detailed, physical layout level. As the number of transistors in VLSI circuits is increasing, the complexity of the design is also increasing, and it is now beyond human ability to manage. Hence CAD (Computer Aided design) or EDA (Electronic Design Automation) tools are involved in the design. EDA or CAD tools automate the design, verification and testing of these VLSI circuits. In today’s market, there are many EDA tools available. However, they are very expen
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Qiang, Qiang. "FORMAL a sequential ATPG-based bounded model checking system for VLSI circuits /." online version, 2006. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=case1144614543.

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Larsson, Erik. "An Integrated System-Level Design for Testability Methodology." Doctoral thesis, Linköpings universitet, ESLAB - Laboratoriet för inbyggda system, 2000. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-4932.

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HARDWARE TESTING is commonly used to check whether faults exist in a digital system. Much research has been devoted to the development of advanced hardware testing techniques and methods to support design for testability (DFT). However, most existing DFT methods deal only with testability issues at low abstraction levels, while new modelling and design techniques have been developed for design at high abstraction levels due to the increasing complexity of digital systems. The main objective of this thesis is to address test problems faced by the designer at the system level. Considering the te
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Books on the topic "DIGITAL SYSTEM DESIGN TEST AND VERIFICATION"

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Navabi, Zainalabedin. Digital System Test and Testable Design. Springer US, 2011. http://dx.doi.org/10.1007/978-1-4419-7548-5.

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Rashinkar, Prakash. System-On-A-Chip verification: Methodology and techniques. Kluwer Academic Publishers, 2002.

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1959-, Lavagno Luciano, Scheffer Lou, and Martin Grant, eds. EDA for IC system design, verification, and testing. Taylor & Francis, 2005.

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Rashinkar, Prakash. System-On-A-Chip verification: Methodology and techniques. Kluwer Academic Publishers, 2001.

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1955-, Paterson Peter, and Singh Leena 1971-, eds. System-On-A-Chip verification: Methodology and techniques. Kluwer Academic Publishers, 2001.

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Bergé, Jean-Michel. Hardware/Software Co-Design and Co-Verification. Springer US, 1997.

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Navabi, Zainalabedin. Digital System Test and Testable Design: Using HDL Models and Architectures. Springer Science+Business Media, LLC, 2011.

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IEEE International High-Level Design Validation and Test Workshop (6th 2001 Monterey, Calif.). Sixth IEEE International High-Level Design Validation and Test Workshop: Proceedings : 7-9 November, 2001. IEEE Computer Society, 2001.

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Calif.) IEEE International High-Level Design Validation and Test Workshop (8th 2003 San Francisco. Eighth IEEE International High-Level Design Validation and Test Workshop: Proceedings : 12-14 November, 2003, San Francisco, California. IEEE Computer Society, 2003.

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Center, Ames Research, ed. Digital-flight-control-system software written in automated-engineering-design language: A user's guide of verification and validation tools. National Aeronautics and Space Administration, Ames Research Center, 1988.

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Book chapters on the topic "DIGITAL SYSTEM DESIGN TEST AND VERIFICATION"

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Wang, Wei, Shuren Guo, Jun Lu, et al. "Design and Practice of Digital Test and Verification of BeiDou Navigation Satellite System." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-6928-9_44.

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Navabi, Zainalabedin. "Test Compression." In Digital System Test and Testable Design. Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-7548-5_10.

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Navabi, Zainalabedin. "Deterministic Test Generation Algorithms." In Digital System Test and Testable Design. Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-7548-5_6.

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Snider, Ross. "Chapter 8: Introduction to Verification." In Advanced Digital System Design using SoC FPGAs. Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-15416-4_8.

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Navabi, Zainalabedin. "Standard IEEE Test Access Methods." In Digital System Test and Testable Design. Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-7548-5_8.

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Navabi, Zainalabedin. "Logic Built-in Self-test." In Digital System Test and Testable Design. Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-7548-5_9.

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Navabi, Zainalabedin. "Verilog HDL for Design and Test." In Digital System Test and Testable Design. Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-7548-5_2.

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Navabi, Zainalabedin. "Test Pattern Generation Methods and Algorithms." In Digital System Test and Testable Design. Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-7548-5_5.

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Navabi, Zainalabedin. "Design for Test by Means of Scan." In Digital System Test and Testable Design. Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-7548-5_7.

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Navabi, Zainalabedin. "Basics of Test and Role of HDLs." In Digital System Test and Testable Design. Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-7548-5_1.

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Conference papers on the topic "DIGITAL SYSTEM DESIGN TEST AND VERIFICATION"

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Zhang, Huamin, Xiaoying Feng, Shan Jin, and Fuman Zhou. "Design and Verification of electronic signature system for power test reports." In 2024 8th International Conference on Electrical, Mechanical and Computer Engineering (ICEMCE). IEEE, 2024. https://doi.org/10.1109/icemce64157.2024.10862498.

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Kamath M, Shrinivas Anand, and Sujatha Hiremath. "Design and Verification of Power Efficient Built-In Self-Test." In 2024 8th International Conference on Computational System and Information Technology for Sustainable Solutions (CSITSS). IEEE, 2024. https://doi.org/10.1109/csitss64042.2024.10816809.

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Xiong, Huasheng, Duo Li, and Liangju Zhang. "Test Facility Design for Integrated Digital Nuclear Reactor Protection System." In 18th International Conference on Nuclear Engineering. ASMEDC, 2010. http://dx.doi.org/10.1115/icone18-29286.

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Reactor protection system is one of the most important safety systems in nuclear power plant and shall be designed with very high reliability. Digital computer-based Reactor Protection System (RPS) takes great advantages over its conventional counterpart based on analog technique and faces the issues how to effectively demonstrate and confirm the completeness and correctness of the software that performs reactor safety functions in the same time. It is commonly accepted that the essential way to solve safety software issues in a digital RPS is to pass a strict and independent Verification and
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Reza Kakoee, Mohammad, M. H. Neishaburi, and Siamak Mohammadi. "Functional Test-Case Generation by a Control Transaction Graph for TLM Verification." In 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007). IEEE, 2007. http://dx.doi.org/10.1109/dsd.2007.4341464.

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Triputra, Fadjar Rahino, Rifki Firdaus, Irfansyah Yudhi Tanasa, et al. "FPGA-Based Digital Circuit Design for UAV Pilot-in-Loop System with Field Test Verification." In 2023 6th International Seminar on Research of Information Technology and Intelligent Systems (ISRITI). IEEE, 2023. http://dx.doi.org/10.1109/isriti60336.2023.10467711.

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Hanada, Satoshi, Koji Ito, and Kenji Mashio. "US-APWR Human System Interface System Verification and Validation Program for Digital I&C Design." In 18th International Conference on Nuclear Engineering. ASMEDC, 2010. http://dx.doi.org/10.1115/icone18-29928.

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The US-APWR, currently under Design Certification review by the U.S. Nuclear Regulatory Commission, is a four loop evolutionary pressurized water reactor with a four train active safety system applied by Mitsubishi Heavy Industries. The digital Instrumentation and Control (I&amp;C) System and Human Systems Interface (HSI) system are to be applied to the US-APWR. This design is currently being applied to the latest Japanese PWR plant and to nuclear power plant I&amp;C modernization program in Japan. The US-APWR digital I&amp;C and HSI system (HSIS) utilizes computerized systems, including compu
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Vargas, John. "REDUCE PROJECT SCHEDULES AND INCREASE QUALITY USING MODEL DRIVEN DEVELOPMENT FOR DESIGN, VERIFICATION AND TEST." In 2024 NDIA Michigan Chapter Ground Vehicle Systems Engineering and Technology Symposium. National Defense Industrial Association, 2024. http://dx.doi.org/10.4271/2024-01-3400.

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&lt;title&gt;ABSTRACT&lt;/title&gt; &lt;p&gt;As contracts move from cost plus to fixed deliverables, total project cost and reducing schedules become more important. This paper will show how Model Driven Development can address common challenges in the system design, verification &amp;amp; testing of complex systems and systems of systems. Project success requires that hardware, software, and test teams fluently integrate application software, controlling firmware, analog and digital hardware, and mechanical components, which often proves to be costly in terms of time, money, and engineering r
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Kadlubowski, Lukasz A., and Piotr Kmon. "Test and Verification Environment and Methodology for Vernier Time-to-Digital Converter Pixel Array." In 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE, 2021. http://dx.doi.org/10.1109/ddecs52668.2021.9417054.

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Zak, P., and V. Dynybyl. "Design and Testing of Gears With Non-Standard Profile." In ASME 2007 International Mechanical Engineering Congress and Exposition. ASMEDC, 2007. http://dx.doi.org/10.1115/imece2007-41027.

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This paper introduces a sophisticated methodology that guides the design of the non-standard geometry of cylindrical gearwheels, methodology for the evaluation of operation life depending on flank damage (pitting) in shortened lifetime tests of gearwheels and also number of other research results. The methodology for the design of gearwheels modifications is solved by using FEM system and takes into account real geometry of the whole gearbox and its component. Processed samples designs are tested in experimental testing stand and compared with samples which are designed using DIN 3990 standard
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Sheng, Xin, Xiaojin Huang, Zhencai An, and Yin Guo. "Study on an Optimization Algorithm of Generating Test Vectors for Digital Reactor Protection System Testing." In 16th International Conference on Nuclear Engineering. ASMEDC, 2008. http://dx.doi.org/10.1115/icone16-48098.

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As a safety-critical system for the NPP, the digital Reactor Protection System (RPS) has replaced the traditional analog Reactor Protection System in the most newly-built NPPs. A new type digital RPS developed by INET, Tsinghua University, must pass the hardware qualification and software Verification &amp; Validation (V&amp;V) to satisfy the requirements of quality criterion and safety laws. The stimulation/response testing method is always used in the integration testing phase of software V&amp;V. The test vectors group would be very large if the digital RPS has many input variables. Therefo
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Reports on the topic "DIGITAL SYSTEM DESIGN TEST AND VERIFICATION"

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Korsah, K., G. W. Turner, and J. A. Mullens. Environmental testing of a prototypic digital safety channel, Phase I: System design and test methodology. Office of Scientific and Technical Information (OSTI), 1995. http://dx.doi.org/10.2172/90921.

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Sancar, Selcuk, and Foster Stulen. L51501 Field Verification of Optimum Transducer Design Criteria for Acoustic Emission Monitoring. Pipeline Research Council International, Inc. (PRCI), 1986. http://dx.doi.org/10.55274/r0011429.

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This work acquired and analyzed simulated acoustic emissions waveforms from pipelines in three series of field tests. The purposes of the analyses were to verify the accuracy of an analytical model of acoustic emission propagation in pipelines to determine transducer design/selection criteria, and to further evaluate the sensitivity of the verification system. Two sets of tests were performed on a bare and a coated 70-ft. long section of pipe. The third test was performed in conjunction with a hydrotest of a new line being installed near Clay City, Kentucky.
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Vogtsberger. L52138 Resolution Capabilities of High Resolution Axial Flux Leakage Casing Inspection Tools. Pipeline Research Council International, Inc. (PRCI), 2008. http://dx.doi.org/10.55274/r0011164.

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Objective Design and construction of 5.5 inch prototype downhole inspection tool and electronics module. Implement preliminary software acquisition and display module. Integrate hardware and software systems. Conduct operational field test (OFT). Technical Approach From the continuation of Phase 1 of this research, the lessons learned in Phase 1 (Bench Test Prototype) were incorporated into the design and construction of an operational field test instrument. Implementation of preliminary software acquisition and display of data along with integration into existing wireline systems operations a
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Weeks, Timothy "Dash." DTPH56-13-X-000013 Modern High-Toughness Steels for Fracture Propagation and Arrest Assessment-Phase II. Pipeline Research Council International, Inc. (PRCI), 2018. http://dx.doi.org/10.55274/r0012037.

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NIST work developed processes to identify the stress/strain/crack velocity conditions for unstable high-rate ductile crack propagation found in a full-scale pipeline burst test and duplicate those conditions in a medium-scale test. With modeling to validate conditions and assumptions used in reducing the scale of the tests. A medium-scale test to elucidate material property data necessary to qualify high-strength high-toughness steels based on the correlation to large-scale tests. Parametric determination of the material properties governing fracture propagation or arrest-ability was developed
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