Relevant bibliographies by topics / Dynamic Voltage and Frequency Scaling (DVFS)

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Dynamic Voltage and Frequency Scaling (DVFS)'

Author: Grafiati
Published: 4 June 2021
Last updated: 6 September 2023

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Journal articles on the topic "Dynamic Voltage and Frequency Scaling (DVFS)"

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Kocanda, Piotr, and Andrzej Kos. "Energy losses and DVFS effectiveness vs technology scaling." Microelectronics International 32, no. 3 (August 3, 2015): 158–63. http://dx.doi.org/10.1108/mi-01-2015-0008.

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Purpose – This article aims to present complete analysis of energy losses in complementary metal-oxide semiconductor (CMOS) circuits and the effectiveness of dynamic voltage and frequency scaling (DVFS) as a method of energy conservation in CMOS circuits in variety of technologies. Energy efficiency in CMOS devices is an issue of highest importance with still continuing technology scaling. There are powerful tools for energy conservation in form of dynamic voltage scaling (DVS) and dynamic frequency scaling (DFS). Design/methodology/approach – Using analytical equations and Spice models of various technologies, energy losses are calculated and effectiveness of DVS and DFS is evaluated for every technology. Findings – Test showed that new dedicated technology for low static energy consumption can be as economical as older technologies. The dynamic voltage and frequency scaling are most effective when there is a dominance of dynamic energy losses in circuit. In case when static energy losses are comparable to dynamic energy losses, use of dynamic voltage frequency scaling can even lead to increased energy consumption. Originality/value – This paper presents complete analysis of energy losses in CMOS circuits and effectiveness of mentioned methods of energy conservation in CMOS circuits in six different technologies.
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Xu, Shen, Jun Song Li, and Jian Feng Jiang. "Dynamic Voltage and Frequency Scaling Under an Accurate System Energy Model." Advanced Materials Research 442 (January 2012): 321–25. http://dx.doi.org/10.4028/www.scientific.net/amr.442.321.

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Dynamic voltage and frequency scaling (DVFS) is a technique used in modern portable devices operated by battery to set voltage and frequency levels that meet performance requirements while minimizing energy consumption. Most of the present work on DVFS policies are based on simplistic assumptions about the hardware characteristics. In this paper, we discuss the DVFS problem under an accurate system energy model which comes from a application system portable media player (PMP) with a DVFS-capable processor PXA255. We present an optimal DVFS algorithm based on all frequency combinations at the cost of large computation. And a simplified algorithm based on two frequency combinations consumes a little more energy than the former with less computations. The experiment results show that the proposed two algorithms reduce the energy consumption effectively.
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Liang, Wen Yew, Ming Feng Chang, Yen Lin Chen, and Jenq Haur Wang. "Performance Evaluation for Dynamic Voltage and Frequency Scaling Using Runtime Performance Counters." Applied Mechanics and Materials 284-287 (January 2013): 2575–79. http://dx.doi.org/10.4028/www.scientific.net/amm.284-287.2575.

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Dynamic voltage and frequency scaling (DVFS) is an effective technique for reducing power consumption. The system performance is not easy to evaluate through Dynamic Voltage and Frequency Scaling. Most of studies use the execution time as an indicator while measuring the performance. However, DVFS adjusted processor speed during a fixed-length period so it cannot rely on the execution time to evaluate the system performance. This study proposes a novel and simple performance evaluation method to evaluate the system performance when DVFS is activated. Based on the performance evaluation method, this study also proposes a DVFS algorithm (P-DVFS) for a general-purpose operating system. The algorithm has been implemented on the Linux operating system and used a PXA270 development board. The results show that P-DVFS could accurately predict the suitable frequency, given runtime statistics information of a running program. In this way, the user can easily control the energy consumption by specifying allowable performance loss factor.
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Gendler, Alex, Ernest Knoll, and Yiannakis Sazeides. "I-DVFS: Instantaneous Frequency Switch During Dynamic Voltage and Frequency Scaling." IEEE Micro 41, no. 5 (September 1, 2021): 76–84. http://dx.doi.org/10.1109/mm.2021.3096655.

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Florence, A. Paulin, V. Shanthi, and C. B. Sunil Simon. "Energy Conservation Using Dynamic Voltage Frequency Scaling for Computational Cloud." Scientific World Journal 2016 (2016): 1–13. http://dx.doi.org/10.1155/2016/9328070.

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Cloud computing is a new technology which supports resource sharing on a “Pay as you go” basis around the world. It provides various services such as SaaS, IaaS, and PaaS. Computation is a part of IaaS and the entire computational requests are to be served efficiently with optimal power utilization in the cloud. Recently, various algorithms are developed to reduce power consumption and even Dynamic Voltage and Frequency Scaling (DVFS) scheme is also used in this perspective. In this paper we have devised methodology which analyzes the behavior of the given cloud request and identifies the associated type of algorithm. Once the type of algorithm is identified, using their asymptotic notations, its time complexity is calculated. Using best fit strategy the appropriate host is identified and the incoming job is allocated to the victimized host. Using the measured time complexity the required clock frequency of the host is measured. According to that CPU frequency is scaled up or down using DVFS scheme, enabling energy to be saved up to 55% of total Watts consumption.
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Jia, Fan, and Longbing Zhang. "Fine-Grained CPU Power Management Based on Digital Frequency Divider." Electronics 12, no. 2 (January 13, 2023): 407. http://dx.doi.org/10.3390/electronics12020407.

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Dynamic voltage and frequency scaling (DVFS) is a widely used method to improve the energy efficiency of the CPU. Reducing the voltage and frequency during memory-intensive workloads can minimize power consumption without affecting performance, thereby improving overall energy efficiency. A finer-grained DVFS strategy leads to better energy efficiency. However, due to the limitation of voltage regulators, the implementation granularity of the current DVFS strategies is 100 μs or more. This paper proposes that managing the CPU’s power through a more fine-grained load-aware approach can improve CPU energy efficiency, even with limitations of the voltage regulators. This paper adds a more fine-grained dynamic frequency divider to the DVFS system. This mechanism can improve the processor’s energy efficiency in scenarios where DVFS does not take effect. This paper also proposes a DVFS management strategy based on finer-grained sampling. In order to improve the accuracy of performance estimation, we enhanced the state-of-the-art CRIT method to complete accurate memory time estimation in a shorter interval. The power management strategy was verified on the ChampSim and McPAT simulating platforms. In the SPEC CPU 2017 benchmark, this work saves an average of 16.36% energy consumption and improves energy efficiency by 13.57%. Compared with the state-of-the-art CRIT of 9.77% and 6.79%, this work improved energy consumption and efficiency by 6.20% and 6.35%, respectively. This method brings a 2.04% performance reduction, only a 0.16% drop in performance compared to CRIT.
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Chen, Yen-Lin, Ming-Feng Chang, Chao-Wei Yu, Xiu-Zhi Chen, and Wen-Yew Liang. "Learning-Directed Dynamic Voltage and Frequency Scaling Scheme with Adjustable Performance for Single-Core and Multi-Core Embedded and Mobile Systems." Sensors 18, no. 9 (September 12, 2018): 3068. http://dx.doi.org/10.3390/s18093068.

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Dynamic voltage and frequency scaling (DVFS) is a well-known method for saving energy consumption. Several DVFS studies have applied learning-based methods to implement the DVFS prediction model instead of complicated mathematical models. This paper proposes a lightweight learning-directed DVFS method that involves using counter propagation networks to sense and classify the task behavior and predict the best voltage/frequency setting for the system. An intelligent adjustment mechanism for performance is also provided to users under various performance requirements. The comparative experimental results of the proposed algorithms and other competitive techniques are evaluated on the NVIDIA JETSON Tegra K1 multicore platform and Intel PXA270 embedded platforms. The results demonstrate that the learning-directed DVFS method can accurately predict the suitable central processing unit (CPU) frequency, given the runtime statistical information of a running program, and achieve an energy savings rate up to 42%. Through this method, users can easily achieve effective energy consumption and performance by specifying the factors of performance loss.
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Huang, Wei, Zhen Wang, Mianxiong Dong, and Zhuzhong Qian. "A Two-Tier Energy-Aware Resource Management for Virtualized Cloud Computing System." Scientific Programming 2016 (2016): 1–15. http://dx.doi.org/10.1155/2016/4386362.

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The economic costs caused by electric power take the most significant part in total cost of data center; thus energy conservation is an important issue in cloud computing system. One well-known technique to reduce the energy consumption is the consolidation of Virtual Machines (VMs). However, it may lose some performance points on energy saving and the Quality of Service (QoS) for dynamic workloads. Fortunately, Dynamic Frequency and Voltage Scaling (DVFS) is an efficient technique to save energy in dynamic environment. In this paper, combined with the DVFS technology, we propose a cooperative two-tier energy-aware management method including local DVFS control and global VM deployment. The DVFS controller adjusts the frequencies of homogenous processors in each server at run-time based on the practical energy prediction. On the other hand, Global Scheduler assigns VMs onto the designate servers based on the cooperation with the local DVFS controller. The final evaluation results demonstrate the effectiveness of our two-tier method in energy saving.
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Khriji, Sabrine, Rym Chéour, and Olfa Kanoun. "Dynamic Voltage and Frequency Scaling and Duty-Cycling for Ultra Low-Power Wireless Sensor Nodes." Electronics 11, no. 24 (December 7, 2022): 4071. http://dx.doi.org/10.3390/electronics11244071.

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Energy efficiency presents a significant challenge to the reliability of Internet of Things (IoT) services. Wireless Sensor Networks (WSNs) present as an elementary technology of IoT, which has limited resources. Appropriate energy management techniques can perform increasing energy efficiency under variable workload conditions. Therefore, this paper aims to experimentally implement a hybrid energy management solution, combining Dynamic Voltage and Frequency Scaling (DVFS) and Duty-Cycling. The DVFS technique is implemented as an effective power management scheme to optimize the operating conditions during data processing. Moreover, the duty-cycling method is applied to reduce the energy consumption of the transceiver. Hardware optimization is performed by selecting the low-power microcontroller, MSP430, using experimental estimation and characterization. Another contribution is evaluating the energy-saving design by defining the normalized power as a metric to measure the consumed power of the proposed model per throughput. Extensive simulations and real-world implementations indicate that normalized power can be significantly reduced while sustaining performance levels in high-data IoT use cases.
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Zou, An, Huifeng Zhu, Jingwen Leng, Xin He, Vijay Janapa Reddi, Christopher D. Gill, and Xuan Zhang. "System-level Early-stage Modeling and Evaluation of IVR-assisted Processor Power Delivery System." ACM Transactions on Architecture and Code Optimization 18, no. 4 (December 31, 2021): 1–27. http://dx.doi.org/10.1145/3468145.

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Despite being employed in numerous efforts to improve power delivery efficiency, the integrated voltage regulator (IVR) approach has yet to be evaluated rigorously and quantitatively in a full power delivery system (PDS) setting. To fulfill this need, we present a system-level modeling and design space exploration framework called Ivory for IVR-assisted power delivery systems. Using a novel modeling methodology, it can accurately estimate power delivery efficiency, static performance characteristics, and dynamic transient responses under different load variations and external voltage/frequency scaling conditions. We validate the model over a wide range of IVR topologies with silicon measurement and SPICE simulation. Finally, we present two case studies using architecture-level performance and power simulators. The first case study focuses on optimal PDS design for multi-core systems, which achieves 8.6% power efficiency improvement over conventional off-chip voltage regulator module– (VRM) based PDS. The second case study explores the design tradeoffs for IVR-assisted PDSs in CPU and GPU systems with fast per-core dynamic voltage and frequency scaling (DVFS). We find 2 μs to be the optimal DVFS timescale, which not only reaps energy benefits (12.5% improvement in CPU and 50.0% improvement in GPU) but also avoids costly IVR overheads.
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Dissertations / Theses on the topic "Dynamic Voltage and Frequency Scaling (DVFS)"

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Rountree, Barry. "Theory and Practice of Dynamic Voltage/Frequency Scaling in the High Performance Computing Environment." Diss., The University of Arizona, 2009. http://hdl.handle.net/10150/305368.

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This dissertation provides a comprehensive overview of the theory and practice of Dynamic Voltage/Frequency Scaling (DVFS) in the High Performance Computing (HPC) environment. We summarize the overall problem as follows: how can the same level of computational performance be achieved using less electrical power? Equivalently, how can computational performance be increased using the same amount of electrical power? In this dissertation we present performance and architecture models of DVFS as well as the Adagio runtime system. The performance model recasts the question as an optimization problem that we solve using linear programming, thus establishing a bound on potential energy savings. The architectural model provides a low-level explanation of how memory bus and CPU clock frequencies interact to determine execution time. Using insights provided from these models, we have designed and implemented the Adagio runtime system. This system realizes near-optimal energy savings on real-world scientific applications without the use of training runs or source code modification, and under the constraint that only negligible delay will be tolerated by the user. This work has opened up several new avenues of research, and we conclude by enumerating these.
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Saha, Sonal. "An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms." Thesis, Virginia Tech, 2011. http://hdl.handle.net/10919/35035.

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Dynamic voltage and frequency scaling (DVFS) is an extensively studied energy manage- ment technique, which aims to reduce the energy consumption of computing platforms by dynamically scaling the CPU frequency. Real-Time DVFS (RT-DVFS) is a branch of DVFS, which reduces CPU energy consumption through DVFS, while at the same time ensures that task time constraints are satisfied by constructing appropriate real-time task schedules. The literature presents numerous RT-DVFS scheduling algorithms, which employ different tech- niques to utilize the CPU idle time to scale the frequency. Many of these algorithms have been experimentally studied through simulations, but have not been implemented on real hardware platforms. Though simulation-based experimental studies can provide a first-order understanding, implementation-based studies can reveal actual timeliness and energy con- sumption behaviours. This is particularly important, when it is difficult to devise accurate simulation models of hardware, which is increasingly the case with modern systems. In this thesis, we study the timeliness and energy consumption behaviours of fourteen state- of-the-art RT-DVFS schedulers by implementing and evaluating them on two hardware plat- forms. The schedulers include CC-EDF, LA-EDF, REUA, DRA andd AGR1 among others, and the hardware platforms include ASUS laptop with the Intel I5 processor and a mother- board with the AMD Zacate processor. We implemented these schedulers in the ChronOS real-time Linux kernel and measured their actual timeliness and energy behaviours under a range of workloads including CPU-intensive, memory-intensive, mutual exclusion lock- intensive, and processor-underloaded and overloaded workloads. Our studies reveal that measuring the CPU power consumption as the cube of CPU fre- quency can lead to incorrect conclusions. In particular, it ignores the idle state CPU power consumption, which is orders of magnitude smaller than the active power consumption. Consequently, power savings obtained by exclusively optimizing active power consumption (i.e., RT-DVFS) may be offset by completing tasks sooner by running them at the highest frequency and transitioning to the idle state earlier (i.e., no DVFS). Thus, the active power consumption savings of the RT-DVFS techniquesâ that we report are orders of magnitude smaller than their simulation-based savings reported in the literature.
Master of Science
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Clark, Mark A. "Dynamic Voltage/Frequency Scaling and Power-Gating of Network-on-Chip with Machine Learning." Ohio University / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1544105215810566.

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Li, Juan. "Application-Directed DVFS using Multiple Clock Domains on Graphics Hardware." Digital WPI, 2009. https://digitalcommons.wpi.edu/etd-theses/85.

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As handheld devices have become increasingly popular, powerful programmable graphics hardware for mobile and handheld devices has been deployed. While many resources on mobile devices are limited, the predominant problem for mobile devices is their limited battery power. Several techniques have been proposed to increase the energy efficiency of mobile applications and improve battery life. In this thesis, we propose a new dynamic voltage and frequency scaling (DVFS) on Graphics Processing Units (GPU). In most cases, cues within the graphics appli- cation can be used to predict portions of a GPU that will be used or unused when the application is run. We partition the GPU into six clock domains that can be clocked at different rates. Specifically, each domain it has its own voltage and frequency set- ting based on its predicted workload to save energy without reducing applications frame rates. In addition, we propose an signature-based algorithm for predicting the workload offered to our six clock domains by a given application to decide voltage and frequency settings. We conduct experiments and compare the results of our new signature based workload prediction algorithm with some other traditional interval based workload prediction algorithms. Our results show that our signature-based prediction can save 30-50% energy without afecting application frame rates.
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Muhammad, F. "Ordonnancement de tâches efficace et à complexité maîtrisée pour des systèmes temps-réel." Phd thesis, Université de Nice Sophia-Antipolis, 2009. http://tel.archives-ouvertes.fr/tel-00454616.

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Les performances des algorithmes d'ordonnancement ont un impact direct sur les performances du système complet. Les algorithmes d'ordonnancement temps réel possèdent des bornes théoriques d'ordonnançabilité optimales mais cette optimalité est souvent atteinte au prix d'un nombre élevé d'événements d'ordonnancement à considérer (préemptions et migrations de tâches) et d'une complexité algorithmique importante. Notre opinion est qu'en exploitant plus efficacement les paramètres des tâches il est possible de rendre ces algorithmes plus efficaces et à coût maitrisé, et ce dans le but d'améliorer la Qualité de Service (QoS) des applications. Nous proposons dans un premier temps des algorithmes d'ordonnancement monoprocesseur qui augmentent la qualité de service d'applications hybrides c'est-à-dire qu'en situation de surcharge, les tâches à contraintes souples ont leur exécution maximisée et les échéances des tâches à contraintes strictes sont garanties. Le coût d'ordonnancement de ces algorithmes est aussi réduit (nombre de préemptions) par une meilleure exploitation des paramètres implicites et explicites des tâches. Cette réduction est bénéfique non seulement pour les performances du système mais elle agit aussi positivement sur la consommation d'énergie. Aussi nous proposons une technique associée à celle de DVFS (dynamic voltage and frequency scaling) afin de minimiser le nombre de changements de points de fonctionnement du fait qu'un changement de fréquence implique un temps d'inactivité du processeur et une consommation d'énergie. Les algorithmes d'ordonnancement multiprocesseur basés sur le modèle d'ordonnancement fluide (notion d'équité) atteignent des bornes d'ordonnançabilité optimales. Cependant cette équité n'est garantie qu'au prix d'hypothèses irréalistes en pratique du fait des nombres très élevés de préemptions et de migrations de tâches qu'ils induisent. Dans cette thèse un algorithme est proposé (ASEDZL) qui n'est pas basé sur le modèle d'ordonnancement fluide. Il permet non seulement de réduire les préemptions et les migrations de tâches mais aussi de relâcher les hypothèses imposées par ce modèle d'ordonnancement. Enfin, nous proposons d'utiliser ASEDZL dans une approche d'ordonnancement hiérarchique ce qui permet d'obtenir de meilleurs résultats que les techniques classiques.
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Shiomi, Jun. "Performance Modeling and On-Chip Memory Structures for Minimum Energy Operation in Voltage-Scaled LSI Circuits." Kyoto University, 2017. http://hdl.handle.net/2433/228252.

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Bhatti, K. "Energy-aware Scheduling for Multiprocessor Real-time Systems." Phd thesis, Université de Nice Sophia-Antipolis, 2011. http://tel.archives-ouvertes.fr/tel-00599980.

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Les applications temps réel modernes deviennent plus exigeantes en termes de ressources et de débit amenant la conception d'architectures multiprocesseurs. Ces systèmes, des équipements embarqués au calculateur haute performance, sont, pour des raisons d'autonomie et de fiabilité, confrontés des problèmes cruciaux de consommation d'énergie. Pour ces raisons, cette thèse propose de nouvelles techniques d'optimisation de la consommation d'énergie dans l'ordonnancement de systèmes multiprocesseur. La premiére contribution est un algorithme d'ordonnancement hiérarchique á deux niveaux qui autorise la migration restreinte des tâches. Cet algorithme vise á réduire la sous-optimalité de l'algorithme global EDF. La deuxiéme contribution de cette thèse est une technique de gestion dynamique de la consommation nommée Assertive Dynamic Power Management (AsDPM). Cette technique, qui régit le contrôle d'admission des tâches, vise á exploiter de manière optimale les modes repos des processeurs dans le but de réduire le nombre de processeurs actifs. La troisiéme contribution propose une nouvelle technique, nommée Deterministic Stretch-to-Fit (DSF), permettant d'exploiter le DVFS des processeurs. Les gains énergétiques observés s'approchent des solutions déjà existantes tout en offrant une complexité plus réduite. Ces techniques ont une efficacité variable selon les applications, amenant á définir une approche plus générique de gestion de la consommation appelée Hybrid Power Management (HyPowMan). Cette approche sélectionne, en cours d'exécution, la technique qui répond le mieux aux exigences énergie/performance.
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Mallangi, Siva Sai Reddy. "Low-Power Policies Based on DVFS for the MUSEIC v2 System-on-Chip." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-229443.

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Multi functional health monitoring wearable devices are quite prominent these days. Usually these devices are battery-operated and consequently are limited by their battery life (from few hours to a few weeks depending on the application). Of late, it was realized that these devices, which are currently being operated at fixed voltage and frequency, are capable of operating at multiple voltages and frequencies. By switching these voltages and frequencies to lower values based upon power requirements, these devices can achieve tremendous benefits in the form of energy savings. Dynamic Voltage and Frequency Scaling (DVFS) techniques have proven to be handy in this situation for an efficient trade-off between energy and timely behavior. Within imec, wearable devices make use of the indigenously developed MUSEIC v2 (Multi Sensor Integrated circuit version 2.0). This system is optimized for efficient and accurate collection, processing, and transfer of data from multiple (health) sensors. MUSEIC v2 has limited means in controlling the voltage and frequency dynamically. In this thesis we explore how traditional DVFS techniques can be applied to the MUSEIC v2. Experiments were conducted to find out the optimum power modes to efficiently operate and also to scale up-down the supply voltage and frequency. Considering the overhead caused when switching voltage and frequency, transition analysis was also done. Real-time and non real-time benchmarks were implemented based on these techniques and their performance results were obtained and analyzed. In this process, several state of the art scheduling algorithms and scaling techniques were reviewed in identifying a suitable technique. Using our proposed scaling technique implementation, we have achieved 86.95% power reduction in average, in contrast to the conventional way of the MUSEIC v2 chip’s processor operating at a fixed voltage and frequency. Techniques that include light sleep and deep sleep mode were also studied and implemented, which tested the system’s capability in accommodating Dynamic Power Management (DPM) techniques that can achieve greater benefits. A novel approach for implementing the deep sleep mechanism was also proposed and found that it can obtain up to 71.54% power savings, when compared to a traditional way of executing deep sleep mode.
Nuförtiden så har multifunktionella bärbara hälsoenheter fått en betydande roll. Dessa enheter drivs vanligtvis av batterier och är därför begränsade av batteritiden (från ett par timmar till ett par veckor beroende på tillämpningen). På senaste tiden har det framkommit att dessa enheter som används vid en fast spänning och frekvens kan användas vid flera spänningar och frekvenser. Genom att byta till lägre spänning och frekvens på grund av effektbehov så kan enheterna få enorma fördelar när det kommer till energibesparing. Dynamisk skalning av spänning och frekvens-tekniker (såkallad Dynamic Voltage and Frequency Scaling, DVFS) har visat sig vara användbara i detta sammanhang för en effektiv avvägning mellan energi och beteende. Hos Imec så använder sig bärbara enheter av den internt utvecklade MUSEIC v2 (Multi Sensor Integrated circuit version 2.0). Systemet är optimerat för effektiv och korrekt insamling, bearbetning och överföring av data från flera (hälso) sensorer. MUSEIC v2 har begränsad möjlighet att styra spänningen och frekvensen dynamiskt. I detta examensarbete undersöker vi hur traditionella DVFS-tekniker kan appliceras på MUSEIC v2. Experiment utfördes för att ta reda på de optimala effektlägena och för att effektivt kunna styra och även skala upp matningsspänningen och frekvensen. Eftersom att ”overhead” skapades vid växling av spänning och frekvens gjordes också en övergångsanalys. Realtidsoch icke-realtidskalkyler genomfördes baserat på dessa tekniker och resultaten sammanställdes och analyserades. I denna process granskades flera toppmoderna schemaläggningsalgoritmer och skalningstekniker för att hitta en lämplig teknik. Genom att använda vår föreslagna skalningsteknikimplementering har vi uppnått 86,95% effektreduktion i jämförelse med det konventionella sättet att MUSEIC v2-chipets processor arbetar med en fast spänning och frekvens. Tekniker som inkluderar lätt sömn och djupt sömnläge studerades och implementerades, vilket testade systemets förmåga att tillgodose DPM-tekniker (Dynamic Power Management) som kan uppnå ännu större fördelar. En ny metod för att genomföra den djupa sömnmekanismen föreslogs också och enligt erhållna resultat så kan den ge upp till 71,54% lägre energiförbrukning jämfört med det traditionella sättet att implementera djupt sömnläge.
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Akgul, Yeter. "Gestion de la consommation basée sur l’adaptation dynamique de la tension, fréquence et body bias sur les systèmes sur puce en technologie FD-SOI." Thesis, Montpellier 2, 2014. http://www.theses.fr/2014MON20132/document.

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Au-delà du nœud technologique CMOS BULK 28nm, certaines limites ont été atteintes dans l'amélioration des performances en raison notamment d'une consommation énergétique devenant trop importante. C'est une des raisons pour lesquelles de nouvelles technologies ont été développées, notamment celles basées sur Silicium sur Isolant (SOI). Par ailleurs, la généralisation des architectures complexes de type multi-cœurs, accentue le problème de gestion de la consommation à grain-fin. Les technologies CMOS FD-SOI offrent de nouvelles opportunités pour la gestion de la consommation en permettant d'ajuster, outre les paramètres usuels que sont la tension d'alimentation et la fréquence d'horloge, la tension de body bias. C'est dans ce contexte que ce travail étudie les nouvelles possibilités offertes et explore des solutions innovantes de gestion dynamique de la tension d'alimentation, fréquence d'horloge et tension de body bias afin d'optimiser la consommation énergétique des systèmes sur puce. L'ensemble des paramètres tensions/fréquence permettent une multitude de points de fonctionnement, qui doivent satisfaire des contraintes de fonctionnalité et de performance. Ce travail s'intéresse donc dans un premier temps à une problématique de conception, en proposant une méthode d'optimisation du placement de ces points de fonctionnement. Une solution analytique permettant de maximiser le gain en consommation apporté par l'utilisation de plusieurs points de fonctionnement est proposée. La deuxième contribution importante de cette thèse concerne la gestion dynamique de la tension d'alimentation, de la fréquence et de la tension de body bias, permettant d'optimiser l'efficacité énergétique en se basant sur le concept de convexité. La validation expérimentale des méthodes proposées s'appuie sur des échantillons de circuits réels, et montre des gains en consommation moyens allant jusqu'à 35%
Beyond 28nm CMOS BULK technology node, some limits have been reached in terms of performance improvements. This is mainly due to the increasing power consumption. This is one of the reasons why new technologies have been developed, including those based on Silicon-On-Insulator (SOI). Moreover, the standardization of complex architectures such as multi-core architectures emphasizes the problem of power management at fine-grain. FD-SOI technologies offer new power management opportunities by adjusting, in addition to the usual parameters such as supply voltage and clock frequency, the body bias voltage. In this context, this work explores new opportunities and searches novel solutions for dynamically manage supply voltage, clock frequency and body bias voltage in order to optimize the power consumption of System on Chip.Adjusting supply voltage, frequency and body bias parameters allows multiple operating points, which must satisfy the constraints of functionality and performance. This work focuses initially at design time, proposing a method to optimize the placement of these operating points. An analytical solution to maximize power savings achieved through the use of several operating points is provided. The second important contribution of this work is a method based on convexity concept to dynamically manage the supply voltage, the frequency and the body bias voltage so as to optimize the energy efficiency. The experimental results based on real circuits show average power savings reaching 35%
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Zorello, Ligia Maria Moreira. "Dynamic CPU frequency scaling using machine learning for NFV applications." Universidade de São Paulo, 2018. http://www.teses.usp.br/teses/disponiveis/3/3141/tde-30012019-100044/.

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Growth in the Information and Communication Technology sector is increasing the need to improve the quality of service and energy efficiency, as this industry has already surpassed 12% of global energy consumption in 2017. Data centers correspond to a large part of this consumption, accounting for about 15% of energy expenditure on the Information and Communication Technology domain; moreover, the subsystem that generates the most costs for data center operators is that of servers and storage. Many solutions have been proposed to reduce server consumption, such as the use of dynamic voltage and frequency scaling, a technology that enables the adaptation of energy consumption to the workload by modifying the operating voltage and frequency, although they are not optimized for network traffic. In this thesis, a control method was developed using a prediction engine based on the analysis of the ongoing traffic. Machine learning algorithms based on Neural Networks and Support Vector Machines have been used, and it was verified that it is possible to reduce power consumption by up to 12% on servers with Intel Sandy Bridge processor and up to 21 % in servers with Intel Haswell processor when compared to the maximum frequency, which is currently the most used solution in the industry.
O crescimento do setor de Tecnologia da Informação e Comunicação está aumentando a necessidade de melhorar a qualidade de serviço e a eficiência energética, pois o setor já ultrapassou a marca de 12% do consumo energético global em 2017. Data centers correspondem a grande parte desse consumo, representando cerca de 15% dos gastos com energia do setor Tecnologia Informação e Comunicação; além disso, o subsistema que gera mais custos para operadores de data centers é o de servidores e armazenamento. Muitas soluções foram propostas a fim de reduzir o consumo de energia com servidores, como o uso de escalonamento dinâmico de tensão e frequência, uma tecnologia que permite adaptar o consumo de energia à carga de trabalho, embora atualmente não sejam otimizadas para o processamento do tráfego de rede. Nessa dissertação, foi desenvolvido um método de controle usando um mecanismo de previsão baseado na análise do tráfego que chega aos servidores. Os algoritmos de aprendizado de máquina baseados em Redes Neurais e em Máquinas de Vetores de Suporte foram utilizados, e foi verificado que é possível reduzir o consumo de energia em até 12% em servidores com processador Intel Sandy Bridge e em até 21% em servidores com processador Intel Haswell quando comparado com a frequência máxima, que é atualmente a solução mais utilizada na indústria.
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Books on the topic "Dynamic Voltage and Frequency Scaling (DVFS)"

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Trescases, Olivier. A high-frequency, soft-switching DC-DC converter for dynamic voltage scaling in VLSI loads. 2004.

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Book chapters on the topic "Dynamic Voltage and Frequency Scaling (DVFS)"

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Kumar, Sachin, Saurabh Pal, Satya Singh, Vijendra Pratap Singh, Devashish Singh, Tapash Kumar Saha, Himanshu Gupta, and Priya Jaiswal. "Energy Efficient Model for Balancing Energy in Cloud Datacenters Using Dynamic Voltage Frequency Scaling (DVFS) Technique." In Proceedings of Third Doctoral Symposium on Computational Intelligence, 533–40. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-3148-2_45.

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Moons, Bert, and Marian Verhelst. "DVAFS—Dynamic-Voltage-Accuracy-Frequency-Scaling Applied to Scalable Convolutional Neural Network Acceleration." In System-Scenario-based Design Principles and Applications, 99–111. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-20343-6_5.

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Hsu, Chung-Hsing, and Ulrich Kremer. "Dynamic Voltage and Frequency Scaling for Scientific Applications." In Languages and Compilers for Parallel Computing, 86–99. Berlin, Heidelberg: Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/3-540-35767-x_6.

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Hsu, Chung-Hsing, and Ulrich Kremer. "Compiler-Directed Dynamic CPU Frequency and Voltage Scaling." In Designing Embedded Processors, 305–23. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5869-1_14.

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Akgün, Gökhan, Lester Kalms, and Diana Göhringer. "Resource Efficient Dynamic Voltage and Frequency Scaling on Xilinx FPGAs." In Applied Reconfigurable Computing. Architectures, Tools, and Applications, 178–92. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-44534-8_14.

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Meijer, Maurice, and José Pineda Gyvez. "Technological Boundaries of Voltage and Frequency Scaling for Power Performance Tuning." In Adaptive Techniques for Dynamic Processor Optimization, 25–47. Boston, MA: Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-76472-6_2.

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Ghosh, Shreya, and Jaydeep Das. "Dynamic Voltage and Frequency Scaling Approach for Processing Spatio-Temporal Queries in Mobile Environment." In Green Mobile Cloud Computing, 185–99. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-08038-8_9.

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Huang, Xin, KenLi Li, and RenFa Li. "A Energy Efficient Scheduling Base on Dynamic Voltage and Frequency Scaling for Multi-core Embedded Real-Time System." In Algorithms and Architectures for Parallel Processing, 137–45. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-03095-6_14.

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Hayamizu, Yuto, Kazuo Goda, Miyuki Nakano, and Masaru Kitsuregawa. "Application-Aware Power Saving for Online Transaction Processing Using Dynamic Voltage and Frequency Scaling in a Multicore Environment." In Architecture of Computing Systems - ARCS 2011, 50–61. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-19137-4_5.

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Yanamandra, Aditya, Soumya Eachempati, Vijaykrishnan Narayanan, and Mary Jane Irwin. "Reliability Aware Performance and Power Optimization in DVFS-Based On-Chip Networks." In Dynamic Reconfigurable Network-on-Chip Design, 277–92. IGI Global, 2010. http://dx.doi.org/10.4018/978-1-61520-807-4.ch011.

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Recently, chip multi-processors (CMP) have emerged to fully utilize the increased transistor count within stringent power budgets. Transistor scaling has lead to more error-prone and defective components. Static and run-time induced variations in the circuit lead to reduced yield and reliability. Providing reliability at low overheads specifically in terms of power is a challenging task that requires innovative solutions for building future integrated chips. Static variations have been studied previously. In this proposal, we study the impact of run-time variations on reliability. On-chip interconnection network that forms the communication fabric in the CMP has a crucial role in determining the performance, power consumption and reliability of the system. We manage protecting the data in a network on chip from transient errors induced by voltage fluctuations. Variations in operating conditions result in a significant variation in the reliability of the system, motivating the need to provide tunable levels of data protection. For example, the use of Dynamic Voltage and Frequency Scaling (DVFS) technique used in most CMPs today results in voltage variation across the chip, giving rise to variable error rates across the chip. We investigated the design of a dynamically reconfigurable error protection scheme in a NoC to achieve a desired level of reliability. We protect data at the desired reliability while minimizing the power and performance overhead incurred. We obtain a maximum of 55% savings in the power expended for error protection in the network with our proposed reconfigurable ECC while maintaining constant reliability. Further, 35% reduction in the average message latency in the network is observed, making a case for providing tunability in error protection in the on-chip network fabric.
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Conference papers on the topic "Dynamic Voltage and Frequency Scaling (DVFS)"

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Garg, Deepak, and Rajender Sharma. "Low Power Multiplier using Dynamic Voltage and Frequency Scaling (DVFS)." In 2014 International Conference on Advances in Computing, Communications and Informatics (ICACCI). IEEE, 2014. http://dx.doi.org/10.1109/icacci.2014.6968494.

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Jeabin Lee, Byeong-Gyu Nam, and Hoi-Jun Yoo. "Dynamic Voltage and Frequency Scaling (DVFS) scheme for multi-domains power management." In 2007 IEEE Asian Solid-State Circuits Conference. IEEE, 2007. http://dx.doi.org/10.1109/asscc.2007.4425705.

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Chen, Yen-Hao, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, and TingTing Hwang. "A Novel Cache-Utilization Based Dynamic Voltage Frequency Scaling (DVFS) Mechanism for Reliability Enhancements." In Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE). Singapore: Research Publishing Services, 2016. http://dx.doi.org/10.3850/9783981537079_0067.

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Melo, Renato, and Vinicius Petrucci. "Eficiência Energética em Navegação Web usando DVFS." In Simpósio Brasileiro de Redes de Computadores e Sistemas Distribuídos. Sociedade Brasileira de Computação - SBC, 2018. http://dx.doi.org/10.5753/sbrc.2018.2412.

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O consumo de energia tornou-se uma grande preocupação em data centers e dispositivos móveis. Este trabalho propõe um gerenciador inteligente de energia, Web Governor, que explora a técnica DVFS (Dynamic Voltage and Frequency Scaling) disponível em processadores modernos para reduzir o consumo de energia em aplicações de navegação na Web, com o diferencial em explorar características da rede de comunicação. Resultados experimentais mostram que o Web Governor é capaz de reduzir o consumo de energia do sistema em 12% (média) e 18% (max) quando comparado ao governor DVFS do Linux desenvolvido pelo Google/Android, enquanto carrega as páginas mais rapidamente (em média, 4%). Quando comparado a um gerenciador DVFS do Linux focado no desempenho, o Web Governor melhora a eficiência energética em 29% em média e até 49%, mantendo semelhante o tempo de carregamento para uma variedade de páginas Web.
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Costa, Mariana, Sandro Marques, Thiarles Medeiros, Fábio Rossi, Marcelo Luizelli, Antonio Carlos Beck, and Arthur Lorenzon. "PampaFreq: Otimizando o EDP de Aplicações Paralelas em Processadores AMD." In XXI Simpósio em Sistemas Computacionais de Alto Desempenho. Sociedade Brasileira de Computação, 2020. http://dx.doi.org/10.5753/wscad.2020.14057.

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O DVFS (Dynamic Voltage and Frequency Scaling) tem sido amplamente utilizado para melhorar o uso dos recursos computacionais quando aplicações paralelas estão sendo executadas. No entanto, as aplicações paralelas têm comportamentos distintos e se relacionam de diferentes maneiras com as políticas de modificação de frequência do DVFS. Neste sentido, é necessário utilizar métodos otimizados de DVFS para melhorar o custo-benefício entre desempenho e consumo de energia, representado pelo EDP (energy-delay product). Dito isso, através de uma extensa exploração de espaço e projeto de diferentes políticas de DVFS, níveis de frequência de operação da CPU e modo de operação de técnicas de boosting com a execução de dezesseis aplicações paralelas em três arquiteturas multicore, nós propomos PampaFreq, uma metodologia que otimiza o EDP em processadores AMD considerando as características da aplicação em tempo de execução. No caso mais significativo, PampaFreq otimiza o EDP em até 38% quando comparado com governor ondemand.
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Zhao, Shuze, Ibrahim Ahmed, Carl Lamoureux, Ashraf Lotfi, Vaughn Betz, and Olivier Trescases. "A universal self-calibrating Dynamic Voltage and Frequency Scaling (DVFS) scheme with thermal compensation for energy savings in FPGAs." In 2016 IEEE Applied Power Electronics Conference and Exposition (APEC). IEEE, 2016. http://dx.doi.org/10.1109/apec.2016.7468125.

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Moons, Bert, Roel Uytterhoeven, Wim Dehaene, and Marian Verhelst. "DVAFS: Trading computational accuracy for energy through dynamic-voltage-accuracy-frequency-scaling." In 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2017. http://dx.doi.org/10.23919/date.2017.7927038.

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Nobuaki Kobayashi and Tadayoshi Enomoto. "A low power 90-nm CMOS motion estimation processor implementing dynamic voltage and frequency scaling (DVFS) and fast motion estimation algorithm." In 2008 IEEE International Symposium on Circuits and Systems - ISCAS 2008. IEEE, 2008. http://dx.doi.org/10.1109/iscas.2008.4541757.

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Ait El Mahjoub, Youssef, Leo Le Corre, and Hind Castel-Taleb. "Stochastic Modeling And Optimization For Power And Performance Control In DVFS Systems." In 37th ECMS International Conference on Modelling and Simulation. ECMS, 2023. http://dx.doi.org/10.7148/2023-0497.

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The paper addresses the problem of performance-energy trade-off in DVFS (Dynamic Voltage Frequency Scaling) systems. We propose a stochastic hybrid model between hysteresis models and server block models. We provide a closed form for the steady-state distribution probability and we establish a "st" type order to compare the performance measures. The fast computation of power and performance measures leads to a multi-objective optimization analysis in two forms: a scalarization method and a Pareto based method. For the two approaches, we propose fast and efficient approximate algorithms that construct progressively an optimal solution. To discuss results, the model is used to simulate a physical server hosting several VMs (Virtual Machines) where we investigate optimal thresholds for the performance-energy trade-off.
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Brandalero, Marcelo, and Antonio Carlos Beck. "MuTARe: A Multi-Target, Adaptive Reconfigurable Architecture." In XX Simpósio em Sistemas Computacionais de Alto Desempenho. Sociedade Brasileira de Computação - SBC, 2019. http://dx.doi.org/10.5753/wscad_estendido.2019.8706.

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Power consumption, earlier a design constraint only in embedded systems, has become the major driver for architectural optimizations in all domains, from the cloud to the edge. Application-specific accelerators provide a low-power processing solution by efficiently matching the hardware to the application; however, since in many domains the hardware must execute efficiently a broad range of fast-evolving applications, unpredictable at design time and each with distinct resource requirements, alternatives approaches are required. Besides that, the same hardware must also adapt the computational power at run time to the system status and workload sizes. To address these issues, this thesis presents a general-purpose reconfigurable accelerator that can be coupled to a heterogeneous set of cores and supports Dynamic Voltage and Frequency Scaling (DVFS), synergistically combining the techniques for a better match between different applications and hardware when compared to current designs. The resulting architecture, MuTARe, provides a coarse-grained regular and reconfigurable structure which is suitable for automatic acceleration of deployed code through dynamic binary translation. In extension to that, the structure of MuTARe is further leveraged to apply two emerging computing paradigms that can boost the power-efficiency: Near-Threshold Voltage (NTV) computing (while still supporting transparent acceleration) and Approximate Computing (AxC). Compared to a traditional heterogeneous system with DVFS support, the base MuTARe architecture can automatically improve the execution time by up to 1:3×, or adapt to the same task deadline with 1:6× smaller energy consumption, or adapt to the same low energy budget with 2:3× better performance. In NTV mode, MuTARe can transparently save further 30% energy in memory-intensive workloads by operating the combinatorial datapath at half the memory frequency. In AxC mode, MuTARe can further improve power savings by up to 50% by leveraging approximate functional units for arithmetic computations.
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