Relevant bibliographies by topics / Embedded Processors

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Embedded Processors'

Author: Grafiati
Published: 4 June 2021
Last updated: 6 September 2023

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'Embedded Processors.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "Embedded Processors"

1

Pflanz, M., and H. T. Vierhaus. "Generating reliable embedded processors." IEEE Micro 18, no. 5 (1998): 33–41. http://dx.doi.org/10.1109/40.735942.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Wei, Xiaotong, Ying Yang, and Jie Chen. "A Low-Latency Divider Design for Embedded Processors." Sensors 22, no. 7 (March 23, 2022): 2471. http://dx.doi.org/10.3390/s22072471.

Full text
Abstract:
Division is generally regarded as a low-frequency, high-latency operation in integer operations. Division is also the operation that stalls the processor pipeline most frequently. In order to improve the overall performance of embedded processors, a low-delay divider for embedded processors was designed. Based on the non-restoring algorithm, the divider uses a compound adder to execute addition and subtraction simultaneously and reduces the iteration path delay. By shifting the operands to align the most effective bits, the divider dynamically adjusts the number of iteration cycles to reduce t
APA, Harvard, Vancouver, ISO, and other styles
3

KWON, YOUNG-SU, and NAK-WOONG EUM. "APPLICATION-ADAPTIVE RECONFIGURATION OF MEMORY ADDRESS SHUFFLER FOR FPGA-EMBEDDED INSTRUCTION-SET PROCESSOR." Journal of Circuits, Systems and Computers 19, no. 07 (November 2010): 1435–47. http://dx.doi.org/10.1142/s0218126610006748.

Full text
Abstract:
Programmability requirement in reconfigurable systems necessitates the integration of soft processors in FPGAs. The extensive memory bandwidth sets a major performance bottleneck in soft processors for media applications. While the parallel memory system is a viable solution to account for a large amount of memory transactions in media processors, memory access conflicts caused by multiple memory buses limit the overall performance. We propose and evaluate the configurable memory address shuffler integrated in memory access arbiter for the parallel memory system in a soft processor. The novel
APA, Harvard, Vancouver, ISO, and other styles
4

Doraipandian, Manivannan, and Periasamy Neelamegam. "Wireless Sensor Network Using ARM Processors." International Journal of Embedded and Real-Time Communication Systems 4, no. 4 (October 2013): 48–59. http://dx.doi.org/10.4018/ijertcs.2013100103.

Full text
Abstract:
The hardware design of Wireless Sensor Networks (WSN) is the crux of its effective deployment. Nowadays these networks are used in microscopic, secure and high-end embedded products. WSN's potentiality in terms of efficient data sensing and distributed data processing has led to its usage in applications for measurement and tracking. WSN comprises of small number of embedded devices known as sensor nodes, gateways and base stations. Sensor nodes consist of sensors, processors and transceivers. The property of embedded sensor devices, also called motes, is to determine the strength of WSN. Thus
APA, Harvard, Vancouver, ISO, and other styles
5

Núñez-Prieto, Ricardo, David Castells-Rufas, and Lluís Terés-Terés. "RisCO2: Implementation and Performance Evaluation of RISC-V Processors for Low-Power CO2 Concentration Sensing." Micromachines 14, no. 7 (July 4, 2023): 1371. http://dx.doi.org/10.3390/mi14071371.

Full text
Abstract:
In the field of embedded systems, energy efficiency is a critical requirement, particularly for battery-powered devices. RISC-V processors have gained popularity due to their flexibility and open-source nature, making them an attractive choice for embedded applications. However, not all RISC-V processors are equally energy-efficient, and evaluating their performance in specific use cases is essential. This paper presents RisCO2, an RISC-V implementation optimized for energy efficiency. It evaluates its performance compared to other RISC-V processors in terms of resource utilization and energy
APA, Harvard, Vancouver, ISO, and other styles
6

Muralidharan, K., and S. Uma Maheswari. "Design of Low Power Cam Memory Cell for the Next Generation Network Processors." IRO Journal on Sustainable Wireless Systems 3, no. 4 (December 3, 2021): 208–18. http://dx.doi.org/10.36548/jsws.2021.4.001.

Full text
Abstract:
In the modern world, high performance embedded applications in the field of multimedia, networking, and imaging are increasing day by day. These applications require high performance and more complex out-of-order superscalar processor. These complex dynamic instructions scheduling superscalar processors need higher levels of on-chip integration designs which are often associated with power dissipation. These out-of-order superscalar processors achieve higher performance compared to other processors by simultaneous fetching, decoding and execution for multiple instructions in out-of-order that
APA, Harvard, Vancouver, ISO, and other styles
7

Levy, Markus, and Thomas M. Conte. "Embedded Multicore Processors and Systems." IEEE Micro 29, no. 3 (May 2009): 7–9. http://dx.doi.org/10.1109/mm.2009.41.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Dutt, N., and Kiyoung Choi. "Configurable processors for embedded computing." Computer 36, no. 1 (January 2003): 120–23. http://dx.doi.org/10.1109/mc.2003.1160063.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Shin, Youngsoo, Kiyoung Choi, and Takayasu Sakurai. "Power-conscious Scheduling for Real-time Embedded Systems Design." VLSI Design 12, no. 2 (January 1, 2001): 139–50. http://dx.doi.org/10.1155/2001/23925.

Full text
Abstract:
Power efficient design of real-time embedded systems based on programmable processors becomes more important as system functionality is increasingly realized through software. We address a power optimization method for real-time embedded applications on a variable speed processor. The method combines off-line and on-line components. The off-line component determines the lowest possible maximum processor speed while guaranteeing deadlines of all tasks. The on-line component dynamically varies the processor speed or bring a processor into a power-down mode to exploit execution time variations an
APA, Harvard, Vancouver, ISO, and other styles
10

Wang, Tun, and Yu Tian. "Design of Embedded Ai Engine Based on the Microkernel Operating System." Wireless Communications and Mobile Computing 2022 (April 21, 2022): 1–9. http://dx.doi.org/10.1155/2022/9304019.

Full text
Abstract:
At present, the application of the embedded microkernel operating system in military and civil fields has begun to take shape, but it has not yet formed a unified method and standard. Due to its high performance, low frequency, and high reliability, dual-core embedded processors are getting the attention of many chip manufacturers. Compatibility has been favored by many telecom equipment manufacturers and embedded high-end application integrators, but the dual-core embedded processor needs a new real-time operating system to support it, so that it can give full play to the high performance of
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "Embedded Processors"

1

Gong, Shaojie, and Zhongping Deng. "Benchmarks for Embedded Multi-processors." Thesis, Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-660.

Full text
Abstract:
<p>During the recent years, computer performance has increased dramatically. To measure </p><p>the performance of computers, benchmarks are ideal tools. Benchmarks exist in many </p><p>areas and point to different applications. For instance, in a normal PC, benchmarks can be </p><p>used to test the performance of the whole system which includes the CPU, graphic card, </p><p>memory system, etc. For multiprocessor systems, there also exist open source benchmark </p><p>programs. In our project, we gathered information about some open benchmark programs </p><p>and investigated their applicability
APA, Harvard, Vancouver, ISO, and other styles
2

Dasarathan, Dinesh. "Benchmark Characterization of Embedded Processors." NCSU, 2005. http://www.lib.ncsu.edu/theses/available/etd-05152005-170108/.

Full text
Abstract:
The design of a processor is an iterative process, with many cycles of simulation, performance analysis and subsequent changes. The inputs to these cycles of simulations are generally a selected subset of standard benchmarks. To aid in reducing the number of cycles involved in design, one can characterize these selected benchmarks and use those characteristics to hit at a good initial design that will converge faster. Methods and systems to characterize benchmarks for normal processors are designed and implemented. This thesis extends these approaches and defines an abstract system to characte
APA, Harvard, Vancouver, ISO, and other styles
3

Ryu, Soojung. "Storage Management for Embedded SIMD Processors." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/5122.

Full text
Abstract:
SIMD parallelism offers a high performance and efficient execution approach for today's broad range of portable multimedia consumer products. However, new methods are needed to meet the complex demands of high performance, embedded systems. This research explores new storage management techniques for this focused but critical application. These techniques include memory design exploration based on the application retargeting technique, storage-based systolic instruction broadcast, and systolic virtual memory to improve both the performance and efficiency of embedded SIMD systems. For an effic
APA, Harvard, Vancouver, ISO, and other styles
4

Johnson, N. E. "Code size optimization for embedded processors." Thesis, University of Cambridge, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.605626.

Full text
Abstract:
This thesis studies the problem of reducing code size produced by an optimizing compiler. We develop the Value State Dependence Graph (VSDG) as a powerful intermediate form. Nodes represent computation, and edges represent value (data) and state (control) dependencies between nodes. The edges specify a partial ordering of the nodes—sufficient ordering to maintain the I/O semantics of the source program, while allowing optimizers greater freedom to move nodes within the program to achieve better (smaller) code. Optimizations, both classical and new, transform the graph through graph rewriting r
APA, Harvard, Vancouver, ISO, and other styles
5

Mucci, Claudio <1977&gt. "Software tools or embedded reconfigurable processors." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2007. http://amsdottorato.unibo.it/402/1/claudiomucci_phdthesis.pdf.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Mucci, Claudio <1977&gt. "Software tools or embedded reconfigurable processors." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2007. http://amsdottorato.unibo.it/402/.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Hoffmann, Andreas Leupers Rainer Meyr Heinrich. "Architecture exploration for embedded processors with LISA /." Boston [u.a.] : Kluwer Acad. Publ, 2002. http://www.loc.gov/catdir/toc/fy037/2002043258.html.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Hadjiyiannis, George Ioannou. "An architecture synthesis system for embedded processors." Thesis, Massachusetts Institute of Technology, 2000. http://hdl.handle.net/1721.1/86440.

Full text
Abstract:
Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.<br>Includes bibliographical references (leaves 261-264).<br>by George Ioannou Hadjiyiannis.<br>Ph.D.
APA, Harvard, Vancouver, ISO, and other styles
9

Mistry, Jatin N. "Leakage power minimisation techniques for embedded processors." Thesis, University of Southampton, 2013. https://eprints.soton.ac.uk/348805/.

Full text
Abstract:
Leakage power is a growing concern in modern technology nodes. In some current and emerging applications, speed performance is uncritical but many of these applications rely on untethered power making energy a primary constraint. Leakage power minimisation is therefore key to maximising energy efficiency for these applications. This thesis proposes two new leakage power minimisation techniques to improve the energy efficiency of embedded processors. The first technique, called sub-clock power gating,can be used to reduce leakage power during the active mode. The technique capitalises on the ob
APA, Harvard, Vancouver, ISO, and other styles
10

Zushi, Junpei, Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada, and Koji Inoue. "Improved Policies for Drowsy Caches in Embedded Processors." IEEE, 2008. http://hdl.handle.net/2237/12081.

Full text
APA, Harvard, Vancouver, ISO, and other styles
More sources

Books on the topic "Embedded Processors"

1

Henkel, Jörg, and Sri Parameswaran, eds. Designing Embedded Processors. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5869-1.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Corporation, Intel, ed. Embedded microcontrollers & processors. Mt. Prospect, Ill: Intel Corporation, 1992.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
3

Corporation, Intel. Embedded microcontrollers and processors. Santa Clara: Intel Corporation, 1993.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
4

Corporation, Intel. Embedded microcontrollers and processors. Santa Clara: Intel Corporation, 1993.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
5

Marwedel, Peter, and Gert Goossens, eds. Code Generation for Embedded Processors. Boston, MA: Springer US, 2002. http://dx.doi.org/10.1007/978-1-4615-2323-9.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Peter, Marwedel, and Goossens Gert, eds. Code generation for embedded processors. Boston: Kluwer Academic Publishers, 1995.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
7

Marwedel, Peter. Code Generation for Embedded Processors. Boston, MA: Springer US, 2002.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
8

Embedded DSP processor design: Application specific instruction set processors. Amsterdam: Morgan Kaufmann, 2008.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
9

Liem, Clifford. Retargetable Compilers for Embedded Core Processors. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4757-6422-2.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Leupers, Rainer. Code Optimization Techniques for Embedded Processors. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/978-1-4757-3169-9.

Full text
APA, Harvard, Vancouver, ISO, and other styles
More sources

Book chapters on the topic "Embedded Processors"

1

Henkel, Jörg, Sri Parameswaran, and Newton Cheung. "Application-Specific Embedded Processors." In Designing Embedded Processors, 3–23. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5869-1_1.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Quan, Gang, and Xiaobo Sharon Hu. "Static DVFS Scheduling." In Designing Embedded Processors, 231–42. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5869-1_10.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Pillai, Padmanabhan S., and Kang G. Shin. "Dynamic DVFS Scheduling." In Designing Embedded Processors, 243–58. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5869-1_11.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Andrei, Alexandru, Petru Eles, Zebo Peng, Marcus Schmitz, and Bashir M. Al-Hashimi. "Voltage Selection for Time-Constrained Multiprocessor Systems." In Designing Embedded Processors, 259–84. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5869-1_12.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Kremer, Ulrich. "Compilation Techniques for Power, Energy, and Thermal Management." In Designing Embedded Processors, 287–303. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5869-1_13.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Hsu, Chung-Hsing, and Ulrich Kremer. "Compiler-Directed Dynamic CPU Frequency and Voltage Scaling." In Designing Embedded Processors, 305–23. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5869-1_14.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Li, Feihui, Guangyu Chen, Mahmut Kandemir, and Mustafa Karakoy. "Link Idle Period Exploitation for Network Power Management." In Designing Embedded Processors, 325–45. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5869-1_15.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Li, Zhiyuan, and Cheng Wang. "Remote Task Mapping." In Designing Embedded Processors, 347–70. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5869-1_16.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Martin, Grant. "A Power and Energy Perspective on MultiProcessors." In Designing Embedded Processors, 373–89. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5869-1_17.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Chatha, Karam S., and Krishnan Srinivasan. "System-Level Design of Network-on-Chip Architectures." In Designing Embedded Processors, 391–422. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5869-1_18.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "Embedded Processors"

1

Butera, William, and V. Michael Bove, Jr. "Literally embedded processors." In Photonics West 2001 - Electronic Imaging, edited by Sethuraman Panchanathan, V. Michael Bove, Jr., and Subramania I. Sudharsanan. SPIE, 2001. http://dx.doi.org/10.1117/12.420800.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Tillich, Stefan, Mario Kirschbaum, and Alexander Szekely. "SCA-resistant embedded processors." In the 26th Annual Computer Security Applications Conference. New York, New York, USA: ACM Press, 2010. http://dx.doi.org/10.1145/1920261.1920293.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Lakshmi, Vinay Vijendra Kumar, Arindam Mukherjee, and Bharat Joshi. "Architecture exploration for embedded processors: Design framework for embedded bio-medical processors." In IEEE SOUTHEASTCON 2013. IEEE, 2013. http://dx.doi.org/10.1109/secon.2013.6567394.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Sjödin, Jan, and Carl von Platen. "Storage allocation for embedded processors." In the international conference. New York, New York, USA: ACM Press, 2001. http://dx.doi.org/10.1145/502217.502221.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Vinay Vijendra Kumar Lakshmi, Arindam Mukherjee, and Bharat Joshi. "Architecture exploration for embedded processors." In SOUTHEASTCON 2012. IEEE, 2012. http://dx.doi.org/10.1109/secon.2012.6196917.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Gholamipour, Amir Hossein, Elaheh Bozorgzadeh, and Sudarshan Banerjee. "Energy-aware co-processor selection for embedded processors on FPGAs." In 2007 25th International Conference on Computer Design ICCD 2007. IEEE, 2007. http://dx.doi.org/10.1109/iccd.2007.4601895.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

"Session TA1: Embedded Processors for SOC." In IEEE International SOC Conference, 2004. Proceedings. IEEE, 2004. http://dx.doi.org/10.1109/socc.2004.1362400.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Fisher, Joseph A. "Customized instruction-sets for embedded processors." In the 36th ACM/IEEE conference. New York, New York, USA: ACM Press, 1999. http://dx.doi.org/10.1145/309847.309923.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Azarpeyvand, Ali, Mostafa E. Salehi, Farshad Firouzi, Amir Yazdanbakhsh, and Sied Mehdi Fakhraie. "Instruction reliability analysis for embedded processors." In 2010 IEEE 13th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE, 2010. http://dx.doi.org/10.1109/ddecs.2010.5491824.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Deris, Kaveh Jokar, and Amirali Baniasadi. "Branchless cycle prediction for embedded processors." In the 2006 ACM symposium. New York, New York, USA: ACM Press, 2006. http://dx.doi.org/10.1145/1141277.1141492.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Reports on the topic "Embedded Processors"

1

Lee, Edward A. System-Level Design Methodology for Embedded Signal Processors. Fort Belvoir, VA: Defense Technical Information Center, August 1997. http://dx.doi.org/10.21236/ada342899.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Graham, Paul, and Brent Nelson. Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing. Fort Belvoir, VA: Defense Technical Information Center, January 1999. http://dx.doi.org/10.21236/ada451425.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Wheat, Jr., Robert Mitchell, Dale A. Dalmas, and Gregory E. Dale. A Four Channel Beam Current Monitor Data Acquisition System Using Embedded Processors. Office of Scientific and Technical Information (OSTI), August 2015. http://dx.doi.org/10.2172/1209457.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Shen, Chung-Ching, Shenpei Wu, Lai-Huei Wang, Stephen Won, Kishan Sudusinghe, and Shuvra Bhattacharyya. Dataflow-Based Implementation of Layered Sensing Applications on High-Performance Embedded Processors. Fort Belvoir, VA: Defense Technical Information Center, March 2013. http://dx.doi.org/10.21236/ada582499.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Chou, Pai, Ken Hines, Kurt Partridge, and Gaetano Borriello. Control Generation for Embedded Systems Based on Composition of Modal Processes. Fort Belvoir, VA: Defense Technical Information Center, January 1998. http://dx.doi.org/10.21236/ada416531.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Wilcox, D. R., and P. N. Pham. Unix STREAMS Emulation of an Input/Output Controller (IOC) for an Embedded AN/UYK-44(V) Processor. Fort Belvoir, VA: Defense Technical Information Center, May 1993. http://dx.doi.org/10.21236/ada270867.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Learn, Mark Walter. Mitigation of cache memory using an embedded hard-core PPC440 processor in a Virtex-5 Field Programmable Gate Array. Office of Scientific and Technical Information (OSTI), February 2010. http://dx.doi.org/10.2172/984165.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Higdon, Grace Lyn. Nested Theories of Change for Adaptive Rigour. Institute of Development Studies (IDS), December 2020. http://dx.doi.org/10.19088/creid.2020.010.

Full text
Abstract:
This learning brief provides illustrative examples of three major adaptations the Coalition for Religious Equality and Inclusive Development (CREID) programme has undertaken while working within fragile contexts to promote freedom of religion or beilief (FoRB). These examples highlight how the programme has utilised embedded monitoring, evaluation, and learning (MEL) strategies to encourage what Ramalingam et al. (2019) refer to as ‘adaptive rigour’, a concept which underscores the importance of transparent documentation of programmatic decision making processes during programme adaptations. I
APA, Harvard, Vancouver, ISO, and other styles
9

Jha, Deepika, Sudeshna Mitra, Amlanjyoti Goswami, Sahil Sasidharan, and Kaye Lushington. Land Records Modernisation in India: Bihar. Indian Institute for Human Settlements, 2021. http://dx.doi.org/10.24943/9788195648535.

Full text
Abstract:
This work provides an institutional, legal and policy review of crucial aspects of land records modernisation systems in Bihar. The state’s progress with land records modernisation efforts has been historically slow but in the last few years, it has taken long strides in computerisation of land records and associated processes, and is on the way to a more accessible land information system. Bihar is a significant example to understand that in certain parts of India, issues of land and property ownership are embedded in socio-historical conditions, which can be addressed only in part by current
APA, Harvard, Vancouver, ISO, and other styles
10

Clark, Louise. The Diamond of Influence: A Model For Exploring Behaviour in Research to Policy Linkages. Institute of Development Studies (IDS), November 2020. http://dx.doi.org/10.19088/apra.2020.011.

Full text
Abstract:
This learning paper presents an initial analysis of the emerging research to policy linkages within the Agricultural Policy Research in Africa (APRA) programme of the Future Agricultures Consortium, which is funded by the Foreign, Commonwealth &amp; Development Office (FCDO). APRA has an innovative monitoring, evaluation and learning approach known as the ‘Accompanied Learning on Relevance and Effectiveness’ (ALRE), which is being delivered by a small team of embedded evaluation specialists. This paper discusses how ALRE has applied the COM-B (Capability, Opportunity, Motivation and Behaviour)
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic 'Embedded Processors' for particular source types:
Journal articles Dissertations / Theses Books
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography