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Dissertations / Theses on the topic 'Embedded Processors'

Author: Grafiati

Published: 4 June 2021

Last updated: 6 September 2023

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1

Gong, Shaojie, and Zhongping Deng. "Benchmarks for Embedded Multi-processors." Thesis, Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-660.

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<p>During the recent years, computer performance has increased dramatically. To measure </p><p>the performance of computers, benchmarks are ideal tools. Benchmarks exist in many </p><p>areas and point to different applications. For instance, in a normal PC, benchmarks can be </p><p>used to test the performance of the whole system which includes the CPU, graphic card, </p><p>memory system, etc. For multiprocessor systems, there also exist open source benchmark </p><p>programs. In our project, we gathered information about some open benchmark programs </p><p>and investigated their applicability

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2

Dasarathan, Dinesh. "Benchmark Characterization of Embedded Processors." NCSU, 2005. http://www.lib.ncsu.edu/theses/available/etd-05152005-170108/.

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The design of a processor is an iterative process, with many cycles of simulation, performance analysis and subsequent changes. The inputs to these cycles of simulations are generally a selected subset of standard benchmarks. To aid in reducing the number of cycles involved in design, one can characterize these selected benchmarks and use those characteristics to hit at a good initial design that will converge faster. Methods and systems to characterize benchmarks for normal processors are designed and implemented. This thesis extends these approaches and defines an abstract system to characte

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3

Ryu, Soojung. "Storage Management for Embedded SIMD Processors." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/5122.

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SIMD parallelism offers a high performance and efficient execution approach for today's broad range of portable multimedia consumer products. However, new methods are needed to meet the complex demands of high performance, embedded systems. This research explores new storage management techniques for this focused but critical application. These techniques include memory design exploration based on the application retargeting technique, storage-based systolic instruction broadcast, and systolic virtual memory to improve both the performance and efficiency of embedded SIMD systems. For an effic

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4

Johnson, N. E. "Code size optimization for embedded processors." Thesis, University of Cambridge, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.605626.

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This thesis studies the problem of reducing code size produced by an optimizing compiler. We develop the Value State Dependence Graph (VSDG) as a powerful intermediate form. Nodes represent computation, and edges represent value (data) and state (control) dependencies between nodes. The edges specify a partial ordering of the nodes—sufficient ordering to maintain the I/O semantics of the source program, while allowing optimizers greater freedom to move nodes within the program to achieve better (smaller) code. Optimizations, both classical and new, transform the graph through graph rewriting r

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Mucci, Claudio <1977&gt. "Software tools or embedded reconfigurable processors." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2007. http://amsdottorato.unibo.it/402/1/claudiomucci_phdthesis.pdf.

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Mucci, Claudio <1977&gt. "Software tools or embedded reconfigurable processors." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2007. http://amsdottorato.unibo.it/402/.

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7

Hoffmann, Andreas Leupers Rainer Meyr Heinrich. "Architecture exploration for embedded processors with LISA /." Boston [u.a.] : Kluwer Acad. Publ, 2002. http://www.loc.gov/catdir/toc/fy037/2002043258.html.

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8

Hadjiyiannis, George Ioannou. "An architecture synthesis system for embedded processors." Thesis, Massachusetts Institute of Technology, 2000. http://hdl.handle.net/1721.1/86440.

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Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.<br>Includes bibliographical references (leaves 261-264).<br>by George Ioannou Hadjiyiannis.<br>Ph.D.

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9

Mistry, Jatin N. "Leakage power minimisation techniques for embedded processors." Thesis, University of Southampton, 2013. https://eprints.soton.ac.uk/348805/.

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Leakage power is a growing concern in modern technology nodes. In some current and emerging applications, speed performance is uncritical but many of these applications rely on untethered power making energy a primary constraint. Leakage power minimisation is therefore key to maximising energy efficiency for these applications. This thesis proposes two new leakage power minimisation techniques to improve the energy efficiency of embedded processors. The first technique, called sub-clock power gating,can be used to reduce leakage power during the active mode. The technique capitalises on the ob

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10

Zushi, Junpei, Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada, and Koji Inoue. "Improved Policies for Drowsy Caches in Embedded Processors." IEEE, 2008. http://hdl.handle.net/2237/12081.

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11

Hanono, Silvina Zimi. "AVIV : a retargetable code generator for embedded processors." Thesis, Massachusetts Institute of Technology, 1999. http://hdl.handle.net/1721.1/80080.

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Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.<br>Vita.<br>Includes bibliographical references (p. 225-231).<br>by Silvina Zimi Hanono.<br>Ph.D.

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12

BenDor, Jonathan, and J. D. Baker. "Processing Real-Time Telemetry with Multiple Embedded Processors." International Foundation for Telemetering, 1994. http://hdl.handle.net/10150/611671.

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International Telemetering Conference Proceedings / October 17-20, 1994 / Town & Country Hotel and Conference Center, San Diego, California<br>This paper describes a system in which multiple embedded processors are used for real-time processing of telemetry streams from satellites and radars. Embedded EPC-5 modules are plugged into VME slots in a Loral System 550. Telemetry streams are acquired and decommutated by the System 550, and selected parameters are packetized and appended to a mailbox which resides in VME memory. A Windows-based program continuously fetches packets from the mailbox, p

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13

Kufel, Jedrzej. "Techniques and validation for protection of embedded processors." Thesis, University of Southampton, 2015. https://eprints.soton.ac.uk/381185/.

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Advances in technology scaling and miniaturization of on-chip structures have caused an increasing complexity of modern devices. Due to immense time-to-market pressures, the reusability of intellectual property (IP) sub-systems has become a necessity. With the resulting high risks involved with such a methodology, securing IP has become a major concern. Despite a number of proposed IP protection (IPP) techniques being available, securing an IP in the register transfer level (RTL) is not a trivial task, with many of the techniques presenting a number of shortfalls or design limitations. The mos

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14

Ragel, Roshan Gabriel Computer Science &amp Engineering Faculty of Engineering UNSW. "Architectural support for security and reliability in embedded processors." Awarded by:University of New South Wales. Computer Science and Engineering, 2006. http://handle.unsw.edu.au/1959.4/28797.

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Security and reliability in processor based systems are concerns requiring adroit solutions. Security is often compromised by code injection attacks, jeopardizing even ???trusted software???. Reliability is of concern, where unintended code is executed in modern processors with ever smaller feature sizes and low voltage swings causing bit flips. Countermeasures by software-only approaches increase code size and therefore significantly reduce performance. Hardware assisted approaches use additional hardware monitors and thus incur considerably high hardware cost and have scalability problems. C

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15

Xu, Xianhong. "Code memory compression technologies for embedded arm/thumb processors." Thesis, University of Bath, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.442019.

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16

Liao, Stan Yi-Huang 1972. "Code generation and optimization for embedded digital signal processors." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/11048.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1996.<br>Vita.<br>Includes bibliographical references (p. [203]-211).<br>by Stan Yi-Huang Liao.<br>Ph.D.

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17

Chakraborty, Samarjit. "System-level timing analysis and scheduling for embedded packet processors /." Zürich : Institut für Technische Informatik und Kommunikationsnetze TIK, ETH Zürich, 2003. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=15093.

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18

Talavera, Velilla Guillermo. "Scratchpad-oriented address generation for low-power embedded VLIW processors." Doctoral thesis, Universitat Autònoma de Barcelona, 2009. http://hdl.handle.net/10803/5780.

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Actualmente, los sistemas encastados están creciendo a un ritmo impresionante y proporcionan cada vez aplicaciones más sofisticadas. Un conjunto de creciente importancia son los sistemas multimedia portátiles de tiempo real y los sistemas de comunicación de procesado digital de señal: teléfonos móviles, PDAs, cámaras digitales, consolas portátiles de juegos, terminales multimedia, netbooks, etc. Estos sistemas requieren computación específica de alto rendimiento, generalmente con restricciones de tiempo real y calidad de servicio (Quality of Service - QoS), que han de ejecutarse con un nivel

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Caulfield, Ian Michael. "Complexity-effective superscalar embedded processors using instruction-level distributed processing." Thesis, University of Cambridge, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.613309.

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20

Franke, Bjorn. "Compilation techniques for high-performance embedded systems with multiple processors." Thesis, University of Edinburgh, 2004. http://hdl.handle.net/1842/568.

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Despite the progress made in developing more advanced compilers for embedded systems, programming of embedded high-performance computing systems based on Digital Signal Processors (DSPs) is still a highly skilled manual task. This is true for single-processor systems, and even more for embedded systems based on multiple DSPs. Compilers often fail to optimise existing DSP codes written in C due to the employed programming style. Parallelisation is hampered by the complex multiple address space memory architecture, which can be found in most commercial multi-DSP configurations. This thesis devel

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21

Liu, ke. "A Simulation Based Approach to EstimateEnergy Consumption for Embedded Processors." Thesis, Högskolan i Halmstad, Centrum för forskning om inbyggda system (CERES), 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-29913.

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Embedded systems have entered a new era in which system designers have to consider more and more strict energy consumption constraints. This thesis reviewsprevious studies of the processor energy consumption estimation. Particularly, wefocus on instruction-level energy consumption for embedded processors and explorethe energy consumption model for manycore architecture in real traffic pattern.The purpose of this thesis project is to estimate energy consumption and constructan energy model using an instruction-set simulator for embedded processors. OpenVirtual Platforms (OVP) and Epiphany Singl

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Lins, Filipe Maciel. "The effects of the compiler optimizations in embedded processors reliability." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2017. http://hdl.handle.net/10183/169248.

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O recente avanço tecnológico dos processadores embarcados aumentou a complexidade dos compiladores e o uso de recursos heterogêneos, como Arranjo de Portas Programáveis em Campo (Field Programmable Gate Array - FPGA) e Unidade de Processamento Gráfico (Graphics Processing Unit - GPU), integrado aos processadores. Além disso, aumentou-se o uso de componentes de prateleira (Commercial off-the-shelf - COTS) em aplicações críticas, ao invés de chips tolerantes a radiação, pois os COTS podem ser mais baratos, flexíveis, terem uma rápida colocação no mercado e um menor consumo de energia. No entanto

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23

Cooke, Alan. "The Killer App – Combining Embedded Processors, FPGAs and Smart Software." International Foundation for Telemetering, 2016. http://hdl.handle.net/10150/624252.

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In this paper, the benefits and advantages of combining advanced embedded processing capabilities with an FPGA based approach within a Data Acquisition Unit (DAU) are discussed. The paper begins with a discussion of some of the services and functionality that such a system enables. Basic features such as system discovery, verification, configuration and upgrade are discussed in addition to other value added services such as continuous built in test (CBIT) and embedded real-time parameter quick-look. Finally, the paper discusses some advanced services that could be deployed to these syste

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24

Akturan, Cagdas. "Performance enhancing software loop transformations for embedded VLIW/EPIC processors." Access restricted to users with UT Austin EID Full text (PDF) from UMI/Dissertation Abstracts International, 2001. http://wwwlib.umi.com/cr/utexas/fullcit?p3035929.

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25

Gayen, Neela. "Automatic parallelization of stream programs for resource efficient embedded processors." Thesis, Queensland University of Technology, 2021. https://eprints.qut.edu.au/213058/1/Neela_Gayen_Thesis.pdf.

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This thesis considers how to exploit the specific characteristics of data streaming functions and multi-core processors to increase throughput through appropriate software process mappings. The hypothesis is that large numbers of low-power processors can achieve high throughput for streaming applications if a good mapping is provided. The innovation is to use compilation principles to guide the mapping, rather than heuristics. Three increasingly complex approaches are developed that focus on computational bottlenecks, then adds communication overheads, and lastly adds the costs of splitting

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26

Franz, Jonathan D. Duren Russell Walker. "An evaluation of CoWare Inc.'s Processor Designer tool suite for the design of embedded processors." Waco, Tex. : Baylor University, 2008. http://hdl.handle.net/2104/5254.

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27

Lau, ChokSheak. "An optimization framework for embedded processors with auto-modify addressing modes." Thesis, Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-11152004-212501/unrestricted/Lau%5FChokSheak%5F200412%5Fmast.pdf.

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Thesis (M.S.)--Computing, Georgia Institute of Technology, 2005.<br>Pande, Santosh, Committee Chair ; Lee, Hsien-Hsin Sean, Committee Member ; Uh, Gang-Ryung, Committee Member. Includes bibliographical references.

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28

Ganesan, Sharan Kumaar. "Design and Implementation of Digital Spiking Neurons for Ultra-low-Power In-cluster processors." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-198115.

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Neuromorphic computing is a recent and growing field of research. Its conceptual attractiveness is due to the potential it has in deep learning applications such as sensor networks, low-power computer vision, robotics and other fields. Inspired by the functioning of brain, different neural network models have been devised, each with their own special focus on certain applications. Using such computing models are already helping us in different cases such as image, character and voice recognition, data analysis, stock market prediction, etc. Among the multitude of artificial neural models avail

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Mourad, Azzam. "A Selective Dynamic Compiler for Embedded Java Virtual Machine Targeting ARM Processors." Thesis, Université Laval, 2005. http://www.theses.ulaval.ca/2005/22534/22534.pdf.

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Ce travail présente une nouvelle technique de compilation dynamique sélective pour les systèmes embarqués avec processeurs ARM. Ce compilateur a été intégré dans la plateforme J2ME/CLDC (Java 2 Micro Edition for Connected Limited Device Con- figuration). L’objectif principal de notre travail est d’obtenir une machine virtuelle accélérée, légère et compacte prête pour l’exécution sur les systèmes embarqués. Cela est atteint par l’implémentation d’un compilateur dynamique sélectif pour l’architecture ARM dans la Kilo machine virtuelle de Sun (KVM). Ce compilateur est appelé Armed E-Bunny. Premiè

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BHALGAT, ASHISH ZUMBARLAL. "INSTRUCTION SCHEDULING TO HIDE LOAN/STORE LATENCY IN IRREGULAR ARCHITECTURE EMBEDDED PROCESSORS." University of Cincinnati / OhioLINK, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=ucin982261963.

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Arunachalam, Srinath. "An online wear state monitoring methodology for off-the-shelf embedded processors." DigitalCommons@USU, 2015. https://digitalcommons.usu.edu/etd/4552.

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The continued scaling of transistors has led to an exponential increase in on-chip power density, which has resulted in increasing temperature. In turn, the increase in temperature directly leads to the increase in the rate of wear of a processor. Negative-bias temperature instability (NBTI) is one of the most dominant integrated circuit (IC) failure mechanisms [13, 5] that strongly depends on temperature. NBTI manifests in the form of increased circuit delays which can lead to timing failures and processor crashes. The ability to monitor the wear progression of a processor due to NBTI is valu

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Bechara, Charly. "Study and design of a manycore architecture with multithreaded processors for dynamic embedded applications." Phd thesis, Université Paris Sud - Paris XI, 2011. http://tel.archives-ouvertes.fr/tel-00713536.

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Embedded systems are getting more complex and require more intensive processing capabilities. They must be able to adapt to the rapid evolution of the high-end embedded applications that are characterized by their high computation-intensive workloads (order of TOPS: Tera Operations Per Second), and their high level of parallelism. Moreover, since the dynamism of the applications is becoming more significant, powerful computing solutions should be designed accordingly. By exploiting efficiently the dynamism, the load will be balanced between the computing resources, which will improve greatly t

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Oliveira, Ádria Barros de. "Applying dual core lockstep in embedded processors to mitigate radiation induced soft errors." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2017. http://hdl.handle.net/10183/173785.

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Os processadores embarcados operando em sistemas de segurança ou de missão crítica não podem falhar. Qualquer falha neste tipo de aplicação pode levar a consequências inaceitáveis, como risco de vida ou danos à propriedade ou ao meio ambiente. Os sistemas embarcados que operam em aplicações aeroespaciais são sucetíveis à falhas transientes induzidas por radiação. Entretanto, os efeitos de radiação também podem ser observados ao nível do solo. Falhas transientes afetam os processadores modificando os valores armazenados em elementos de memória, tais como registradores e memória de dados. Essas

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Chen, Zhimin. "SCA-Resistant and High-Performance Embedded Cryptography Using Instruction Set Extensions and Multi-Core Processors." Diss., Virginia Tech, 2011. http://hdl.handle.net/10919/51256.

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Nowadays, we use embedded electronic devices in almost every aspect of our daily lives. They represent our electronic identity; they store private information; they monitor health status; they do confidential communications, and so on. All these applications rely on cryptography and, therefore, present us a research objective: how to implement cryptography on embedded systems in a trustworthy and efficient manner. Implementing embedded cryptography faces two challenges - constrained resources and physical attacks. Due to low cost constraints and power budget constraints, embedded device

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Lide, David A., and Stephen Talabac. "The Use of Digital Signal Processors in Front-End Weather Satellite Telemetry Processing." International Foundation for Telemetering, 1994. http://hdl.handle.net/10150/608545.

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International Telemetering Conference Proceedings / October 17-20, 1994 / Town & Country Hotel and Conference Center, San Diego, California<br>This paper discusses the use of DSP technology in the embedded real time ingest and pre-processing of weather satellite data. Specifically, case studies are presented in the use of Texas Instrument TMS 320 processors as front-end handlers of GOES MODE AAA and GOES GVAR data formats.

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Azambuja, José Rodrigo Furlanetto de. "Designing and evaluating hybrid techniques to detect transient faults in processors embedded in FPGAs." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2013. http://hdl.handle.net/10183/102687.

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Der aktuelle Stand der Technologie bringt schnellere und kleinere Bausteine für die Herstellung von integrierten Schaltungen mit sich, die während sie effizienter sind auch anfälliger für Strahlung werden. Kleinere Abmessungen der Transistoren, höhere Integrationsdichte, geringere Versorgungsspannungen und höhere Betriebsfrequenzen sind einige der Charakteristika, die energiegeladene Partikel zu einer Herausforderung machen, wenn man integrierte Schaltungen in rauen Umgebungen einsetzt. Diese Art der Partikel hat einen sehr großen Einfluss auf Prozessoren, die in einer solchen Umgebung eingese

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Musasa, Mutombo Mike. "Evaluation of embedded processors for next generation asic : Evaluation of open source Risc-V processors and tools ability to perform packet processing operations compared to Arm Cortex M7 processors." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-299656.

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Nowadays, network processors are an integral part of information technology. With the deployment of 5G network ramping up around the world, numerous new devices are going to take advantage of their processing power and programming flexibility. Contemporary information technology providers of today such as Ericsson, spend a great amount of financial resources on licensing deals to use processors with proprietary instruction set architecture designs from companies like Arm holdings. There is a new non-proprietary instruction set architecture technology being developed known as Risc-V. There are

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Webb, Robert L. "ASYNCHRONOUS MIPS PROCESSORS: EDUCATIONAL SIMULATIONS." DigitalCommons@CalPoly, 2010. https://digitalcommons.calpoly.edu/theses/381.

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The system clock has been omnipresent in most mainstream chip designs. While simplifying many design problems the clock has caused the problems of clock skew, high power consumption, electromagnetic interference, and worst-case performance. In recent years, as the timing constraints of synchronous designs have been squeezed ever tighter, the efficiencies of asynchronous designs have become more attractive. By removing the clock, these issues can be mitigated. How- ever, asynchronous designs are generally more complex and difficult to debug. In this paper I discuss the advantages of asynchronou

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El, Moussawi Ali Hassan. "SIMD-aware word length optimization for floating-point to fixed-point conversion targeting embedded processors." Thesis, Rennes 1, 2016. http://www.theses.fr/2016REN1S150/document.

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Afin de limiter leur coût et/ou leur consommation électrique, certains processeurs embarqués sacrifient le support matériel de l'arithmétique à virgule flottante. Pourtant, pour des raisons de simplicité, les applications sont généralement spécifiées en utilisant l'arithmétique à virgule flottante. Porter ces applications sur des processeurs embarqués de ce genre nécessite une émulation logicielle de l'arithmétique à virgule flottante, qui peut sévèrement dégrader la performance. Pour éviter cela, l'application est converti pour utiliser l'arithmétique à virgule fixe, qui a l'avantage d'être p

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Raisi, Mehrdad. "Adaptive applications of OPTO-VLSI processors in WDM networks." Thesis, Edith Cowan University, Research Online, Perth, Western Australia, 2004. https://ro.ecu.edu.au/theses/840.

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Communication is an inseparable part of human life and its nature continues to evolve and improve. The advent of laser was a herald to the new possibilities in the communication world. In recent years technologies such as Wavelength Division Multiplexing (WDM) and Erbium Doped Fiber Amplifiers (EDFA) have afforded significant boost to the practice of optical communication. At the heart of this brave new world is the need to dynamically/ adaptively steer/route beams of light carrying very large amounts of data. In recent years many techniques have been proposed for this purpose by various resea

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De, Guzman Ethan Paul Palisoc. "Energy Efficient Computing using Scalable General Purpose Analog Processors." DigitalCommons@CalPoly, 2021. https://digitalcommons.calpoly.edu/theses/2305.

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Due to fundamental physical limitations, conventional digital circuits have not been able to scale at the pace expected from Moore’s law. In addition, computationally intensive applications such as neural networks and computer vision demand large amounts of energy from digital circuits. As a result, energy efficient alternatives are needed in order to provide continued performance scaling. Analog circuits have many well known benefits: the ability to store more information onto a single wire and efficiently perform mathematical operations such as addition, subtraction, and differential equatio

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Kim, Jongmyon. "Architectural Enhancements for Color Image and Video Processing on Embedded Systems." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6948.

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As emerging portable multimedia applications demand more and more computational throughput with limited energy consumption, the need for high-efficiency, high-throughput embedded processing is becoming an important challenge in computer architecture. In this regard, this dissertation addresses application-, architecture-, and technology-level issues in existing processing systems to provide efficient processing of multimedia in many, or ideally all, of its form. In particular, this dissertation explores color imaging in multimedia while focusing on two architectural enhancements for memory-

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DUTT, Nikil D., Hiroaki TAKADA, and Hiroyuki TOMIYAMA. "Memory Data Organization for Low-Energy Address Buses." Institute of Electronics, Information and Communication Engineers, 2004. http://hdl.handle.net/2237/15042.

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Revy, Guillaume. "Implementation of binary floating-point arithmetic on embedded integer processors - Polynomial evaluation-based algorithms and certified code generation." Phd thesis, Ecole normale supérieure de lyon - ENS LYON, 2009. http://tel.archives-ouvertes.fr/tel-00469661.

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Aujourd'hui encore, certains systèmes embarqués n'intègrent pas leur propre unité flottante, pour des contraintes de surface, de coût et de consommation d'énergie. Cependant, ce type d'architecture est largement utilisé dans des domaines d'application extrêmement exigeants en calculs flottants (le multimédia, l'audio et la vidéo ou les télécommunications). Pour compenser le fait que l'arithmétique flottante ne soit pas implantée en matériel, elle doit être émulée efficacement à travers une implantation logicielle. Cette thèse traite de la conception et de l'implantation d'un support logiciel e

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TAVARES, Eduardo Antônio Guimarães. "A time Petri net based approach for software synthesis in Hard Real-Time embedded systems with multiple processors." Universidade Federal de Pernambuco, 2006. https://repositorio.ufpe.br/handle/123456789/2589.

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Made available in DSpace on 2014-06-12T15:59:31Z (GMT). No. of bitstreams: 2 arquivo5135_1.pdf: 1049051 bytes, checksum: e5be25e2aa87cb17b0788411f129a4a8 (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2006<br>Atualmente, sistemas embarcados são ubíquos. Em outras palavras, eles estão em todos os lugares. Desde utilitários domésticos (ex: fornos microondas, refrigeradores, videocassetes, máquinas de fax, máquinas de lavar roupa, alarmes) até equipamentos militares (ex: mísseis guiados, satélites espiões, sondas espaciais, aeronaves), nó

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Chielle, Eduardo. "Selective Software-Implemented Hardware Fault Tolerance Techniques to Detect Soft Errors in Processors with Reduced Overhead." Doctoral thesis, Universidad de Alicante, 2016. http://hdl.handle.net/10045/62467.

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Software-based fault tolerance techniques are a low-cost way to protect processors against soft errors. However, they introduce significant overheads to the execution time and code size, which consequently increases the energy consumption. System operating with time or energy restrictions may not be able to use these techniques. For this reason, this work proposes new software-based fault tolerance techniques with lower overheads and similar fault coverage to state-of-the-art software techniques. Thus, they can meet the system constraints. In addition, the shorter execution time reduces the ex

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Guan, Nan. "New Techniques for Building Timing-Predictable Embedded Systems." Doctoral thesis, Uppsala universitet, Avdelningen för datorteknik, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-209623.

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Embedded systems are becoming ubiquitous in our daily life. Due to close interaction with physical world, embedded systems are typically subject to timing constraints. At design time, it must be ensured that the run-time behaviors of such systems satisfy the pre-specified timing constraints under any circumstance. In this thesis, we develop techniques to address the timing analysis problems brought by the increasing complexity of underlying hardware and software on different levels of abstraction in embedded systems design. On the program level, we develop quantitative analysis techniques to p

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Colombet, Quentin. "Decoupled (SSA-based) register allocators : from theory to practice, coping with just-in-time compilation and embedded processors constraints." Phd thesis, Ecole normale supérieure de lyon - ENS LYON, 2012. http://tel.archives-ouvertes.fr/tel-00764405.

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My thesis deals with register allocation. During this phase, the compiler has to assign variables of the source program, in an arbitrary big number, to actual registers of the processor, in a limited number k. Recent works, for instance the thesis of F. Bouchez and S. Hack, have shown that it is possible to split in two different decoupled step this phase: the spill - store the variables into memory to release registers - followed by the registers assignment. These works demonstrate the feasibility of this decoupling relying on a theoretic framework and some assumptions. In particular, it is s

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Schölzel, Mario [Verfasser], and Heinrich Theodor [Akademischer Betreuer] Vierhaus. "Self-testing and self-repairing embedded processors: techniques for statically scheduled superscalar architectures / Mario Schölzel ; Betreuer: Heinrich Theodor Vierhaus." Cottbus : BTU Cottbus - Senftenberg, 2014. http://d-nb.info/1114664901/34.

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Burgio, Paolo <1981&gt. "Use of shared memory in the context of embedded multi-core processors: exploration of the technology and its limits." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2013. http://amsdottorato.unibo.it/6187/1/Burgio_Paolo_Tesi.pdf.

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Modern embedded systems embrace many-core shared-memory designs. Due to constrained power and area budgets, most of them feature software-managed scratchpad memories instead of data caches to increase the data locality. It is therefore programmers’ responsibility to explicitly manage the memory transfers, and this make programming these platform cumbersome. Moreover, complex modern applications must be adequately parallelized before they can the parallel potential of the platform into actual performance. To support this, programming languages were proposed, which work at a high level of abstra

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