Relevant bibliographies by topics / Energy Delay Product(EDP)

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers
  5. Reports

Academic literature on the topic 'Energy Delay Product(EDP)'

Author: Grafiati
Published: 2 June 2025
Last updated: 31 July 2025

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Journal articles on the topic "Energy Delay Product(EDP)"

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Seok, Hyelin, Hyoju Seo, Jungwon Lee, and Yongtae Kim. "COREA: Delay- and Energy-Efficient Approximate Adder Using Effective Carry Speculation." Electronics 10, no. 18 (2021): 2234. http://dx.doi.org/10.3390/electronics10182234.

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This paper presents a delay- and energy-efficient approximate adder design exploiting an effective carry speculation scheme with error reduction. The proposed scheme reduces the delay and improves the energy efficiency without any significant accuracy degradation by effectively adding the predicted carry input using the OR operation. Additionally, the error reduction technique improves the overall computation accuracy at the expense of a few logic gates. As a result, the proposed adder achieves 3.84- and 7.79-times greater energy and energy-delay product (EDP) efficiencies than the traditional
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García, José C., Juan A. Montiel-Nelson, and Saeid Nooshabadi. "Versatile CMOS Current Conveyor for Digital VLSI Systems with Low-Voltage Power Supply." Journal of Low Power Electronics 15, no. 3 (2019): 323–28. http://dx.doi.org/10.1166/jolpe.2019.1617.

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A low voltage supply CMOS current conveyor circuit for digital input signals from 0.25 V up to 1.2 V is presented. The circuit is optimized and pre-layout simulated in a 65 nm CMOS process technology. At the target design voltage of 1.2 V, the current conveyor has a propagation delay of 2.86 ns, an energy consumption of only 80.9 pJ, and energy-delay product (EDP) of 231 pJns for resistive load of 10 kΩ. Superior performance of this work is demonstrated through comparison with other similar published work at a frequency of 5 MHz. It is shown that the proposed circuit is suitable for digital si
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Pérez, Santiago S., Alessandro Bedoya, Luis Miguel Prócel, and Ramiro Taco. "Exploiting TFET-based technology for energy-efficient STT-MRAM cells." International Journal of Applied Electromagnetics and Mechanics 73, no. 1 (2023): 15–24. https://doi.org/10.3233/jae-220300.

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Spin-transfer torque magnetic random-access memory (STT-MRAM) has been demonstrated to be a leading candidate for on-chip memory technology. In this work, double-barrier magnetic tunnel junction (DMTJ) is exploited to define STT-MRAMs at the circuit-level (i.e. at the bitcell level). The DMTJ-based bitcells are built from tunnel-FET technology and benchmarked against a calibrated 10 nm-FinFET technology model. STT-MRAM bitcells operate in the ultra-low voltage domain, and are evaluated in terms of energy-efficiency and area. Simulation results points out that the tunnel-FET based solution is t
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Shahrokhi, Seyed Hossein, Mehdi Hosseinzadeh, Midia Reshadi, and Saeid Gorgin. "A Novel High-Speed and Low-PDP Approximate Full Adder Cell for Image Blending." Mathematics 11, no. 12 (2023): 2649. http://dx.doi.org/10.3390/math11122649.

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This paper presents a new and high-performance inaccurate Full Adder Cell utilizing the Carbon Nanotube Field Effect Transistor (CNFET) technology. Comprehensive simulations are performed at the transistor and application levels to justify the performance of our design. Simulations performed using the HSPICE tool confirm the significant improvement in the performance of the proposed circuit delay, power-delay product (PDP) and energy-delay product (EDP) compared to competitor designs. Additionally, via a MATLAB tool, the image blending (alpha blending) application uses inaccurate Full Adder ce
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Nirlakalla, Ravi, Rao Subba, and Talari Jayachandra-Prasad. "Performance evaluation of high speed compressors for high speed multipliers." Serbian Journal of Electrical Engineering 8, no. 3 (2011): 293–306. http://dx.doi.org/10.2298/sjee1103293n.

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This paper describes high speed compressors for high speed parallel multipliers like Booth Multiplier, Wallace Tree Multiplier in Digital Signal Processing (DSP). This paper presents 4-3, 5-3, 6-3 and 7-3 compressors for high speed multiplication. These compressors reduce vertical critical path more rapidly than conventional compressors. A 5-3 conventional compressor can take four steps to reduce bits from 5 to 3, but the proposed 5-3 takes only 2 steps. These compressors are simulated with H-Spice at a temperature of 25?C at a supply voltage 2.0V using 90nm MOSIS technology. The Power, Delay,
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Chin, Huei Chaeng, Cheng Siong Lim, Weng Soon Wong, Kumeresan A. Danapalasingam, Vijay K. Arora, and Michael Loong Peng Tan. "Enhanced Device and Circuit-Level Performance Benchmarking of Graphene Nanoribbon Field-Effect Transistor against a Nano-MOSFET with Interconnects." Journal of Nanomaterials 2014 (2014): 1–14. http://dx.doi.org/10.1155/2014/879813.

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Comparative benchmarking of a graphene nanoribbon field-effect transistor (GNRFET) and a nanoscale metal-oxide-semiconductor field-effect transistor (nano-MOSFET) for applications in ultralarge-scale integration (ULSI) is reported. GNRFET is found to be distinctly superior in the circuit-level architecture. The remarkable transport properties of GNR propel it into an alternative technology to circumvent the limitations imposed by the silicon-based electronics. Budding GNRFET, using the circuit-level modeling software SPICE, exhibits enriched performance for digital logic gates in 16 nm process
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Abdul Tahrim, ‘Aqilah binti, Huei Chaeng Chin, Cheng Siong Lim, and Michael Loong Peng Tan. "Design and Performance Analysis of 1-Bit FinFET Full Adder Cells for Subthreshold Region at 16 nm Process Technology." Journal of Nanomaterials 2015 (2015): 1–13. http://dx.doi.org/10.1155/2015/726175.

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The scaling process of the conventional 2D-planar metal-oxide semiconductor field-effect transistor (MOSFET) is now approaching its limit as technology has reached below 20 nm process technology. A new nonplanar device architecture called FinFET was invented to overcome the problem by allowing transistors to be scaled down into sub-20 nm region. In this work, the FinFET structure is implemented in 1-bit full adder transistors to investigate its performance and energy efficiency in the subthreshold region for cell designs of Complementary MOS (CMOS), Complementary Pass-Transistor Logic (CPL), T
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Kim, Junha, and Moonju Park. "Dynamic Frequency Scaling Regarding Memory for Energy Efficiency of Embedded Systems." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 3 (2018): 1798. http://dx.doi.org/10.11591/ijece.v8i3.pp1798-1804.

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Memory significantly affects the power consumption of embedded systems as well as performance. CPU frequency scaling for power management could fail in optimizing the energy efficiency without considering the memory access. In this paper, we analyze the power consumption and energy efficiency of an embedded system that supports dynamic scaling of frequency for both CPU and memory access. The power consumption of the CPU and the memory is modeled to show that the memory access rate affects the energy efficiency and the CPU frequency selection. Based on the power model, a method for frequency se
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Cao, Peng, and Jingjing Guo. "Standard Cell Sizing for Worst-Case Performance Optimization Considering Process Variation in Subthreshold Region." Electronics 13, no. 22 (2024): 4477. http://dx.doi.org/10.3390/electronics13224477.

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Ultra-low-voltage design brings considerable outcomes in power reduction and energy efficiency improvement at the cost of performance degradation and uncertainty. Conventional standard cell design methodology cannot guarantee optimal performance for subthreshold operations due to the lack of consideration of process variation. In this paper, an effective subthreshold cell sizing method is proposed to minimize the worst-case propagation delay by deriving the optimal pMOS-to-nMOS width ratio (β) analytically, which reveals the relation between the minimal worst-case delay and the process paramet
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Abid, Z., Dalia A. El-Dib, and Rizwan Mudassir. "Modified Operand Decomposition Multiplication for High Performance Parallel Multipliers." Journal of Circuits, Systems and Computers 25, no. 12 (2016): 1650149. http://dx.doi.org/10.1142/s0218126616501498.

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A low power operand decomposition multiplication architecture implementation is modified to further reduce its power dissipation and delay. First, the multiplier’s implementation was modified to generate the partial products using NAND gates instead of AND and OR gates in order to reduce the number of transistors (area utilized) and to reduce the delay. Then, new types of adders and (4:2) compressors, that accept negatively weighted bits are used to reduce the number of inverters. Therefore, the resulting multiplier architecture reduces the number of transistors significantly. These modificati
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Dissertations / Theses on the topic "Energy Delay Product(EDP)"

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Ekambavanan, Sasidharan. "Encoding serial data for energy-delay-product and energy minimization." 2007. http://hdl.handle.net/1969.1/ETD-TAMU-1490.

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Serial or parallel buses are widely used to communicate information in most electronic devices. The energy consumed by bus interconnects may comprise a significant portion of the overall energy consumption of the device. Hence, techniques to reduce the energy consumption of bus interconnects have become an important area of research. One common method adopted to reduce energy is Bus Encoding, where redundant bits are added to the original data stream either in time or space to reduce the energy consumption. In this thesis, a novel bus encoding technique, called the Multiple Codebook Approach (M
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Bo-ZhouKe and 柯柏州. "Low Cost and Low Energy-Delay-Product Sub-threshold Logic Design." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/65954650473020057391.

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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>101<br>Sub-threshold operation has been shown to be a promising approach for ultra-low power applications, such as portable mobile devices, biomedical electronic systems and wireless sensor network. However, operating logic circuits in the sub-threshold regime would seriously degrade the ratio of transistor driving current to leakage current and increase the sensitivity of process variations, thus increasing the possibility of logic functional failures. To increase the robustness of logic circuit in the sub-threshold regime, we propose a sub-threshold logic style
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孫信慶. "Migrating Java Threads with Fuzzy Control on Asymmetric Multicore Systems for Better Energy Delay Product." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/86440700052893639415.

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碩士<br>國立交通大學<br>資訊科學與工程研究所<br>99<br>Asymmetric multicore systems had been studied as a new hardware platform toward performance power efficiency for the execution of application programs. Each core in the system has distinct performance and power characteristics. When exploiting asymmetric multicore systems, a major issue is to distribute threads to various cores. In this work, we build a pseudo asymmetric system by dynamic voltage frequency scaling (DVFS) mechanism on Intel core i7 920 for physical power measurement and implement a tool agent for regular JVM to form an asymmetric-aware JVM th
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Park, Junyoung. "Self-tuning dynamic voltage scaling techniques for processor design." 2013. http://hdl.handle.net/2152/22989.

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The Dynamic Voltage Scaling (DVS) technique has proven to be ideal in regard to balancing performance and energy consumption of a processor since it allows for almost cubic reduction in dynamic power consumption with only a nearly linear reduction in performance. Due to its virtue, the DVS technique has been used for the two main purposes: energy-saving and temperature reduction. However, recently, a Dynamic Voltage Scaled (DVS) processor has lost its appeal as process technology advances due to the increasing Process, Voltage and Temperature (PVT) variations. In order to make a processor tol
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Book chapters on the topic "Energy Delay Product(EDP)"

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Laros III, James H., Kevin Pedretti, Suzanne M. Kelly, et al. "Energy Delay Product." In Energy-Efficient High Performance Computing. Springer London, 2012. http://dx.doi.org/10.1007/978-1-4471-4492-2_8.

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Ahmed, Jameel, Mohammed Yakoob Siyal, Shaheryar Najam, and Zohaib Najam. "Energy-Delay Product and Throughput." In Fuzzy Logic Based Power-Efficient Real-Time Multi-Core System. Springer Singapore, 2016. http://dx.doi.org/10.1007/978-981-10-3120-5_2.

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Mishra, Vishwas, and Shyam Akashe. "Calculation of Power Delay Product and Energy Delay Product in 4-Bit FinFET Based Priority Encoder." In Springer Proceedings in Physics. Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2367-2_36.

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Mittal Sparsh and Zhang Zhao. "Palette: A Cache Leakage Energy Saving Technique for Green Computing." In Advances in Parallel Computing. IOS Press, 2013. https://doi.org/10.3233/978-1-61499-324-7-46.

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With each CMOS technology generation, leakage energy has been increasing at an exponential rate. Since modern processors employ large last level caches (LLCs), their leakage energy consumption has become an important concern in modern chip design. To address this issue, several techniques have been proposed. However, most of these techniques require offline profiling and hence, cannot be used in real-life systems which run trillions of instructions of arbitrary applications. In this paper, we propose Palette, a technique for saving cache leakage energy using cache coloring. Palette uses a smal
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Gupta, Priya, Anu Gupta, and Abhijit Asati. "Detailed Analysis of Ultra Low Power Column Compression WALLACE and DADDA Multiplier in Sub-Threshold Regime." In Advances in Computational Intelligence and Robotics. IGI Global, 2016. http://dx.doi.org/10.4018/978-1-4666-9474-3.ch004.

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In this chapter, the design and comparative analysis is done in between the most well-known column compression multipliers by Wallace and Dadda in sub-threshold regime. In order to reduce the hardware which ultimately reduces area, power and overall power delay product, an energy efficient basic modules of the multipliers like AND gates, half adders, full adders and partial product generate units have been analyzed for sub-threshold operation. At the last stage ripple carry adder is used in both multipliers. The performance metrics considered for the analysis of the multipliers are: power, del
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Goz, David, Georgios Ieronymakis, Vassilis Papaefstathiou, et al. "Direct N-Body Application on Low-Power and Energy-Efficient Parallel Architectures." In Parallel Computing: Technology Trends. IOS Press, 2020. http://dx.doi.org/10.3233/apc200088.

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The aim of this work is to quantitatively evaluate the impact of computation on the energy consumption on ARM MPSoC platforms, exploiting CPUs, embedded GPUs and FPGAs. One of them possibly represents the future of High Performance Computing systems: a prototype of an Exascale supercomputer. Performance and energy measurements are made using a state-of-the-art direct N-body code from the astrophysical domain. We provide a comparison of the time-to-solution and energy delay product metrics, for different software configurations.We have shown that FPGA technologies can be used for application ke
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Sivasaravanababu, S., T. R. Dineshkumar, and G. Saravana Kumar. "Assertion Driven Modified Booth Encoding and Post Computation Model for Speed MAC Applications." In Recent Trends in Intensive Computing. IOS Press, 2021. http://dx.doi.org/10.3233/apc210289.

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The Multiply-Accumulate Unit (MAC) is the core computational block in many DSP and wireless application but comes with more complicated architectures. Moreover the MAC block also decides the energy consumption and the performance of the overall design; due to its lies in the maximal path delay critical propagation. Developing high performance and energy optimized MAC core is essential to optimized DSP core. In this work, a high speed and low power signed booth radix enabled MAC Unit is proposed with highly configurable assertion driven modified booth algorithm (AD-MBE). The proposed booth core
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Meghanathan, Natarajan. "Data Gathering Algorithms and Sink Mobility Models for Wireless Sensor Networks." In Advances in Wireless Technologies and Telecommunication. IGI Global, 2014. http://dx.doi.org/10.4018/978-1-4666-4715-2.ch008.

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In the first half of the chapter, the authors provide a comprehensive description of two broad categories of data gathering algorithms for wireless sensor networks: the classical energy-unaware algorithms and the modern energy-aware algorithms, as well as presented an exhaustive performance comparison of representative algorithms from both these categories. While the first half of the chapter focuses on static sink (that is located outside on the network boundary), the second half of the chapter explores the use of mobile sinks that gather data by stopping at the vicinity of the sensor nodes.
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Conference papers on the topic "Energy Delay Product(EDP)"

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Costa, Mariana, Sandro Marques, Thiarles Medeiros, et al. "PampaFreq: Otimizando o EDP de Aplicações Paralelas em Processadores AMD." In XXI Simpósio em Sistemas Computacionais de Alto Desempenho. Sociedade Brasileira de Computação, 2020. http://dx.doi.org/10.5753/wscad.2020.14057.

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O DVFS (Dynamic Voltage and Frequency Scaling) tem sido amplamente utilizado para melhorar o uso dos recursos computacionais quando aplicações paralelas estão sendo executadas. No entanto, as aplicações paralelas têm comportamentos distintos e se relacionam de diferentes maneiras com as políticas de modificação de frequência do DVFS. Neste sentido, é necessário utilizar métodos otimizados de DVFS para melhorar o custo-benefício entre desempenho e consumo de energia, representado pelo EDP (energy-delay product). Dito isso, através de uma extensa exploração de espaço e projeto de diferentes polít
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Pereira, Luan, Leonardo Castro, Matheus Serpa, et al. "Otimizando a correspondência de patches para o inpainting de imagens com diferentes interfaces de programação paralela." In XXI Simpósio em Sistemas Computacionais de Alto Desempenho. Sociedade Brasileira de Computação, 2020. http://dx.doi.org/10.5753/wscad.2020.14059.

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Diversos problemas da área de processamento de imagens demandam um alto esforço computacional, como, por exemplo, os métodos de inpainting baseados na replicação de patches. Estes métodos viabilizam a solução de problemas reais, como a reconstrução de regiões sem conteúdo em imagens. Portanto, eles podem se beneficiar da exploração do paralelismo no nível de threads (TLP) através de interfaces de programação paralela (IPPs). No entanto, como cada IPP possui diferentes características com respeito ao gerenciamento de threads, escolher a ideal para implementar uma aplicação é importante para obte
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Rigon, Pedro H. C., Brenda S. Schussler, Cristiano A. Künas, Arthur F. Lorenzon, Alexandre Carissimi, and Philippe O. A. Navaux. "Otimizando a Implementação Multi-GPU do Método Fletcher através da Paralelização Eficiente na Computação e Comunicação de Dados." In Escola Regional de Alto Desempenho da Região Sul. Sociedade Brasileira de Computação - SBC, 2024. http://dx.doi.org/10.5753/eradrs.2024.238666.

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Este estudo explora a otimização de um sistema Multi-GPU para a aplicação do Método de Fletcher na exploração geofísica visando aprimorar as aplicações que envolvem esse tipo de modelagem. Com a crescente disponibilidade de várias GPUs em servidores de alto desempenho, nosso foco é otimizar a implementação multi-GPU do Método Fletcher, possibilitando a computação e comunicação de dados de forma paralela. Essa abordagem não apenas assegura uma resolução eficiente da Equação Diferencial Parcial que modela a propagação de ondas sísmicas, mas também aprimora a eficiência global no processamento at
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Berned, Gustavo, and Arthur Lorenzon. "Uma Metodologia para Reduzir o Custo de Aprendizado para Técnicas de Otimização de Aplicações Paralelas." In Escola Regional de Alto Desempenho da Região Sul. Sociedade Brasileira de Computação - SBC, 2020. http://dx.doi.org/10.5753/eradrs.2020.10780.

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A exploração do paralelismo em nível de threads (TLP - Thread Level Parallelism) tem sido amplamente utilizada para melhorar o desempenho de aplicações de diferentes domínios. Entretanto, muitas aplicações não escalam conforme o número de threads aumenta, ou seja, executar uma aplicação utilizando o máximo de threads não trará, necessariamente, o melhor resultado para tempo, energia ou EDP(Energy Delay Product), devido a questões relacionadas à hardware e Software [Raasch and Reinhardt 2003],[Lorenzon and Filho 2019]. Portanto, é preciso utilizar metodologias que consigam buscar um número idea
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Razavi, Pedram, Isabelle Ferain, Samaresh Das, Ran Yu, Nima Dehdashti Akhavan, and Jean-Pierre Colinge. "Intrinsic gate delay and energy-delay product in junctionless nanowire transistors." In 2012 13th International Conference on Ultimate Integration on Silicon (ULIS). IEEE, 2012. http://dx.doi.org/10.1109/ulis.2012.6193373.

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Bolla, Raffaele, Roberto Bruschi, Franco Davoli, and Paolo Lago. "Optimizing the power-delay product in energy-aware packet forwarding engines." In 2013 24th Tyrrhenian International Workshop on Digital Communications - Green ICT (TIWDC). IEEE, 2013. http://dx.doi.org/10.1109/tiwdc.2013.6664195.

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O'Connor, I., A. Poittevin, S. Le Beux, et al. "Analysis of Energy-Delay-Product of a 3D Vertical Nanowire FET Technology." In 2021 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS). IEEE, 2021. http://dx.doi.org/10.1109/eurosoi-ulis53016.2021.9560180.

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Kang, Chang Woo, Soroush Abbaspour, and Massoud Pedram. "Buffer sizing for minimum energy-delay product by using an approximating polynomial." In the 13th ACM Great Lakes Symposium. ACM Press, 2003. http://dx.doi.org/10.1145/764808.764838.

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Mehran, Mahdiyeh, and Nasser Masoumi. "A tapered partitioning method for “delay energy product” optimization in global interconnects." In 2007 Joint 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) and the IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007). IEEE, 2007. http://dx.doi.org/10.1109/mwscas.2007.4488532.

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Consoli, Elio, Massimo Alioto, Gaetano Palumbo, and Jan Rabaey. "Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS." In 2012 IEEE International Solid- State Circuits Conference - (ISSCC). IEEE, 2012. http://dx.doi.org/10.1109/isscc.2012.6177100.

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Reports on the topic "Energy Delay Product(EDP)"

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Kalman, Joseph, and Maryam Haddad. Wastewater-derived Ammonia for a Green Transportation Fuel. Mineta Transportation Institute, 2022. http://dx.doi.org/10.31979/mti.2021.2041.

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The energy-water nexus (i.e., availability of potable water and clean energy) is among the most important problems currently facing society. Ammonia is a carbon-free fuel that has the potential to reduce the carbon footprint in combustion related vehicles. However, ammonia production processes typically have their own carbon footprint and do not necessarily come from sustainable sources. This research examines wastewater filtration processes to harvest ammonia for transportation processes. The research team studied mock wastewater solutions and was able to achieve ammonia concentrations above
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Kalman, Joseph, and Maryam Haddad. Wastewater-derived Ammonia for a Green Transportation Fuel. Mineta Transportation Institute, 2022. http://dx.doi.org/10.31979/mti.2022.2041.

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The energy-water nexus (i.e., availability of potable water and clean energy) is among the most important problems currently facing society. Ammonia is a carbon-free fuel that has the potential to reduce the carbon footprint in combustion related vehicles. However, ammonia production processes typically have their own carbon footprint and do not necessarily come from sustainable sources. This research examines wastewater filtration processes to harvest ammonia for transportation processes. The research team studied mock wastewater solutions and was able to achieve ammonia concentrations above
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