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Journal articles on the topic 'Energy Delay Product(EDP)'

Author: Grafiati

Published: 2 June 2025

Last updated: 31 July 2025

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1

Seok, Hyelin, Hyoju Seo, Jungwon Lee, and Yongtae Kim. "COREA: Delay- and Energy-Efficient Approximate Adder Using Effective Carry Speculation." Electronics 10, no. 18 (2021): 2234. http://dx.doi.org/10.3390/electronics10182234.

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This paper presents a delay- and energy-efficient approximate adder design exploiting an effective carry speculation scheme with error reduction. The proposed scheme reduces the delay and improves the energy efficiency without any significant accuracy degradation by effectively adding the predicted carry input using the OR operation. Additionally, the error reduction technique improves the overall computation accuracy at the expense of a few logic gates. As a result, the proposed adder achieves 3.84- and 7.79-times greater energy and energy-delay product (EDP) efficiencies than the traditional

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2

García, José C., Juan A. Montiel-Nelson, and Saeid Nooshabadi. "Versatile CMOS Current Conveyor for Digital VLSI Systems with Low-Voltage Power Supply." Journal of Low Power Electronics 15, no. 3 (2019): 323–28. http://dx.doi.org/10.1166/jolpe.2019.1617.

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A low voltage supply CMOS current conveyor circuit for digital input signals from 0.25 V up to 1.2 V is presented. The circuit is optimized and pre-layout simulated in a 65 nm CMOS process technology. At the target design voltage of 1.2 V, the current conveyor has a propagation delay of 2.86 ns, an energy consumption of only 80.9 pJ, and energy-delay product (EDP) of 231 pJns for resistive load of 10 kΩ. Superior performance of this work is demonstrated through comparison with other similar published work at a frequency of 5 MHz. It is shown that the proposed circuit is suitable for digital si

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Pérez, Santiago S., Alessandro Bedoya, Luis Miguel Prócel, and Ramiro Taco. "Exploiting TFET-based technology for energy-efficient STT-MRAM cells." International Journal of Applied Electromagnetics and Mechanics 73, no. 1 (2023): 15–24. https://doi.org/10.3233/jae-220300.

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Spin-transfer torque magnetic random-access memory (STT-MRAM) has been demonstrated to be a leading candidate for on-chip memory technology. In this work, double-barrier magnetic tunnel junction (DMTJ) is exploited to define STT-MRAMs at the circuit-level (i.e. at the bitcell level). The DMTJ-based bitcells are built from tunnel-FET technology and benchmarked against a calibrated 10 nm-FinFET technology model. STT-MRAM bitcells operate in the ultra-low voltage domain, and are evaluated in terms of energy-efficiency and area. Simulation results points out that the tunnel-FET based solution is t

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Shahrokhi, Seyed Hossein, Mehdi Hosseinzadeh, Midia Reshadi, and Saeid Gorgin. "A Novel High-Speed and Low-PDP Approximate Full Adder Cell for Image Blending." Mathematics 11, no. 12 (2023): 2649. http://dx.doi.org/10.3390/math11122649.

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This paper presents a new and high-performance inaccurate Full Adder Cell utilizing the Carbon Nanotube Field Effect Transistor (CNFET) technology. Comprehensive simulations are performed at the transistor and application levels to justify the performance of our design. Simulations performed using the HSPICE tool confirm the significant improvement in the performance of the proposed circuit delay, power-delay product (PDP) and energy-delay product (EDP) compared to competitor designs. Additionally, via a MATLAB tool, the image blending (alpha blending) application uses inaccurate Full Adder ce

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Nirlakalla, Ravi, Rao Subba, and Talari Jayachandra-Prasad. "Performance evaluation of high speed compressors for high speed multipliers." Serbian Journal of Electrical Engineering 8, no. 3 (2011): 293–306. http://dx.doi.org/10.2298/sjee1103293n.

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This paper describes high speed compressors for high speed parallel multipliers like Booth Multiplier, Wallace Tree Multiplier in Digital Signal Processing (DSP). This paper presents 4-3, 5-3, 6-3 and 7-3 compressors for high speed multiplication. These compressors reduce vertical critical path more rapidly than conventional compressors. A 5-3 conventional compressor can take four steps to reduce bits from 5 to 3, but the proposed 5-3 takes only 2 steps. These compressors are simulated with H-Spice at a temperature of 25?C at a supply voltage 2.0V using 90nm MOSIS technology. The Power, Delay,

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Chin, Huei Chaeng, Cheng Siong Lim, Weng Soon Wong, Kumeresan A. Danapalasingam, Vijay K. Arora, and Michael Loong Peng Tan. "Enhanced Device and Circuit-Level Performance Benchmarking of Graphene Nanoribbon Field-Effect Transistor against a Nano-MOSFET with Interconnects." Journal of Nanomaterials 2014 (2014): 1–14. http://dx.doi.org/10.1155/2014/879813.

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Comparative benchmarking of a graphene nanoribbon field-effect transistor (GNRFET) and a nanoscale metal-oxide-semiconductor field-effect transistor (nano-MOSFET) for applications in ultralarge-scale integration (ULSI) is reported. GNRFET is found to be distinctly superior in the circuit-level architecture. The remarkable transport properties of GNR propel it into an alternative technology to circumvent the limitations imposed by the silicon-based electronics. Budding GNRFET, using the circuit-level modeling software SPICE, exhibits enriched performance for digital logic gates in 16 nm process

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Abdul Tahrim, ‘Aqilah binti, Huei Chaeng Chin, Cheng Siong Lim, and Michael Loong Peng Tan. "Design and Performance Analysis of 1-Bit FinFET Full Adder Cells for Subthreshold Region at 16 nm Process Technology." Journal of Nanomaterials 2015 (2015): 1–13. http://dx.doi.org/10.1155/2015/726175.

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The scaling process of the conventional 2D-planar metal-oxide semiconductor field-effect transistor (MOSFET) is now approaching its limit as technology has reached below 20 nm process technology. A new nonplanar device architecture called FinFET was invented to overcome the problem by allowing transistors to be scaled down into sub-20 nm region. In this work, the FinFET structure is implemented in 1-bit full adder transistors to investigate its performance and energy efficiency in the subthreshold region for cell designs of Complementary MOS (CMOS), Complementary Pass-Transistor Logic (CPL), T

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8

Kim, Junha, and Moonju Park. "Dynamic Frequency Scaling Regarding Memory for Energy Efficiency of Embedded Systems." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 3 (2018): 1798. http://dx.doi.org/10.11591/ijece.v8i3.pp1798-1804.

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Memory significantly affects the power consumption of embedded systems as well as performance. CPU frequency scaling for power management could fail in optimizing the energy efficiency without considering the memory access. In this paper, we analyze the power consumption and energy efficiency of an embedded system that supports dynamic scaling of frequency for both CPU and memory access. The power consumption of the CPU and the memory is modeled to show that the memory access rate affects the energy efficiency and the CPU frequency selection. Based on the power model, a method for frequency se

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Cao, Peng, and Jingjing Guo. "Standard Cell Sizing for Worst-Case Performance Optimization Considering Process Variation in Subthreshold Region." Electronics 13, no. 22 (2024): 4477. http://dx.doi.org/10.3390/electronics13224477.

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Ultra-low-voltage design brings considerable outcomes in power reduction and energy efficiency improvement at the cost of performance degradation and uncertainty. Conventional standard cell design methodology cannot guarantee optimal performance for subthreshold operations due to the lack of consideration of process variation. In this paper, an effective subthreshold cell sizing method is proposed to minimize the worst-case propagation delay by deriving the optimal pMOS-to-nMOS width ratio (β) analytically, which reveals the relation between the minimal worst-case delay and the process paramet

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Abid, Z., Dalia A. El-Dib, and Rizwan Mudassir. "Modified Operand Decomposition Multiplication for High Performance Parallel Multipliers." Journal of Circuits, Systems and Computers 25, no. 12 (2016): 1650149. http://dx.doi.org/10.1142/s0218126616501498.

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A low power operand decomposition multiplication architecture implementation is modified to further reduce its power dissipation and delay. First, the multiplier’s implementation was modified to generate the partial products using NAND gates instead of AND and OR gates in order to reduce the number of transistors (area utilized) and to reduce the delay. Then, new types of adders and (4:2) compressors, that accept negatively weighted bits are used to reduce the number of inverters. Therefore, the resulting multiplier architecture reduces the number of transistors significantly. These modificati

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Ying, Yong Jie, and Zaharah Johari. "Simulation and Characterization of Carbon Nanotube-based 2:1 Multiplexer Electrical Properties." Journal of Physics: Conference Series 2622, no. 1 (2023): 012023. http://dx.doi.org/10.1088/1742-6596/2622/1/012023.

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Abstract This paper reports on using simulation to characterize a Carbon Nanotube (CNT) based 2:1 multiplexer (MUX). This study aimed to evaluate the electrical properties, particularly the propagation delay, average power consumption, Power-Delay Product (PDP), and Energy-Delay Product (EDP). Different design approaches namely conventional CMOS, Pass Transistor Logic (PTL) approach, and Gate Diffusion Input (GDI) were adopted. The voltage supply (VDD) and diameter of the CNT are varied to see the effect on the electrical properties. The simulation was carried out using HSPICE. Through simulat

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Bakshi, Suyash, and Lennart Johnsson. "Computationally Efficient DNN Mapping Search Heuristic using Deep Reinforcement Learning." ACM Transactions on Embedded Computing Systems 22, no. 5s (2023): 1–21. http://dx.doi.org/10.1145/3609110.

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In this work, we present a computationally efficient Reinforcement Learning mapping search heuristic for finding high quality mappings for N-dimensional convolution loops that uses a computationally inexpensive reward function based on potential data reuse of operands to guide the search process. We also present a RL state representation generalizable to N-dimensional convolution loops, and a state representation parsing strategy ensuring that only valid mappings are evaluated for quality. Our RL search heuristic is applicable to multi-core systems with a memory hierarchy. We show that our RL

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Bhargav, Avireni, and Phat Huynh. "Design and Analysis of Low-Power and High Speed Approximate Adders Using CNFETs." Sensors 21, no. 24 (2021): 8203. http://dx.doi.org/10.3390/s21248203.

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Adders are constituted as the fundamental blocks of arithmetic circuits and are considered important for computation devices. Approximate computing has become a popular and developing area, promising to provide energy-efficient circuits with low power and high performance. In this paper, 10T approximate adder (AA) and 13T approximate adder (AA) designs using carbon nanotube field-effect transistor (CNFET) technology are presented. The simulation for the proposed 10T approximate adder and 13T approximate adder designs were carried out using the HSPICE tool with 32 nm CNFET technology. The metri

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14

NAGARAJAN, SATHIYARAJ PANDIAN, THANDABANI KAVITHA, NAGARAJAN ASHOK KUMAR, and ALEXANDER SHIRLY EDWARD. "POWER ENERGY AND POWER AREA PRODUCT SIMULATION ANALYSIS OF MASTER-SLAVE FLIP-FLOP." REVUE ROUMAINE DES SCIENCES TECHNIQUES — SÉRIE ÉLECTROTECHNIQUE ET ÉNERGÉTIQUE 68, no. 4 (2023): 325–30. http://dx.doi.org/10.59277/rrst-ee.2023.4.19.

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Flip-flops are the fundamental building blocks of the data path structure. It is a key component of digital circuits and systems. This work offers an exclusive master-slave flip-flop topology by ensuing clocked complementary metal oxide semiconductor (C2MOS) logic, minimizing the total device count and the count of clocked devices. Reducing the number of clocked devices reduces undesirable transient activity and reduces dynamic power dissipation. C2MOS logic connects static logic design with clock signal synchronization, resulting in power savings and increased speed. The area reduction is als

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Nagarajan, P., N. Ashok Kumar, and P. Venkat Ramana. "Design of implicit pulsed-dual edge triggering flip flop for low power and high speed clocking systems." International Journal of Wavelets, Multiresolution and Information Processing 18, no. 01 (2019): 1941009. http://dx.doi.org/10.1142/s0219691319410091.

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The flip-flops are considered as major contributors to the power dissipation of the clocking system, which is made up of the clock provision network and storage elements (latches, flip-flops). The power- and delay-efficient new implicit-pulsed dual-edge triggering flip-flop circuit (IP-DETFF) is proposed with two latching stages by employing an implicit-pulse triggering, dual-edge clocking and reducing the number of clocked loads. This leads to the reduction of power consumption due to clock allocation tree (pclk-tree) and reduces the delay time. The dual-edge clocking technique is incorporate

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Mendez, Tanya, Subramanya G. Nayak, Vasanth Kumar P., Vijay S. R., and Vishnumurthy Kedlaya K. "Performance Metric Evaluation of Error-Tolerant Adders for 2D Image Blending." Electronics 11, no. 15 (2022): 2461. http://dx.doi.org/10.3390/electronics11152461.

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The hardware implementation of error-tolerant adders using the paradigm of approximate computing has considerably influenced the performance metrics, especially in applications that can compromise accuracy. The foundation for approximate processing is the inclusion of errors in the design to enhance the effectiveness and reduce the complexity. This work presents three base adders using the novel concept of error tolerance in digital VLSI design. The research is extended to construct nine variants of power and delay-efficient 16 and 32-bit error-tolerant carry select adders (CSLA). To attain op

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Singhal, Subodh Kumar, B. K. Mohanty, Sujit Kumar Patel, and Gaurav Saxena. "Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder." Journal of Circuits, Systems and Computers 29, no. 12 (2020): 2050186. http://dx.doi.org/10.1142/s0218126620501868.

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Parallel prefix adder (PPA) is the core component of diminished-1 modulo ([Formula: see text]) adder structure. In this paper, group-carry selection logic based PPA design is proposed and it is free from redundant logic operations which otherwise present in the existing PPA design based on group sum selection logic. Further, the logic expression of pre-processing unit of PPA is also presented in a simplified form to save some logic resources. The proposed PPA design for bit-width 32-bit involves 26.1% less area, consumes 28.4% less power and marginally higher critical-path delay than the exist

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Goksoy, A. Alper, Sahil Hassan, Anish Krishnakumar, Radu Marculescu, Ali Akoglu, and Umit Y. Ogras. "Theoretical Validation and Hardware Implementation of Dynamic Adaptive Scheduling for Heterogeneous Systems on Chip." Journal of Low Power Electronics and Applications 13, no. 4 (2023): 56. http://dx.doi.org/10.3390/jlpea13040056.

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Domain-specific systems on chip (DSSoCs) aim to narrow the gap between general-purpose processors and application-specific designs. CPU clusters enable programmability, whereas hardware accelerators tailored to the target domain minimize task execution times and power consumption. Traditional operating system (OS) schedulers can diminish the potential of DSSoCs, as their execution times can be orders of magnitude larger than the task execution time. To address this problem, we propose a dynamic adaptive scheduling (DAS) framework that combines the advantages of a fast, low-overhead scheduler a

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Wairya, Subodh, Rajendra Kumar Nagaria, and Sudarshan Tiwari. "Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design." VLSI Design 2012 (April 4, 2012): 1–18. http://dx.doi.org/10.1155/2012/173079.

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This paper presents a comparative study of high-speed and low-voltage full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit. A high performance adder cell using an XOR-XNOR (3T) design style is discussed. This paper also discusses a high-speed conventional full adder design combined with MOSCAP Majority function circuit in one unit to implement a hybrid full adder circuit. Moreover, it presents low-power Majority-function-based 1-bit full addersthat use MOS capacitors (MOSCAP) in its structure. This technique helps in reducing power consumpti

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Spagnolo, Fanny, Pasquale Corsonello, Fabio Frustaci, and Stefania Perri. "Efficient Addition Circuits Using Three-Gate Reconfigurable Field Effect Transistors." Journal of Low Power Electronics and Applications 14, no. 2 (2024): 24. http://dx.doi.org/10.3390/jlpea14020024.

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Reconfigurable FETs (RFETs) are widely recognized as a promising way to overcome conventional CMOS architectures. This paper presents novel addition circuit intentionally designed to exploit the ability of RFETs to operate efficiently on demand as n- or p-type FETs. First, a novel Full Adder (FA) is proposed and characterized. A comparison with other designs shows that the proposed FA achieves a worst-case delay and a dynamic power consumption of up to 43.5% and 79% lower. As a drawback, in terms of the estimated area, it is up to 32% larger than the competitors. Then, the new FA is used to im

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Bylina, Beata, and Monika Piekarz. "Time–Energy Correlation for Multithreaded Matrix Factorizations." Energies 16, no. 17 (2023): 6290. http://dx.doi.org/10.3390/en16176290.

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The relationship between time and energy is an important aspect related to energy savings in modern multicore architectures. In this paper, we investigated and analyzed the correlation between time and energy. We compared the execution time and energy consumption of the LU factorization algorithms (versions with and without pivoting) and Cholesky with the Math Kernel Library (MKL) on a multicore machine. To reduce the energy of these multithreaded factorizations, the Dynamic Voltage and Frequency Scaling (DVFS) technique was used. This technique allows the clock frequency to be scaled without

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Mohapatra, Sushanta, Kumar Pradhan, and Prasanna Sahu. "ZTC bias point of advanced fin based device: The importance and exploration." Facta universitatis - series: Electronics and Energetics 28, no. 3 (2015): 393–405. http://dx.doi.org/10.2298/fuee1503393m.

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The present understanding of this work is about to evaluate and resolve the temperature compensation point (TCP) or zero temperature coefficient (ZTC) point for a sub-20 nm FinFET. The sensitivity of geometry parameters on assorted performances of Fin based device and its reliability over ample range of temperatures i.e. 25?C to 225?C is reviewed to extend the benchmark of device scalability. The impact of fin height (HFin), fin width (WFin), and temperature (T) on immense performance metrics including on-off ratio (Ion/Ioff), transconductance (gm), gain (AV), cut-off frequency (fT), static po

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Haq, Shams Ul, Maedeh Orouji, Tabassum Khurshid, and Erfan Abbasian. "An efficient design methodology for a tri-state multiplier circuit in carbon nanotube technology." Physica Scripta 100, no. 1 (2024): 015008. https://doi.org/10.1088/1402-4896/ad9646.

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Abstract This study delves into the computational aspects of ternary logic and the use of carbon nanotube field-effect transistors (CNTFETs) to develop an energy-efficient and robust ternary multiplier (TMUL). Leveraging the exceptional qualities of CNTFETs, such as balanced electron and hole mobility and easy modulation of threshold voltage, the research aims to achieve the desired designs. An innovative design method is employed, recommending a reduced count of logic gates for achieving necessary logic levels. These gates are then utilized to manage the activation and deactivation of the pri

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Amruta, S.Thorat* R. S. Khule Dr. S. D.Pable. "DESIGN OF HIGH SPEED SUBTHRESHOLD INTERCONNECTS USING MCML TECHNIQUE." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 5, no. 8 (2016): 729–36. https://doi.org/10.5281/zenodo.60123.

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The recent trend in the VLSI industry toward miniature designs, low power consumption, and increased growth of portable applications compels researchers to design circuit having high speed. This is achieved by operating circuits under subthreshold condition and by designing interconnects using various techniques. This paper presents designing of Subthreshold interconnects using MCML technique which exhibits a decrease in delay in terms of designing of interconnects under subthreshold region as compared to CMOS techniques. Circuit is implemented in 32nm MOS technology using HSPICE. The results

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M.Siva, Kumar, V.Pravallika, B.Rojitha, P.Mahendra, and A.Srujana. "Novel Approach to Suppress Crosstalk in Through-Silicon Vias." Research and Review: VLSI Design, Tools and It's Application 1, no. 1 (2025): 17–26. https://doi.org/10.5281/zenodo.15129838.

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<em>This research presents a novel technique for reducing crosstalk in ternary coupled through-silicon vias (TSVs). The study evaluates crosstalk effects in TSVs that utilize metallic liners made of multi-walled carbon nanotubes (MWCNTs) alongside dielectric liners composed of polymers such as polyimide, polypropylene carbonate (PPC), and benzo cyclobutene (BCB). To investigate various crosstalk challenges, a circuit model of coupled TSVs driven by a ternary inverter is developed. The proposed TSV designs are analyzed using the HSPICE simulation tool. A comparative study is conducted to assess

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Shaik, Sadulla, K. Sri Rama Krishna, and Ramesh Vaddi. "Tunnel Transistor-Based Reliable and Energy Efficient Computing Architectures with Circuit and Architectural Co-Design at Low VDD." Journal of Circuits, Systems and Computers 27, no. 03 (2017): 1850046. http://dx.doi.org/10.1142/s0218126618500469.

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Tunnel field-effect transistors (TFETs) as low voltage device options have attracted recent attention for energy efficient circuit designs with CMOS technology scaling. This paper presents the circuit and architectural co-design approach for designing reliable and energy efficient architectures (adder cells) for new computing platforms at supply voltages. At circuit level TFET-based 28-transistor static logic design (28T) and 24-transistor transmission gate logic design (24T) have been explored. At architectural level, multiplexer (MUX)-based 22-transistor full adder design (22T) is proposed.

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Jaber, Ramzi A., Ali M. Haidar, Abdallah Kassem, and Furqan Zahoor. "Ternary Full Adder Designs Employing Unary Operators and Ternary Multiplexers." Micromachines 14, no. 5 (2023): 1064. http://dx.doi.org/10.3390/mi14051064.

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The design of the Ternary Full Adders (TFA) employing Carbon Nanotube Field-Effect Transistors (CNFET) has been widely presented in the literature. To obtain the optimal design of these ternary adders, we propose two new different designs, TFA1 with 59 CNFETs and TFA2 with 55 CNFETs, that use unary operator gates with two voltage supplies (Vdd and Vdd/2) to reduce the transistor count and energy consumption. In addition, this paper proposes two 4-trit Ripple Carry Adders (RCA) based on the two proposed TFA1 and TFA2; we use the HSPICE simulator and 32 nm CNFET to simulate the proposed circuits

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Paul, Somnath, Subho Chatterjee, Saibal Mukhopadhyay, and Swarup Bhunia. "Energy-Efficient Reconfigurable Computing Using a Circuit-Architecture-Software Co-Design Approach." IEEE Journal on Emerging and Selected Topics in Circuits and Systems 1, no. 3 (2011): 369–80. http://dx.doi.org/10.1109/jetcas.2011.2165232.

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Reconfigurable computing frameworks such as field programmable gate array (FPGA) provide flexibility to map arbitrary applications. However, their intrinsic flexibility comes at the cost of significantly worse performance and power dissipation than their custom counterparts. Existing design solutions such as voltage scaling and multi-threshold assignment typically trade off energy for performance or vise versa. In this paper, we show that an integrated circuit-architecture-software co-design approach can be extremely effective to simultaneously improve the power and performance of a reconfigur

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Abbasian, Erfan, and Maryam Nayeri. "Simulation-Based Recommendations for Digital Circuits Design Using Schottky-Barrier-Type GNRFET." ECS Journal of Solid State Science and Technology 11, no. 7 (2022): 071001. http://dx.doi.org/10.1149/2162-8777/ac7c39.

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The use of graphene nano-ribbon field-effect transistors (GNRFETs) in the nanoscale circuits design is challenging because there are several adjustable parameters that need to be selected carefully. In this paper, we evaluate the impact of changes in different GNRFETs’ parameters including channel length (Lch), oxide thickness (Tox), line-edge roughness (Pr), number of dimer lines (N), supply voltage, and temperature on the performance of inverter, Flip-Flop, and SRAM circuits. Performance analysis in terms of noise margin (NM), delay, average power, and energy-delay-product (EDP) show that th

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Chu, Yul, and Marven Calagos. "A Buffered Dual-Access-Mode Scheme Designed for Low-Power Highly-Associative Caches." International Journal of Embedded and Real-Time Communication Systems 4, no. 2 (2013): 50–61. http://dx.doi.org/10.4018/jertcs.2013040103.

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This paper proposes a buffered dual-access-mode cache to reduce power consumption for highly-associative caches in modern embedded systems. The proposed scheme consists of a MRU (most recently used) buffer table and a single cache structure to implement two accessing modes, phased mode and way-prediction mode. The proposed scheme shows better access time and lower power consumption than two popular low-power caches, phased cache and way-prediction cache. The authors used Cacti and SimpleScalar simulators to evaluate the proposed cache scheme by using SPEC benchmark programs. The experimental r

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Shaik, Javid Basha, and P. Venkatramana. "Investigation of Crosstalk Issues for MWCNT Bundled TSVs in Ternary Logic." ECS Journal of Solid State Science and Technology 11, no. 3 (2022): 031002. http://dx.doi.org/10.1149/2162-8777/ac5c85.

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The investigation of crosstalk issues for coupled through silicon vias (TSVs) in ternary logic is presented in this study. The crosstalk issues are analyzed for coupled TSVs utilizing multi-walled carbon nanotube (MWCNT) as conductive filler, and polymer liners such as polyimide, polypropylene carbonate (PPC), benzocyclobutene (BCB) as insulating materials. For the coupled TSVs, the electrical equivalent circuit model is used to investigate the crosstalk which is driven by the ternary inverter. Based on the Hewlett simulation program with integrated circuit emphasis (HSPICE) simulations, the e

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WANG, XINSHENG, YIZHE HU, LIANG HAN, JINGHU LI, CHENXU WANG, and MINGYAN YU. "A LOW POWER AND VARIATION-INSENSITIVE CURRENT-MODE SIGNALING SCHEME." Journal of Circuits, Systems and Computers 22, no. 08 (2013): 1350068. http://dx.doi.org/10.1142/s0218126613500680.

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Process and supply variations all have a large influence on current-mode signaling (CMS) circuits, limiting their application on the fields of high-speed low power communication over long on-chip interconnects. A variation-insensitive CMS scheme (CMS-Bias) was offered, employing a particular bias circuit to compensate the effects of variations, and was robust enough against inter-die and intra-die variations. In this paper, we studied in detail the principle of variation tolerance of the CMS circuit and proposed a more suitable bias circuit for it. The CMS-Bias with the proposed bias circuit (

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Sabu, Neethu Anna, and K. Batri. "Design and Analysis of Power Efficient TG Based Dual Edge Triggered Flip-Flops with Stacking Technique." Journal of Circuits, Systems and Computers 29, no. 08 (2019): 2050123. http://dx.doi.org/10.1142/s0218126620501236.

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One of the paramount issues in the field of VLSI design is the rapid increase in power consumption. Therefore, it is necessary to develop power-efficient circuits. Here, three new simple architectures are presented for a Dynamic Double Edge Triggered Flip-flop named as Transistor Count Reduction Flip-flop, S-TCRFF (Series Stacking in TCRFF) and FST in TCRFF (Forced Stacking of Transistor in TCRFF). The first one features a dynamic design comprising of transmission gate in which total transistor count has greatly reduced without affecting the logic, thereby attaining better power and speed perf

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Cuenca, Juan, Benjamin Zambrano, Esteban Garzón, Luis Miguel Prócel, and Marco Lanuzza. "An Accurate and Low-Complexity Offset Calibration Methodology for Dynamic Comparators." Journal of Low Power Electronics and Applications 15, no. 2 (2025): 35. https://doi.org/10.3390/jlpea15020035.

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Dynamic comparators play an important role in electronic systems, requiring high accuracy, low power consumption, and minimal offset voltage. This work proposes an accurate and low-complexity offset calibration design based on a capacitive load approach. It was designed using a 65 nm CMOS technology and comprehensively evaluated under Monte Carlo simulations and PVT variations. The proposed scheme was built using MIM capacitors and transistor-based capacitors, and it includes Verilog-based calibration algorithms. The proposed offset calibration is benchmarked, in terms of precision, calibratio

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Chen, Huamin, Ruijie Fang, Tao Chen, et al. "A Novel Adaptive UE Aggregation-Based Transmission Scheme Design for a Hybrid Network with Multi-Connectivity." Symmetry 15, no. 9 (2023): 1766. http://dx.doi.org/10.3390/sym15091766.

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With the progress of the eras and the development of science and technology, the requirements of device-to-device (D2D) connectivity increased rapidly. As one important service in future systems, ultra-reliable low-latency communication (URLLC) has attracted attention in many applications, especially in the Internet of Things (IoT), smart cities, and other scenarios due to its characteristics of ultra-low latency and ultra-high reliability. However, in order to achieve the requirement of ultra-low latency, energy consumption often increases significantly. The optimization of energy consumption

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Surendra, G., Subhasis Banerjee, and S. K. Nandy. "Instruction Reuse in SPEC, media and packet processing benchmarks: A comparative study of power, performance and related microarchitectural optimizations." Journal of Embedded Computing 2, no. 1 (2006): 15–34. https://doi.org/10.3233/emc-2006-00057.

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The effectiveness of Instruction Reuse (IR) – a technique to eliminate redundant computations at run time – is limited by the fact that performance gain seldom exceeds 3% and is dependent on the criticality of instructions being “reused”. In this paper, we focus on the power aspect of IR and propose a “resultbus optimization” that exploits communication reuse to reduce the power dissipated over a high capacitance resultbus. The effectiveness of this optimization depends on the number of result producing instructions that are reused and improves overall power and Energy-Delay Product (EDP) by 3

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Paul, Indrani, Vignesh Ravi, Srilatha Manne, Manish Arora, and Sudhakar Yalamanchili. "Coordinated Energy Management in Heterogeneous Processors." Scientific Programming 22, no. 2 (2014): 93–108. http://dx.doi.org/10.1155/2014/210762.

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This paper examines energy management in a heterogeneous processor consisting of an integrated CPU–GPU for high-performance computing (HPC) applications. Energy management for HPC applications is challenged by their uncompromising performance requirements and complicated by the need for coordinating energy management across distinct core types – a new and less understood problem. We examine the intra-node CPU–GPU frequency sensitivity of HPC applications on tightly coupled CPU–GPU architectures as the first step in understanding power and performance optimization for a heterogeneous multi-node

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R., Manjunath. "LOW POWER OPTIMIZATION OF FULL ADDER CIRCUIT BASED ON GDI LOGIC FOR BIOMEDICAL APPLICATIONS." International Journal of Advanced Research 10, no. 10 (2022): 457–67. http://dx.doi.org/10.21474/ijar01/15511.

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Advanced Electronic Devices have recently become more prevalent, designers have opted for low power, quick speed, and compact designs and processes. Even though there are numerous design methodologies currently in use for VLSI system design optimization, very few design techniques produce solutions that are optimally optimal. GDI-based circuits are becoming increasingly important since they use less space, power, and energy. The GDI technique ensures minimal propagation delay, power, and area in low-power design strategies. For 45nm technology, the Cadence Virtuoso EDA tool is utilised to dete

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Sabu, Neethu Anna, and Batri K. "Power and area-efficient register designs involving EHO algorithm." Circuit World 46, no. 2 (2020): 93–105. http://dx.doi.org/10.1108/cw-07-2019-0077.

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Purpose This paper aims to design three low-power and area-efficient serial input parallel output (SIPO) register designs, namely, transistor count reduction technique shift register (TCRSR), series stacking in TCR shift register (S-TCRSR) and forced stacking of transistor in TCR shift register (FST in TCRSR). Shift registers (SR) are the basic building blocks of all types of digital applications. The performance of all the designs has been improved through one of the metaheuristic algorithms named elephant herding optimization (EHO) algorithm and hence suited for low-power very large scale in

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Upadhyay, Rahul Mani, R. K. Chauhan, and Manish Kumar. "Performance Evaluation of Efficient Low Power 1-bit Hybrid Full Adder." ADCAIJ: Advances in Distributed Computing and Artificial Intelligence Journal 11, no. 4 (2023): 475–88. http://dx.doi.org/10.14201/adcaij.28558.

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The need for a low power system on a chip for embedded systems has increased enormously for human to machine interaction. The primary constraint of such embedded system is to consume less power and improve the battery performance of the device. We propose energy efficient, low power hybrid 1-bit full adder circuit in this paper, which may be integrated on chip to improve the overall performance of embedded systems. The proposed 1-bit hybrid full adder circuit designed at 130 nm technology was simulated using Mentor Graphics EDA tool. Further, a comparison is made with the previously proposed f

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Hatefinasab, Seyedehsomayeh. "Carbon Nanotube Field Effect Transistor-Based Hybrid Full Adders Using Gate-Diffusion Input Structure." Journal of Nanoelectronics and Optoelectronics 14, no. 11 (2019): 1512–22. http://dx.doi.org/10.1166/jno.2019.2661.

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Scaling down the size of transistor in the nanoscale reduces the power supply voltage, as a result, the design of high-performance nano-circuit at low voltage has been considered. Most of digital circuits are composed of different components which determine the performance of the entire digital circuits. With the improvement of these components, the digital circuits can be optimized. One of these components is full adder for which various structures have been proposed to improve its performance, among them the two novel full adder structures are based on Gate-Diffusion Input (GDI) structure an

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Yoo, Changhyun, Jeesoo Chang, Sugil Park, Hyungyeong Kim, and Jongwook Jeon. "Optimization of Gate-All-Around Device to Achieve High Performance and Low Power with Low Substrate Leakage." Nanomaterials 12, no. 4 (2022): 591. http://dx.doi.org/10.3390/nano12040591.

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In this study on multi-nanosheet field-effect transistor (mNS-FET)—one of the gate-all-around FETs (GAAFET) in the 3 nm technology node dimension—3D TCAD (technology computer-aided design) was used to attain optimally reduced substrate leakage from options including a punch-through-stopper (PTS) doping scheme and a bottom oxide (BO) scheme for bottom isolation, with the performance improvement being shown in the circuit-level dynamic operation using the mNS-FET. The PTS doping concentration requires a high value of >5 × 1018 cm−3 to reduce gate induced drain leakage (GIDL), regardless of th

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Singh, Shiwani, Tripti Sharma, K. G. Sharma, and B. P. Singh. "9T Full Adder Design in Subthreshold Region." VLSI Design 2012 (March 11, 2012): 1–5. http://dx.doi.org/10.1155/2012/248347.

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This paper presents prelayout simulations of two existing 9T and new proposed 9T full adder circuit in subthreshold region to employ in ultralow-power applications. The proposed circuit consists of a new logic which is used to implement Sum module. The proposed design remarkably reduces power-delay product (PDP) and improves temperature sustainability when compared with existing 9T adders. Therefore, in a nut shell proposed adder cell outperforms the existing adders in subthreshold region and proves to be a viable option for ultralow-power and energy-efficient applications. All simulations are

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Qadri, Muhammad Yasir, Nadia N. Qadri, Martin Fleury, and Klaus D. McDonald-Maier. "Software-Controlled Instruction Prefetch Buffering for Low-End Processors." Journal of Circuits, Systems and Computers 24, no. 10 (2015): 1550161. http://dx.doi.org/10.1142/s0218126615501613.

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This paper proposes a method of buffering instructions by software-based prefetching. The method allows low-end processors to improve their instruction throughput with a minimum of additional logic and power consumption. Low-end embedded processors do not employ caches for mainly two reasons. The first reason is that the overhead of cache implementation in terms of energy and area is considerable. The second reason is that, because a cache's performance primarily depends on the number of hits, an increasing number of misses could cause a processor to remain in stall mode for a longer duration.

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Siya Salim, Abdul, Dhakshayani V.R., Rahna A, Sruthika S, Dr V. Balamurugan, and Dr Aneesh K. "DESIGNING LOW POWER DOUBLE TAILED COMPARATOR FOR ECG." International Journal of Engineering Applied Sciences and Technology 09, no. 05 (2024): 168–74. http://dx.doi.org/10.33564/ijeast.2024.v09i05.022.

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While designing ECG systems, one of the chief issues is power consumption, most especially for mobile and wearable devices. This paper proposes the DTLC suitable for both low-end and high-end applications employing double-tailed comparators with negative body biasing to improve power throughout in ECG signal monitoring systems modeled using the Mentor Graphics. Integrated circuit designs with EDA tools using 180nm CMOS technology at a power supply of 0.8V improve power consumption without a decline in the car’s performance. Parameters including power consumption and power-delay product (PDP) a

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Et.al, A. Murali. "FPGA Implementation of Proficient 16-Tap FIR Filter Design Using Decision Tree Algorithm." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (2021): 3064–75. http://dx.doi.org/10.17762/turcomat.v12i3.1342.

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Lately, channel is one of the key components in signal handling applications. Among different channels, Finite Impulse Response (FIR) channel is broadly utilized in Digital Signal Processing (DSP) applications for shifting/denoising. For enormous scope coordination (VLSI) execution of fixed-coefficient FIR channels, huge asset used customary multipliers that can be acknowledged by a solitary steady multiplication (SCM) and numerous consistent augmentations (MCM) square utilizing movement and include/take away tasks. For a proficient execution, a variable size apportioning approach is proposed

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K Hari Kishore, A. Murali,. "FPGA Implementation of Proficient 16-Tap FIR Filter Design Using Decision Tree Algorithm." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 5 (2021): 170–80. http://dx.doi.org/10.17762/turcomat.v12i5.809.

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Lately, channel is one of the key components in signal handling applications. Among different channels, Finite Impulse Response (FIR) channel is broadly utilized in Digital Signal Processing (DSP) applications for shifting/denoising. For enormous scope coordination (VLSI) execution of fixed-coefficient FIR channels, huge asset used customary multipliers that can be acknowledged by a solitary steady multiplication (SCM) and numerous consistent augmentations (MCM) square utilizing movement and include/take away tasks. For a proficient execution, a variable size apportioning approach is proposed

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Yugendra Chary, T., S. Anitha, M. Alamillo, and Ameet Chavan. "Level Converters for Ultra Low Power IoT Applications." International Journal of Engineering & Technology 7, no. 2.16 (2018): 19. http://dx.doi.org/10.14419/ijet.v7i2.16.11409.

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For efficient ultra-low power IoT applications, working with various communication devices and sensors which operating voltages from subthreshold to superthreshold levels which requires wide variety of robust level converters for signal interfacing with low power dissipation. This paper proposes two topologies of level converter circuits that offer dramatic improvement in power and performance when compared to the existing level converters that shift signals from sub to super threshold levels for IoT applications. At 250 mV, the first proposed circuit - a modification of a tradition al current

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Rahman, Rahnuma, and Supriyo Bandyopadhyay. "The Cost of Energy-Efficiency in Digital Hardware: The Trade-Off between Energy Dissipation, Energy–Delay Product and Reliability in Electronic, Magnetic and Optical Binary Switches." Applied Sciences 11, no. 12 (2021): 5590. http://dx.doi.org/10.3390/app11125590.

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Binary switches, which are the primitive units of all digital computing and information processing hardware, are usually benchmarked on the basis of their ‘energy–delay product’, which is the product of the energy dissipated in completing the switching action and the time it takes to complete that action. The lower the energy–delay product, the better the switch (supposedly). This approach ignores the fact that lower energy dissipation and faster switching usually come at the cost of poorer reliability (i.e., a higher switching error rate) and hence the energy–delay product alone cannot be a g

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Upadhyay, Rahul Mani. "High Performance Energy-Efficient Leakage-Tolerant Dual Keeper Pseudo Domino Logic." International Journal on Applied Physics and Engineering 2 (May 31, 2023): 35–43. http://dx.doi.org/10.37394/232030.2023.2.6.

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In this paper, an improved high performance energy-efficient leakage-tolerant dual keeper pseudo domino logic circuit is proposed. Circuit design methodologies such as pseudo domino, stacking effect and inverted clock-controlled dual keeper are used in the proposed work for significant reduction of the circuit’s propagation delay and leakage current. Using pseudo-domino logic voltage swing at the output is reduced, stacking effect reduces the leakage current and charge sharing issues in the circuit are reduced by an inverted clock-controlled dual keeper circuit. Leakage current in the proposed

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