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Journal articles on the topic 'FD-SOI (transistors)'

Author: Grafiati

Published: 25 May 2024

Last updated: 31 July 2025

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1

Angelov, George V., Dimitar N. Nikolov, and Marin H. Hristov. "Technology and Modeling of Nonclassical Transistor Devices." Journal of Electrical and Computer Engineering 2019 (November 3, 2019): 1–18. http://dx.doi.org/10.1155/2019/4792461.

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This paper presents a comprehensive outlook for the current technology status and the prospective upcoming advancements. VLSI scaling trends and technology advancements in the context of sub-10-nm technologies are reviewed as well as the associated device modeling approaches and compact models of transistor structures are considered. As technology goes into the nanometer regime, semiconductor devices are confronting numerous short-channel effects. Bulk CMOS technology is developing and innovating to overcome these constraints by introduction of (i) new technologies and new materials and (ii) n

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Lagaev, Dmitriy A., Aleksey S. Klyuchnikov, and Nikolay A. Shelepin. "Prospects for applying FD-SOI technology to space applications." Journal of Physics: Conference Series 2388, no. 1 (2022): 012135. http://dx.doi.org/10.1088/1742-6596/2388/1/012135.

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Abstract In this work, using numerical simulation, the reasons for the occurrence of increased values of leakage currents in NMOS fully depleted SOI (FD-SOI) transistors during interaction with ionizing radiation. It has shown that the main reason for the formation of leakage currents is the charge accumulated in the latent oxide upon interaction with ionizing radiation. The effectiveness of applying a bias on the substrate and the formation of a well under the buried oxide (BOX) to reduce the leakage currents is investigated. Based on the obtained results, it was concluded that it is promisin

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3

Taher Abuelma’atti, Muhammad. "Harmonic and intermodulation distortion in SOI FD transistors." Solid-State Electronics 47, no. 5 (2003): 797–800. http://dx.doi.org/10.1016/s0038-1101(02)00453-7.

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Assalti, Rafael, Denis Flandre, and Michelly De Souza. "Influence of Geometrical Parameters on the DC Analog Behavior of the Asymmetric Self-Cascode FD SOI nMOSFETs." Journal of Integrated Circuits and Systems 13, no. 2 (2018): 1–7. http://dx.doi.org/10.29292/jics.v13i2.15.

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This paper assesses the DC analog performance of a composite transistor named Asymmetric Self-Cascode structure, which is formed by two Fully Depleted SOI nMOSFETs connected in series with shortened gates. The influence of geometrical parameters, such as different channel widths and lengths on the transistors at source and drain sides is evaluated through three-dimensional numerical simulations, which have been firstly adjusted to the experimental measurements. The transconductance, output conductance, Early voltage and intrinsic voltage gain have been used as figure of merit to explore the ad

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Schmidt, Alexander, Holger Kappert, and Rainer Kokozinski. "Enhanced High Temperature Performance of PD-SOI MOSFETs in Analog Circuits Using Reverse Body Biasing." Journal of Microelectronics and Electronic Packaging 10, no. 4 (2013): 171–82. http://dx.doi.org/10.4071/imaps.389.

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Analog circuits realized in a PD-SOI (partially-depleted silicon-on-insulator) CMOS technology for a wide temperature range up to 400°C are significantly affected by the transistor characteristics at high temperatures. As leakage currents increase with temperature, the analog device performance, for example, intrinsic gain and bandwidth, tend to decrease. Both effects influence the precision of analog circuits and lead to malfunction of the circuitry at high temperatures. Enhancement of the MOSFET device performance and improved design techniques are required to handle these issues. In this pa

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Mota Barbosa da Silva, Lucas, Bruna Cardoso Paz, and Michelly De Souza. "Analysis of Mobility in Graded-Channel SOI Transistors Aiming at Circuit Simulation." Journal of Integrated Circuits and Systems 15, no. 2 (2020): 1–5. http://dx.doi.org/10.29292/jics.v15i2.188.

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This work presents an analysis of the behavior of the effective mobility of graded-channel FD SOI transistors using an Y-Function-based technique. Low field mobility, linear and quadratic attenuation factors were extracted from two-dimensional numerical simulations. The influence of the length of both channel regions over these parameters was analyzed. The parameters extracted from experimental data were used in a SPICE simulator, showing that it is possible to simulated GC SOI MOSFET using a regular SOI MOSFET model, by adjusting its parameters.

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Schmidt, Alexander, Holger Kappert, and Rainer Kokozinski. "Enhanced High Temperature Performance of PD-SOI MOSFETs in Analog Circuits Using Reverse Body Biasing." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, HITEN (2013): 000122–33. http://dx.doi.org/10.4071/hiten-ta14.

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Analog circuit realized in a PD-SOI (Partially-Depleted Silicon-on-Insulator) CMOS process for a wide temperature range up to 400 °C are significantly affected by the MOSFET device characteristics at high temperatures. As leakage currents increase with temperature, the analog device performance, e.g. intrinsic gain and bandwidth tend to decrease. Both effects influence the precision of analog circuits and lead to malfunction of the circuitry at high temperatures. Enhancement of the MOSFET device performance and improved design techniques are required to handle these issues. In this paper, we d

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Cerdeira, A., M. Estrada, R. Quintero, D. Flandre, A. Ortiz-Conde, and F. J. Garcı́a Sánchez. "New method for determination of harmonic distortion in SOI FD transistors." Solid-State Electronics 46, no. 1 (2002): 103–8. http://dx.doi.org/10.1016/s0038-1101(01)00258-1.

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9

Gaillardin, Marc, Philippe Paillet, Veronique Ferlet-Cavrois, et al. "Transient Radiation Response of Single- and Multiple-Gate FD SOI Transistors." IEEE Transactions on Nuclear Science 54, no. 6 (2007): 2355–62. http://dx.doi.org/10.1109/tns.2007.910860.

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10

Lee, Noriyuki, Ryuta Tsuchiya, Yusuke Kanno, et al. "16 x 8 quantum dot array operation at cryogenic temperatures." Japanese Journal of Applied Physics 61, SC (2022): SC1040. http://dx.doi.org/10.35848/1347-4065/ac4c07.

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Abstract We developed a 16 x 8 quantum dot array and CMOS circuit hybrid chip (Q-CMOS). By optimizing the transistor design of Q-CMOS formed by fully depleted (FD)-SOI, it is possible to selectively control each of 16 x 8 quantum dots, and obtained characteristics of quantum dot variation for the first time. Due to the mesoscopic effect, the variation in the characteristics of the quantum dots is larger than the threshold voltage variation of the transistors. Thus, we have obtained an important finding that it is necessary to suppress the variability in order to realize a large-scale quantum c

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11

Vasileska, D., K. Raleva, A. Hossain, and S. M. Goodnick. "Current progress in modeling self-heating effects in FD SOI devices and nanowire transistors." Journal of Computational Electronics 11, no. 3 (2012): 238–48. http://dx.doi.org/10.1007/s10825-012-0404-0.

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12

Hartmann, Jean-Michel, Francois Aussenac, Olivier Glorieux, et al. "Advanced SiGe:B Raised Sources and Drains for p-type FD-SOI MOSFETs." ECS Transactions 114, no. 2 (2024): 185–205. http://dx.doi.org/10.1149/11402.0185ecst.

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We have evaluated the feasability of selectively growing, with a chlorinated chemistry, 20 to 30 nm thick SiGe:B Raised Sources and Drains with Ge concentration gradients (from 50% down to 20%-30%, typically) on each side of FD-SOI transistors. The motivation was twofold: (i) inject meaningful amounts of compressive strain in the channel of p-type MOS devices thanks to high Ge concentrations in layers sitting in the same plane than Si or SiGe channels and (ii) benefit from lower Ge concentration SiGe layers on top that are easier to germano-silicide. Growing a thin Si(:B) cap on SiGe:B otherwi

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13

Bhoir, Mandar S., and Nihar R. Mohapatra. "Effects of Scaling on Analog FoMs of UTBB FD-SOI MOS Transistors: A Detailed Analysis." IEEE Transactions on Electron Devices 67, no. 8 (2020): 3035–41. http://dx.doi.org/10.1109/ted.2020.3002878.

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Nocera, Claudio, Giuseppe Papotto, and Giuseppe Palmisano. "Two-Path 77-GHz PA in 28-nm FD-SOI CMOS for Automotive Radar Applications." Electronics 11, no. 8 (2022): 1289. http://dx.doi.org/10.3390/electronics11081289.

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This paper presents a 77 GHz two path power amplifier (PA) for automotive radar applications. It was fabricated in 28-nm fully depleted silicon-on-insulator CMOS technology, which provides transistors with a transition frequency of about 270 GHz and a general-purpose low cost back-end-of-line. The proposed PA consists of a 50 Ω input buffer followed by two power units, which are made up of a current-reuse common source driver for improved efficiency and a stacked cascode power stage for enhanced output power. A peak detector was also embedded into the PA for output power monitoring. The design

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15

Barboni, Leonardo. "Evidence of Limitations of the Transconductance-to-Drain-Current Method (gm/Id) for Transistor Sizing in 28 nm UTBB FD-SOI Transistors." Journal of Low Power Electronics and Applications 10, no. 2 (2020): 17. http://dx.doi.org/10.3390/jlpea10020017.

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The transconductance-to-drain-current method is a transistor sizing methodology that is commonly used in CMOS technology. In this study, we explored by means of simulations, a case of study and three figures of merit used for the method, and we conclude for the first time that the method should be reformulated. The study has been performed on Ultra-Thin Body and Buried Fully Depleted Silicon-On-Insulator 28 nm low-voltage-threshold NFET commercial technology (UTBB FD-SOI), and the simulations were performed via Spectre Circuit Simulator, by using the device model-card. To our knowledge, no pre

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Al Mamun, Fahad, Sarma Vrudhula, Dragica Vasileska, Hugh Barnaby, and Ivan Sanchez Esqueda. "Evidence of Transport Degradation in 22 nm FD-SOI Charge Trapping Transistors for Neural Network Applications." Solid-State Electronics 209 (November 2023): 108783. http://dx.doi.org/10.1016/j.sse.2023.108783.

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Le, Minh-Son, Thi-Nhan Pham, Thanh-Dat Nguyen, and Ik-Joon Chang. "A Variation-Aware Binary Neural Network Framework for Process Resilient In-Memory Computations." Electronics 13, no. 19 (2024): 3847. http://dx.doi.org/10.3390/electronics13193847.

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Binary neural networks (BNNs) that use 1-bit weights and activations have garnered interest as extreme quantization provides low power dissipation. By implementing BNNs as computation-in-memory (CIM), which computes multiplication and accumulations on memory arrays in an analog fashion, namely, analog CIM, we can further improve the energy efficiency to process neural networks. However, analog CIMs are susceptible to process variation, which refers to the variability in manufacturing that causes fluctuations in the electrical properties of transistors, resulting in significant degradation in B

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18

Favre, Luc, Mohammed Bouabdellaoui, Elie Assaf, Imene Guelil, Antoine Ronda, and Isabelle Berbezier. "(Invited) SiGe/SOI System: Mechanisms of Condensation and Strain Relaxation." ECS Meeting Abstracts MA2022-01, no. 20 (2022): 1088. http://dx.doi.org/10.1149/ma2022-01201088mtgabs.

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Silicon-Germanium strain engineering has been used for more than two decades in silicon based devices and has contributed to the scaling down of a transistor’s size and to significant improvements in device performance. However, while conventional silicon-germanium based electronics has experienced rapid and steady growth, thanks to this continuous miniaturization of transistors, this trend cannot continue indefinitely. Industry has already moved to alternate methods such as FinFET devices, in which a thin silicon channel is placed vertically, and the FD-SOI (FD-SGOI) design consisting of a th

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Gao, Shaochen, Duc-Tung Vu, Thibauld Cazimajou, et al. "Shallow Trench Isolation Patterning to Improve Photon Detection Probability of Single-Photon Avalanche Diodes Integrated in FD-SOI CMOS Technology." Photonics 11, no. 6 (2024): 526. http://dx.doi.org/10.3390/photonics11060526.

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The integration of Single-Photon Avalanche Diodes (SPADs) in CMOS Fully Depleted Silicon-On-Insulator (FD-SOI) technology under a buried oxide (BOX) layer and a silicon film containing transistors makes it possible to realize a 3D SPAD at the chip level. In our study, a nanostructurated layer created by an optimized arrangement of Shallow Trench Isolation (STI) above the photosensitive zone generates constructive interferences and consequently an increase in the light sensitivity in the frontside illumination. A simulation methodology is presented that couples electrical and optical data in or

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Bertrand, Isabelle, Philippe Flatresse, Guillaume Besnard, et al. "(G02 Best Paper Award Winner) Development Of High Resistivity FD-SOI Substrates for mmWave Applications." ECS Meeting Abstracts MA2022-01, no. 29 (2022): 1273. http://dx.doi.org/10.1149/ma2022-01291273mtgabs.

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The mmWave era opens up the door to revolutionary applications in the fields of communication, radar, imager, security, etc. FD-SOI CMOS technology is entering the mmW realm providing undeniable benefits in terms of data-rates, bandwidth, latency and power consumption improvements. The high resistivity substrate option is seen as a major booster to reach ultimate mmW performances. The engineering challenges related to this new wafer generation are addressed in this paper. In the different options for highly resistive silicon, low and high interstitial oxygen (Oi) materials are the most common

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Zheng, Qiwen, Jiangwei Cui, Liewei Xu, et al. "Total Ionizing Dose Responses of Forward Body Bias Ultra-Thin Body and Buried Oxide FD-SOI Transistors." IEEE Transactions on Nuclear Science 66, no. 4 (2019): 702–9. http://dx.doi.org/10.1109/tns.2019.2901755.

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22

de Souza, Michelly, Denis Flandre, Rodrigo Trevisoli Doria, Renan Trevisoli, and Marcelo Antonio Pavanello. "On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration." Solid-State Electronics 117 (March 2016): 152–60. http://dx.doi.org/10.1016/j.sse.2015.11.018.

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23

Zhang, Guohe, Junhua Lai, Yali Su, et al. "Study on the Thermal Conductivity Characteristics for Ultra-Thin Body FD SOI MOSFETs Based on Phonon Scattering Mechanisms." Materials 12, no. 16 (2019): 2601. http://dx.doi.org/10.3390/ma12162601.

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The silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) suffer intensive self-heating effects due to the reduced thermal conductivity of the silicon layer while the feature sizes of devices scale down to the nanometer regime. In this work, analytical models of thermal conductivity considering the self-heating effect (SHE) in ultra-thin body fully depleted (UTB-FD) SOI MOSFETs are presented to investigate the influences of impurity, free and bound electrons, and boundary reflection effects on heat diffusion mechanisms. The thermal conductivities of thin silic

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Watkins, A. C., S. T. Vibbert, J. V. D'Amico, et al. "Mitigating Total-Ionizing-Dose-Induced Threshold-Voltage Shifts Using Back-Gate Biasing in 22-nm FD-SOI Transistors." IEEE Transactions on Nuclear Science 69, no. 3 (2022): 374–80. http://dx.doi.org/10.1109/tns.2022.3146318.

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25

Yamaoka, M., R. Tsuchiya, and T. Kawahara. "SRAM Circuit With Expanded Operating Margin and Reduced Stand-By Leakage Current Using Thin-BOX FD-SOI Transistors." IEEE Journal of Solid-State Circuits 41, no. 11 (2006): 2366–72. http://dx.doi.org/10.1109/jssc.2006.882891.

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Maiellaro, Giorgio, Giovanni Caruso, Salvatore Scaccianoce, Mauro Giacomini, and Angelo Scuderi. "40 GHz VCO and Frequency Divider in 28 nm FD-SOI CMOS Technology for Automotive Radar Sensors." Electronics 10, no. 17 (2021): 2114. http://dx.doi.org/10.3390/electronics10172114.

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This paper presents a 40 GHz voltage-controlled oscillator (VCO) and frequency divider chain fabricated in STMicroelectronics 28 nm ultrathin body and box (UTBB) fully depleted silicon-on-insulator (FD-SOI) complementary metal-oxide–semiconductor (CMOS) process with eight metal layers back-end-of-line (BEOL) option. VCOs architecture is based on an LC-tank with p-type metal-oxide–semiconductor (PMOS) cross-coupled transistors. VCOs exhibit a tuning range (TR) of 3.5 GHz by exploiting two continuous frequency tuning bands selectable via a single control bit. The measured phase noise (PN) at 38

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Lespiaux, Justine, Joël Kanyandekwe, Tanguy Marion, et al. "Selective Epitaxial Growth of SiGe(:B) for Advanced p-Type Fd-SOI." ECS Meeting Abstracts MA2024-02, no. 32 (2024): 2356. https://doi.org/10.1149/ma2024-02322356mtgabs.

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Epitaxy is of major importance during the manufacturing of p-type metal oxide semiconductor field effect transistors (p-MOSFETs) for next generation fully depleted-silicon on insulator (FD-SOI) integrated circuits. A compressive-strained SiGe channel has indeed to be present in p-type regions for threshold voltage tuning and hole mobility boosting. In-situ boron-doped SiGe raised sources/drains (RSD) have otherwise to be used to reduce access resistance and, ideally, inject uniaxial compressive strain in the channel. Selective epitaxial growth (SEG) is needed for both types of layers,with depo

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Bhoir, Mandar S., Yogesh Singh Chauhan, and Nihar R. Mohapatra. "Back-Gate Bias and Substrate Doping Influenced Substrate Effect in UTBB FD-SOI MOS Transistors: Analysis and Optimization Guidelines." IEEE Transactions on Electron Devices 66, no. 2 (2019): 861–67. http://dx.doi.org/10.1109/ted.2018.2888799.

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Kanyandekwe, Joel, Jean-Michel Hartmann, Justine Lespiaux, et al. "Selective Epitaxy of Tensile, Highly Doped SiP for Planar NMOS FD-SOI Devices." ECS Meeting Abstracts MA2024-02, no. 32 (2024): 2355. https://doi.org/10.1149/ma2024-02322355mtgabs.

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Fabricating advanced Fully Depleted SOI (FD-SOI) Complementary Metal Oxide Semiconductor Field Effect Transistors (CMOS) require numerous material and process improvements. Junctions between metal contacts and the channel are considered to be of major importance as they have a direct impact on device performances. A well-controlled increase of the active dopant concentration in the sources and drains regions close to the channel is indeed required to lower the contact resistance. The Selective Epitaxial Growth of tens of nm thick heavily in-situ doped SiGe:B or Si:P Raised Sources and Drains (

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Kochiyama, M., T. Sega, K. Hara та ін. "Radiation effects in silicon-on-insulator transistors with back-gate control method fabricated with OKI Semiconductor 0.20μm FD-SOI technology". Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 636, № 1 (2011): S62—S67. http://dx.doi.org/10.1016/j.nima.2010.04.086.

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Goffioul, Michael, Gilles Dambrine, Danielle Vanhoenacker, and Jean-Pierre Raskin. "Comparison of microwave performances for sub-quarter micron fully- and partially-depleted SOI MOSFETs." Journal of Telecommunications and Information Technology, no. 3-4 (December 30, 2000): 72–80. http://dx.doi.org/10.26636/jtit.2000.3-4.25.

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The high frequency performances including microwave noise parameters for sub-quarter micron fully- (FD) and partially-depleted (PD) silicon-on-insulator (SOI) n-MOSFETs are described and compared. Direct extraction techniques based on the physical meaning of each small-signal and noise model element are used to extract the microwave characteristics of various FD and PD SOI n-MOSFETs with different channel lengths and widths. TiSi2 silicidation process has been demonstrated very efficient to reduce the sheet and contact resistances of gate, source and drain transistor regions. 0.25 um FD SOI n-

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Carvalho, Henrique Lanfredi, Ricardo Cardoso Rangel, Katia Sasaki, Leonardo Yojo, Paula Agopian, and Joao Martino. "Improved RFET Performance Using Dual-Aluminum-Contact (DAC)." ECS Meeting Abstracts MA2023-01, no. 33 (2023): 1855. http://dx.doi.org/10.1149/ma2023-01331855mtgabs.

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The reconfigurable field effect transistors (RFET) enable the integration of MOS-type transistors (N-type and P-type) in a single device. The programming gate voltage (VPG) controls the transistor type [1]. A greater area efficiency in logic circuits can be obtained, due to the possible different logic operation, such as NAND to NOR in a single circuit [2 - 3]. Others application include the use of RFET in circuits for security reason in order to avoid the reverse engineering [4]. Figure 1 (A) and (B) show a special type of RFET called BESOI MOSFET that will be one of the devices used in this

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Kanyandekwe, Joël, Matthias Bauer, Tanguy Marion, et al. "Very Low Temperature Tensile and Selective Si:P Epitaxy for Advanced CMOS Devices." ECS Meeting Abstracts MA2022-02, no. 32 (2022): 1190. http://dx.doi.org/10.1149/ma2022-02321190mtgabs.

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Nowadays, “more Moore” and “more than Moore” device architectures are becoming more and more complex. In CEA-Leti, we work on the “CoolCubeTM” 3D sequential integration which is based on the stacking of FDSOI devices [1]. We present solutions, at T<500°C, for the integration of SiP Raised Sources & Drains (RSD) in the upper devices without degrading the electrical performances of the bottom ones. We also target a lowering of the RSD resistance and an increase of the electron mobility in the channel of NMOS devices thanks to tensile strain [2]. Such a know-how will be useful to minimize

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Karsenty, Avi, and Avraham Chelly. "Anomalous DIBL Effect in Fully Depleted SOI MOSFETs Using Nanoscale Gate-Recessed Channel Process." Active and Passive Electronic Components 2015 (2015): 1–5. http://dx.doi.org/10.1155/2015/609828.

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Nanoscale Gate-Recessed Channel (GRC) Fully Depleted- (FD-) SOI MOSFET device with a silicon channel thickness (tSi) as low as 2.2 nm was first tested at room temperature for functionality check and then tested at low temperature (77 K) forI-Vcharacterizations. In spite of its FD-SOI nanoscale thickness and long channel feature, the device has surprisingly exhibited a Drain-Induced Barrier Lowering (DIBL) effect at RT. However, this effect was suppressed at 77 K. If the apparition of such anomalous effect can be explained by a parasitic short channel transistor located at the edges of the chan

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Bédécarrats, Thomas, Philippe Galy, Claire Fenouillet-Béranger, and Sorin Cristoloveanu. "Investigation of built-in bipolar junction transistor in FD-SOI BIMOS." Solid-State Electronics 159 (September 2019): 177–83. http://dx.doi.org/10.1016/j.sse.2019.03.057.

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Harame, David L. "Perspectives on How the "Sige, Ge, & Related Compounds: Materials, Processing, and Devices" Field Has Changed over the Last 20 Years." ECS Meeting Abstracts MA2022-02, no. 32 (2022): 1181. http://dx.doi.org/10.1149/ma2022-02321181mtgabs.

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The field of electronic devices and materials has seen major changes over the last ~20 years. The SiGe, Ge, & Related Compounds: Material Processing, and Devices symposium has documented much of this change. In 2004 the meeting grew out of a desire for the ECS to have a special ongoing symposium on SiGe & Ge as a materials system with increasing importance in silicon semiconductor technology. In 2008 the symposium was expanded to include Ge and Related compounds including SiC and III-Vs on Silicon to recognize the important work in these areas. In 2010 the symposium was expanded to inc

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Galy, Philippe, S. Athanasiou, and S. Cristoloveanu. "BIMOS transistor solutions for ESD protection in FD-SOI UTBB CMOS technology." Solid-State Electronics 115 (January 2016): 192–200. http://dx.doi.org/10.1016/j.sse.2015.09.001.

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Kanyandekwe, Joel, Jean-Michel Hartmann, Justine Lespiaux, et al. "Selective Epitaxy of Tensile, Highly Doped SiP for Planar NMOS FD-SOI Devices." ECS Transactions 114, no. 2 (2024): 253–70. http://dx.doi.org/10.1149/11402.0253ecst.

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The epitaxy of sources and drains is a critical enabler for enhanced transistor performances. In N-type MOS devices, selective SiP epitaxy can simultaneously yield (i) very high levels of electrically active dopants which is crucial for contact resistance minimization and (ii), tensile strain in Raised Sources and Drains (RSD) on each side of Si FD-SOI channels. This study present process solutions in order to benefit from large amounts of phosphorus in a silicon lattice and have thereby tensile strain, while maintaining excellent crystal quality, good surface morphology and a low electrical r

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Kushal, Gowda A. S., and RAMESH K.B. "Low Power Redundant Transition Free-Tspc Flip Flops Doble Edge Triggering Based On C Element and Single Transistor Clock Buffer." Journal of Advancement in Electronics Design 7, no. 3 (2024): 25–33. https://doi.org/10.5281/zenodo.13347117.

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<em>In the modern graphics processing unit (GPU)/artificial intelligence (AI) era, flip-flop (FF) has become one of the most power-hungry blocks in processor When the input signal has been interfered and glitches occur, the power consumption of Double-Edge Triggered Flip-Flops (DETFFs) will significantly increase. To effectively reduce the power consumption, this paper presents an low-power Redundant-Transition- DETFF based on C-elements. And single transistor clocked buffer The STCB uses a single-clocked transistor in the data sampling path, which completely removes clock redundant transition

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Kevkić, Tijana S., Vojkan R. Nikolić, Vladica S. Stojanović, Dragana D. Milosavljević, and Slavica J. Jovanović. "Modeling electrostatic potential in FDSOI MOSFETS: An approach based on homotopy perturbations." Open Physics 20, no. 1 (2022): 106–16. http://dx.doi.org/10.1515/phys-2022-0012.

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Abstract Modeling of the electrostatic potential for fully depleted (FD) silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET) is presented in this article. The modeling is based on the analytical solution of two-dimensional Poisson’s equation obtained by using the homotopy perturbation method (HPM). The HPM with suitable boundary conditions results in the so-called HPM solution in general and closed-form, independent of the surface potential. The HPM solution has been applied in modeling the output characteristics of the FDSOI MOSFET, which show good agreement

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Srikanya, K. "Low-Power Redundant-Transition-Free TSPC DET-FF with STCB for Enhanced Power and Area Efficiency." International Journal for Research in Applied Science and Engineering Technology 12, no. 11 (2024): 956–62. http://dx.doi.org/10.22214/ijraset.2024.65246.

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Abstract: In the contemporary era dominated by graphics processing units (GPUs) and artificial intelligence (AI), flip-flops (FFs) have emerged as power-intensive components within processors. Addressing this power consumption challenge, a pioneering approach introduces a single-phase clock dual-edge-triggering (DET) FF leveraging a single-transistor clocked (STC) buffer (STCB). This STCB employs a singular clocked transistor in the data sampling path, eliminating clock redundant transitions (RTs) and internal RTs observed in alternative DET designs. Validated through post-layout simulations i

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Dou, Cunhua, Weijia Song, Yu Yan, et al. "Model of threshold voltage and drain current in core-shell junctionless transistor on FD-SOI." Solid-State Electronics 229 (November 2025): 109173. https://doi.org/10.1016/j.sse.2025.109173.

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Dou, Cunhua, Weijia Song, Yu Yan, et al. "The Planar Core–Shell Junctionless MOSFET." Micromachines 16, no. 4 (2025): 418. https://doi.org/10.3390/mi16040418.

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The core–shell junctionless MOSFET (CS-JL FET) meets the process requirements of FD-SOI technology. The transistor body comprises a heavily doped ultrathin layer (core linking the source and the drain), located underneath an undoped layer (shell). Drain current, transconductance, and capacitance characteristics demonstrate striking performance improvement compared with conventional junctionless MOSFETs. The addition of the shell results in one order of magnitude higher mobility (peak value), transconductance, and drive current. The doping and thickness of the core can be engineered to achieve

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Sharma, Rajneesh, Rituraj S. Rathore, and Ashwani K. Rana. "Impact of High-k Spacer on Device Performance of Nanoscale Underlap Fully Depleted SOI MOSFET." Journal of Circuits, Systems and Computers 27, no. 04 (2017): 1850063. http://dx.doi.org/10.1142/s0218126618500639.

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The fully depleted Silicon-On-Insulator MOSFETs (FD-SOI) have shown high immunity to short channel effects compared to conventional bulk MOSFETs. The inclusion of gate underlap in SOI structure further improves the device performance in nanoscale regime by reducing drain induced barrier lowering and leakage current ([Formula: see text]). However, the gate underlap also results in reduced ON current ([Formula: see text]) due to increased effective channel length. The use of high-[Formula: see text] material as a spacer region helps to achieve the higher [Formula: see text] but at the cost of in

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Sweeney, Clint, Donald Y. C. Lie, Jill C. Mayeda, and Jerry Lopez. "Broadband Millimeter-Wave Front-End Module Design Considerations in FD-SOI CMOS vs. GaN HEMTs." Applied Sciences 14, no. 23 (2024): 11429. https://doi.org/10.3390/app142311429.

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Millimeter-wave (mm-Wave) phased array systems need to meet the transmitter (Tx) equivalent isotropic radiated power (EIRP) requirement, and that depends mainly on the design of two key sub-components: (1) the antenna array and (2) the Tx power amplifier (PA) in the front-end-modules (FEMs). Simulations using an electromagnetic (EM) solver carried out in Cadence AWR with AXIEM suggest that for two uniform square patch antenna arrays at 24 GHz, the 4 element array has ~6 dB lower antenna gain and twice the half power beam width (HPBW) compared to the 16 element array. We also present measuremen

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Cao, Yong-Feng, M. Arsalan, J. Liu, Yu-Long Jiang, and J. Wan. "A Novel One-Transistor Active Pixel Sensor With In-Situ Photoelectron Sensing in 22 nm FD-SOI Technology." IEEE Electron Device Letters 40, no. 5 (2019): 738–41. http://dx.doi.org/10.1109/led.2019.2908632.

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Artemio Schoulten, Felipe, Rémy Vauche, Jean Gaubert, Sylvain Bourdel, and André Augusto Mariano. "Design of a multi-standard IR-UWB emitter in a 28 nm FD-SOI technology based on the frequency transposition pulse synthesis." Journal of Integrated Circuits and Systems 18, no. 3 (2023): 1–11. http://dx.doi.org/10.29292/jics.v18i3.793.

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Ultra-WideBand Impulse Radio (IR-UWB) is a wireless communication technology well-suited for short range communications (about 10 meters) and has the advantage to allow real-time location with a precision of 5 cm. However, its use has been standardized in some standards and especially in the IEEE 802.15.4 dedicated to Wireless Personnal Area Network (WPAN) and in the IEEE 802.15.6 dedicated to Wireless Body Area Network (WBAN). After presenting requirements of each standard and a literature survey on the IR-UWB emitter, the design of a multi-standard IR-emitter based on the frequency transposi

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Duan, F. L., S. P. Sinha, D. E. Ioannou, and F. T. Brady. "LDD design tradeoffs for single transistor latch-up and hot carrier degradation control in accumulation mode FD SOI MOSFET's." IEEE Transactions on Electron Devices 44, no. 6 (1997): 972–77. http://dx.doi.org/10.1109/16.585553.

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Mayeda, Jill, Donald Y. C. Lie, and Jerry Lopez. "Broadband Millimeter-Wave 5G Power Amplifier Design in 22 nm CMOS FD-SOI and 40 nm GaN HEMT." Electronics 11, no. 5 (2022): 683. http://dx.doi.org/10.3390/electronics11050683.

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Three millimeter-wave (mm-Wave) power amplifiers (PAs) that cover the key 5G FR2 band of 24.25 to 43.5 GHz are designed in two different state-of-the-art device technologies and are presented in this work. First, a single-ended broadband PA that employs a third-order input matching network is designed in a 40 nm GaN/SiC HEMT (High Electron Mobility Transistor) technology. Good agreement between the measurement and post-layout parasitic extracted (PEX) electromagnetic (EM) simulation data is observed, and it achieves a measured 3-dB BW (bandwidth) of 18.0–40.3 GHz and >20% maximum PAE (power

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Golman, Roman, Robert Giterman, and Adam Teman. "Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism." Journal of Low Power Electronics and Applications 14, no. 1 (2024): 2. http://dx.doi.org/10.3390/jlpea14010002.

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Embedded memories occupy an increasingly dominant part of the area and power budgets of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher power due to larger memory bitcells. Gain-cell eDRAM is a high-density alternative for multi-ported operation with a small silicon footprint. However, conventional gain-cell memories have limited data availability, as they require periodic refresh operations to maintain their data. In this paper, we propose a novel multi-ported gain-cell design,

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