Relevant bibliographies by topics / Hardware-Software Codesign Accelerators

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Hardware-Software Codesign Accelerators'

Author: Grafiati
Published: 6 September 2023
Last updated: 31 July 2025

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Journal articles on the topic "Hardware-Software Codesign Accelerators"

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Xiao, Chunhua, Lei Zhang, Yuhua Xie, Weichen Liu, and Duo Liu. "Hardware/Software Adaptive Cryptographic Acceleration for Big Data Processing." Security and Communication Networks 2018 (August 27, 2018): 1–24. http://dx.doi.org/10.1155/2018/7631342.

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Along with the explosive growth of network data, security is becoming increasingly important for web transactions. The SSL/TLS protocol has been widely adopted as one of the effective solutions for sensitive access. Although OpenSSL could provide a freely available implementation of the SSL/TLS protocol, the crypto functions, such as symmetric key ciphers, are extremely compute-intensive operations. These expensive computations through software implementations may not be able to compete with the increasing need for speed and secure connection. Although there are lots of excellent works with th
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Kritikakou, Angeliki, Francky Catthoor, George S. Athanasiou, Vasilios Kelefouras, and Costas Goutis. "Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints." ACM Transactions on Architecture and Code Optimization 10, no. 2 (2013): 1–25. http://dx.doi.org/10.1145/2459316.2459317.

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Sorrentino, Giuseppe, Marco Venere, Davide Conficconi, Eleonora D’Arnese, and Marco Domenico Santambrogio. "Hephaestus : Codesigning and Automating 3D Image Registration on Reconfigurable Architectures." ACM Transactions on Embedded Computing Systems 22, no. 5s (2023): 1–24. http://dx.doi.org/10.1145/3607928.

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Healthcare is a pivotal research field, and medical imaging is crucial in many applications. Therefore finding new architectural and algorithmic solutions would benefit highly repetitive image processing procedures. One of the most complex tasks in this sense is image registration, which finds the optimal geometric alignment among 3D image stacks and is widely employed in healthcare and robotics. Given the high computational demand of such a procedure, hardware accelerators are promising real-time and energy-efficient solutions, but they are complex to design and integrate within software pipe
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Hernández, Mario, Juan M. Cebrián, José M. Cecilia, and José M. García. "Offloading strategies for Stencil kernels on the KNC Xeon Phi architecture: Accuracy versus performance." International Journal of High Performance Computing Applications 34, no. 2 (2017): 199–207. http://dx.doi.org/10.1177/1094342017738352.

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The ever-increasing computational requirements of HPC and service provider applications are becoming a great challenge for hardware and software designers. These requirements are reaching levels where the isolated development on either computational field is not enough to deal with such challenge. A holistic view of the computational thinking is therefore the only way to success in real scenarios. However, this is not a trivial task as it requires, among others, of hardware–software codesign. In the hardware side, most high-throughput computers are designed aiming for heterogeneity, where acce
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Morales-Sandoval, Miguel, Luis Armando Rodriguez Flores, Rene Cumplido, Jose Juan Garcia-Hernandez, Claudia Feregrino, and Ignacio Algredo. "A Compact FPGA-Based Accelerator for Curve-Based Cryptography in Wireless Sensor Networks." Journal of Sensors 2021 (January 6, 2021): 1–13. http://dx.doi.org/10.1155/2021/8860413.

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The main topic of this paper is low-cost public key cryptography in wireless sensor nodes. Security in embedded systems, for example, in sensor nodes based on field programmable gate array (FPGA), demands low cost but still efficient solutions. Sensor nodes are key elements in the Internet of Things paradigm, and their security is a crucial requirement for critical applications in sectors such as military, health, and industry. To address these security requirements under the restrictions imposed by the available computing resources of sensor nodes, this paper presents a low-area FPGA-prototyp
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Ahmed, O., S. Areibi, K. Chattha, and B. Kelly. "PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability." International Journal of Reconfigurable Computing 2011 (2011): 1–21. http://dx.doi.org/10.1155/2011/648483.

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Packet classification plays a crucial role for a number of network services such as policy-based routing, firewalls, and traffic billing, to name a few. However, classification can be a bottleneck in the above-mentioned applications if not implemented properly and efficiently. In this paper, we propose PCIU, a novel classification algorithm, which improves upon previously published work. PCIU provides lower preprocessing time, lower memory consumption, ease of incremental rule update, and reasonable classification time compared to state-of-the-art algorithms. The proposed algorithm was evaluat
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Ashna, Farheen, Fatima Zoha, and Tahura Muskan. "Applications of Embedded System Using AI: A Review." Journal of Optoelectronics and Communication 7, no. 2 (2025): 1–7. https://doi.org/10.5281/zenodo.15349209.

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<em>Conventional methods for implementing logic programming applications on embedded systems are software- based, requiring a compiler to convert the initial declarative logic program to its equivalent procedural one. This increases the complexity of the final implementation and reduces system performance. However, hardware implementations that only support logic programs prevent their use in applications where logic programs need to be intertwined with traditional procedural ones. This paper exploits HW/SW codesign methods to present a microprocessor capable of supporting hybrid ap- plication
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Pedram, Ardavan, Andreas Gerstlauer, and Robert A. van de Geijn. "Algorithm, Architecture, and Floating-Point Unit Codesign of a Matrix Factorization Accelerator." IEEE Transactions on Computers 63, no. 8 (2014): 1854–67. http://dx.doi.org/10.1109/tc.2014.2315627.

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Acer, Seher, Ariful Azad, Erik G. Boman, et al. "EXAGRAPH: Graph and combinatorial methods for enabling exascale applications." International Journal of High Performance Computing Applications 35, no. 6 (2021): 553–71. http://dx.doi.org/10.1177/10943420211029299.

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Combinatorial algorithms in general and graph algorithms in particular play a critical enabling role in numerous scientific applications. However, the irregular memory access nature of these algorithms makes them one of the hardest algorithmic kernels to implement on parallel systems. With tens of billions of hardware threads and deep memory hierarchies, the exascale computing systems in particular pose extreme challenges in scaling graph algorithms. The codesign center on combinatorial algorithms, ExaGraph, was established to design and develop methods and techniques for efficient implementat
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Kumar, Rakesh, Alejandro Martínez, and Antonio González. "Efficient Power Gating of SIMD Accelerators Through Dynamic Selective Devectorization in an HW/SW Codesigned Environment." ACM Transactions on Architecture and Code Optimization 11, no. 3 (2014): 1–23. http://dx.doi.org/10.1145/2629681.

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Dissertations / Theses on the topic "Hardware-Software Codesign Accelerators"

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Sredojević, Ranko Radovin. "Template-based hardware-software codesign for high-performance embedded numerical accelerators." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/84895.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (pages 129-132).<br>Sophisticated algorithms for control, state estimation and equalization have tremendous potential to improve performance and create new capabilities in embedded and mobile systems. Traditional implementation approaches are not well suited for porting these algorithmic solutions into practical implementations within embedded system constraints. Most of the technical challenges
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Fons, Lluís Mariano. "Hardware accelerators for embedded fingerprint-based personal recognition systems." Doctoral thesis, Universitat Rovira i Virgili, 2012. http://hdl.handle.net/10803/83493.

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Abstract The development of automatic biometrics-based personal recognition systems is a reality in the current technological age. Not only those operations demanding stringent security levels but also many daily use consumer applications request the existence of computational platforms in charge of recognizing the identity of one individual based on the analysis of his/her physiological and/or behavioural characteristics. The state of the art points out two main open problems in the implementation of such applications: on the one hand, the needed reliability improvement in terms of recogniti
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Ramesh, Chinthala. "Hardware-Software Co-Design Accelerators for Sparse BLAS." Thesis, 2017. http://etd.iisc.ac.in/handle/2005/4276.

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Sparse Basic Linear Algebra Subroutines (Sparse BLAS) is an important library. Sparse BLAS includes three levels of subroutines. Level 1, Level2 and Level 3 Sparse BLAS routines. Level 1 Sparse BLAS routines do computations over sparse vector and spare/dense vector. Level 2 deals with sparse matrix and vector operations. Level 3 deals with sparse matrix and dense matrix operations. The computations of these Sparse BLAS routines on General Purpose Processors (GPPs) not only suffer from less utilization of hardware resources but also takes more compute time than the workload due to poor data loc
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Book chapters on the topic "Hardware-Software Codesign Accelerators"

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Ha, Soonhoi, and Donghyun Kang. "Hardware–Software Codesign of an Adder-Tree Type CNN Accelerator." In Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing. Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-39932-9_18.

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Ben Othman, Slim, Ahmed Karim Ben Salem, and Slim Ben Saoud. "Performance Analysis of FPGA Architectures based Embedded Control Applications." In Reconfigurable Embedded Control Systems. IGI Global, 2011. http://dx.doi.org/10.4018/978-1-60960-086-0.ch011.

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The performances of System on Chip (SoC) and the Field Programmable Gate Array (FPGA) particularly, are increasing continually. Due to the growing complexity of modern embedded control systems, the need of more performance digital devices is evident. Recent FPGA technology makes it possible to include processor cores into the FPGA chip, which ensures more flexibility for digital controllers. Indeed, greater functionality of hardware and system software, Real-Time (RT) platforms and distributed subsystems are demanded. In this chapter, a design concept of FPGA based controller with Hardware/Sof
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Conference papers on the topic "Hardware-Software Codesign Accelerators"

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Qin, Yifan, Zheyu Yan, Wujie Wen, Xiaobo Sharon Hu, and Yiyu Shi. "Special Session: Sustainable Deployment of Deep Neural Networks on Non-Volatile Compute-in-Memory Accelerators." In 2024 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). IEEE, 2024. http://dx.doi.org/10.1109/codes-isss60120.2024.00017.

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Temam, O. "Hardware neural network accelerators." In 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). IEEE, 2013. http://dx.doi.org/10.1109/codes-isss.2013.6659008.

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Glint, Tom, Kailash Prasad, Jinay Dagli, et al. "Hardware-Software Codesign of DNN Accelerators Using Approximate Posit Multipliers." In ASPDAC '23: 28th Asia and South Pacific Design Automation Conference. ACM, 2023. http://dx.doi.org/10.1145/3566097.3567866.

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Pasricha, Sudeep. "EDAML 2022 Invited Speaker 10: Hardware/Software Codesign for Optical Deep Learning Accelerators." In 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). IEEE, 2022. http://dx.doi.org/10.1109/ipdpsw55747.2022.00203.

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Vogel, Pirmin, Andrea Marongiu, and Luca Benini. "Lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs." In 2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). IEEE, 2015. http://dx.doi.org/10.1109/codesisss.2015.7331367.

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Wang, Xuan, Chao Wang, and Xuehai Zhou. "Work-in-Progress: WinoNN: Optimising FPGA-based Neural Network Accelerators using Fast Winograd Algorithm." In 2018 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). IEEE, 2018. http://dx.doi.org/10.1109/codesisss.2018.8525909.

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Gong, Lei, Chao Wang, Xi Li, and Xuehai Zhou. "WiderFrame: An Automatic Customization Framework for Building CNN Accelerators on FPGAs: Work-in-Progress." In 2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). IEEE, 2020. http://dx.doi.org/10.1109/codesisss51650.2020.9244024.

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Colucci, Alessio, Alberto Marchisio, Beatrice Bussolino, et al. "A Fast Design Space Exploration Framework for the Deep Learning Accelerators: Work-in-Progress." In 2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). IEEE, 2020. http://dx.doi.org/10.1109/codesisss51650.2020.9244038.

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Conti, Francesco, Andrea Marongiu, and Luca Benini. "Synthesis-friendly techniques for tightly-coupled integration of hardware accelerators into shared-memory multi-core clusters." In 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). IEEE, 2013. http://dx.doi.org/10.1109/codes-isss.2013.6658992.

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Qin, Yunji, Lei Gong, Zhendong Zheng, and Chao Wang. "Work-in-Progress: BloCirNN: An Efficient Software/hardware Codesign Approach for Neural Network Accelerators with Block-Circulant Matrix." In 2022 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). IEEE, 2022. http://dx.doi.org/10.1109/codes-isss55005.2022.00010.

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