Relevant bibliographies by topics / High Temperature Gate Bias - HTGB

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'High Temperature Gate Bias - HTGB'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "High Temperature Gate Bias - HTGB"

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Principato, Fabio, Giuseppe Allegra, Corrado Cappello, Olivier Crepel, Nicola Nicosia, Salvatore D′Arrigo, Vincenzo Cantarella, et al. "Investigation of the Impact of Neutron Irradiation on SiC Power MOSFETs Lifetime by Reliability Tests." Sensors 21, no. 16 (August 20, 2021): 5627. http://dx.doi.org/10.3390/s21165627.

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High temperature reverse-bias (HTRB), High temperature gate-bias (HTGB) tests and electrical DC characterization were performed on planar-SiC power MOSFETs which survived to accelerated neutron irradiation tests carried out at ChipIr-ISIS (Didcot, UK) facility, with terrestrial neutrons. The neutron test campaigns on the SiC power MOSFETs (manufactered by ST) were conducted on the same wafer lot devices by STMicroelectronics and Airbus, with different neutron tester systems. HTGB and HTRB tests, which characterise gate-oxide integrity and junction robustness, show no difference between the non irradiated devices and those which survived to the neutron irradiation tests, with neutron fluence up to 2× 1011 (n/cm2). Electrical characterization performed pre and post-irradiation on different part number of power devices (Si, SiC MOSFETs and IGBTs) which survived to neutron irradiation tests does not show alteration of the data-sheet electrical parameters due to neutron interaction with the device.
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Lee, Kwangwon, Young Ho Seo, Taeseop Lee, Kyeong Seok Park, Martin Domeij, Fredrik Allerstam, and Thomas Neyer. "Effect of Phosphorus Doped Poly Annealing on Threshold Voltage Stability and Thermal Oxide Reliability in 4H-SiC MOSFET." Materials Science Forum 1004 (July 2020): 554–58. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.554.

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We have investigated the effect of high temperature annealing of phosphorus doped poly on gate oxide integrity and device reliability. In NMOS capacitance analysis, unstable flat band voltage characteristics and lower oxide breakdown electric field were observed in wafers which received high temperature poly annealing at 1100 °C. Gate oxide integrity (GOI/Vramp) tests and time dependent dielectric breakdown (TDDB) tests were performed to evaluate wafer level reliability. Degraded GOI characteristics and poor gate oxide lifetime were obtained for the high temperature poly annealed condition. To evaluate package level reliability, high temperature gate bias (HTGB) stress tests were conducted. Some samples failed in positive gate bias stress and more severe negative threshold voltage shift was observed in negative gate bias stress for the high temperature poly annealed condition.
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Das, Mrinal K., Sarah K. Haney, Jim Richmond, Anthony Olmedo, Q. Jon Zhang, and Zoltan Ring. "SiC MOSFET Reliability Update." Materials Science Forum 717-720 (May 2012): 1073–76. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.1073.

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Significant advancement has been made in the gate oxide reliability of SiC MOS devices to enable the commercial release of Cree’s Z-FET™ product. This paper discusses the key reliability results from Time-Dependent-Dielectric-Breakdown (TDDB) and High Temperature Gate Bias (HTGB) measurements that indicate that the SiC MOSFETs can demonstrate excellent lifetime and stable operation in the field.
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van Brunt, Edward, Michael O’Loughlin, Al Burk, Brett Hull, Sei Hyung Ryu, Jim Richmond, Yuri Khlebnikov, et al. "Industrial and Body Diode Qualification of Gen-III Medium Voltage SiC MOSFETs: Challenges and Solutions." Materials Science Forum 963 (July 2019): 805–10. http://dx.doi.org/10.4028/www.scientific.net/msf.963.805.

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In this work, we report the results of industrial qualification tests run on medium voltage SiC MOSFETs rated for 3.3 kV/40 A and 10 kV/15 A. The JEDEC JESD47J.01 standard was used as a guideline to conduct HTRB (High Temperature, Reverse Bias), HTGB (High Temperature, Gate Bias), and TDDB (Time Dependent Dielectric Breakdown) tests. No devices were found to have failed the qualification tests, and long oxide lifetime was projected for constant operation under positive bias. This paper also reports for the first time the results of qualification testing of the MOSFET body diode on a large population of medium voltage SiC MOSFETs. Constant current stress at a current equal to the device forward rating was applied for 1000 hours. No degradation of any device parameter was observed for 3 lots of devices at both the 3.3 kV and 10 kV voltage rating.
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Habersat, Daniel B., Aivars Lelis, and Ronald Green. "Influence of High-Temperature Bias Stress on Room-Temperature VT Drift Measurements in SiC Power MOSFETs." Materials Science Forum 963 (July 2019): 757–62. http://dx.doi.org/10.4028/www.scientific.net/msf.963.757.

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Our results reinforce the notion of the need for an improved high-temperature gate bias (HTGB) test method — one which discourages the use of slow (greater than ~1 ms) threshold-voltage (VT) measurements at elevated temperatures and includes biased cool-down if room temperature measurements are performed, to ensure that any ephemeral effects during the high-temperature stress are observed. The paper presents a series of results on both state-of-the-art commercially-available devices as well as older vintage devices that exhibit enhanced charge-trapping effects. Although modern devices appear to be robust, it is important to ensure that any new devices released commercially, especially by new vendors, are properly evaluated for VT stability.
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Lichtenwalner, Daniel J., Shadi Sabri, Edward Van Brunt, Brett Hull, Sei Hyung Ryu, Philipp Steinmann, Amy Romero, et al. "Accelerated Testing of SiC Power Devices under High-Field Operating Conditions." Materials Science Forum 1004 (July 2020): 992–97. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.992.

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Power metal-oxide-semiconductor field-effect transistors (MOSFETs) experience conditions of high field during normal operation. During switching conditions, unexpected transient events may occur which force devices into avalanche or short circuit conditions. Moreover, silicon carbide devices typically experience higher fields in the gate oxide and drift regions than comparable Si devices due to channel and drift property differences. A summary of SiC MOSFET reliability and ruggedness test results are reported here. Reliability tests under high field conditions: positive-bias and negative-bias temperature instability (PBTI, NBTI) to examine threshold stability; time-dependent dielectric breakdown (TDDB) for gate oxide lifetime extrapolation; high-temperature reverse bias (HTRB); and HTRB testing under high neutron flux to determine terrestrial neutron single-event burnout (SEB) rates. High-power ruggedness evaluation is presented for SiC MOSFETs under forced avalanche conditions (unclamped inductive switching (UIS)) and under short-circuit operation to bound device safe operating areas. Overall results demonstrate the intrinsic reliability of SiC MOSFETs.
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Cheng, Lin, P. Martin, Michael S. Mazzola, David C. Sheridan, R. L. Kelly, Volodymyr Bondarenko, S. Morrison, et al. "High-Temperature Static and Dynamic Reliability Study of 4H-SiC Vertical-Channel JFETs for High-Power System Applications." Materials Science Forum 600-603 (September 2008): 1051–54. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.1051.

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In this work we report the most recent high-temperature long-term reliability results of the 600 V/14 A, 4H-SiC vertical-channel junction field-effect transistors (VJFETs). Two groups (A and B) devices were subjected to different thermal and electrical stresses. One device (Group A) reached 12,000 hours of continuous switching without a single failure. Four devices in Group A were thermally stressed at 250 °C over 4,670 hours in air, for which standard deviation of the specific on-resistance (RONSP) in linear region at gate bias (VGS) of 3 V were < 4.1% throughout the entire duration time. The off-state characteristics were evaluated by high temperature reverse bias (HTRB) tests. Three devices (Group A) were biased at 50% rated BVDS at 250 °C for 2,278 hours. A higher reverse bias at 80 % rated BVDS was then applied to 14 devices (group B) at 200 °C for 1,000 hours. Variations of the leakage current were negligible throughout the entire HTRB test for all tested devices.
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Gendron-Hansen, Amaury, Changsoo Hong, Yi Fan Jiang, John May, Dumitru Sdrulla, Bruce Odekirk, and Avinash S. Kashyap. "Commercialization of Highly Rugged 4H-SiC 3300 V Schottky Diodes and Power MOSFETs." Materials Science Forum 1004 (July 2020): 822–29. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.822.

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In this paper, we present a new family of 3300 V silicon carbide (SiC) Schottky barrier diodes (SBDs) and power MOSFETs. The main design requirements are discussed with an emphasis on the design rules to improve the long-term reliability. Basic static and dynamic performance demonstrates low conduction and switching losses. Long-term tests such as high-temperature reverse bias (HTRB) and body diode forward bias stress were performed to evaluate the devices’ reliability. An emission microscopy (EMMI) study was conducted to assess the quality of the gate oxide. Outstanding surge and avalanche capabilities are reported with UIS ruggedness of 11.4 and 20.8 J.cm-2 for SBDs and MOSFETs, respectively.
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Chowdhury, Sauvik, Levi Gant, Blake Powell, Kasturirangan Rangaswamy, and Kevin Matocha. "Reliability and Ruggedness of 1200V SiC Planar Gate MOSFETs Fabricated in a High Volume CMOS Foundry." Materials Science Forum 924 (June 2018): 697–702. http://dx.doi.org/10.4028/www.scientific.net/msf.924.697.

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This paper presents the performance, reliability and ruggedness characterization of 1200V, 80mΩ rated SiC planar gate MOSFETs, fabricated in a high volume, 150mm silicon CMOS foundry. The devices showed a specific on-resistance of 5.1 mΩ.cm2 at room temperature, increasing to 7.5 mΩ.cm2 at 175 °C. Total switching losses were less than 300μJ (VDD = 800V, ID = 20A). The devices showed excellent gate oxide reliability with VTH shifts under 0.2V for extended HTGB stress testing at 175 °C for up to 5500 hours (VGS = 25V) and 2500 hours (VGS = -10V). Ruggedness performance such as unclamped inductive load switching and short circuit capability are also discussed.
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Yang, L., and A. Castellazzi. "High temperature gate-bias and reverse-bias tests on SiC MOSFETs." Microelectronics Reliability 53, no. 9-11 (September 2013): 1771–73. http://dx.doi.org/10.1016/j.microrel.2013.07.065.

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Dissertations / Theses on the topic "High Temperature Gate Bias - HTGB"

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Aviñó, Salvadó Oriol. "Contribution to the study of the SiC MOSFETs gate oxide." Thesis, Lyon, 2018. http://www.theses.fr/2018LYSEI110/document.

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Les MOSFET en SiC sont appelées à remplacer les IGBT en Silicium pour des applications de demandant une plus forte vitesse de commutation. Cependant, les MOSFET en SiC ont encore quelques problèmes de fiabilité, tels que la robustesse de la diode interne ou bien la robustesse de l'oxyde de grille. Cette dernière est liée à l’oxyde de grille des composants du type MOSFET. Des instabilités de la tension de seuil sont aussi signalées. Cette thèse aborde ces deux sujets sur des MOSFET commerciaux 1200 V. L'étude de la diode interne met en évidence que les caractéristiques I-V (de la diode intrinsèque) demeurent stables après l'application d'un stress. Cependant, une dérive surprenante de la tension de seuil apparaît. Des tests complémentaires, en stressant le canal à la place de la diode, avec les mêmes contraintes n'ont pas montré de dérive significative de la tension de seuil. Donc, l'application d'un stress en courant quand le composant est en mode d'accumulation semble favoriser l'apparition des instabilités de la tension de seuil. La robustesse de l'oxyde de grille concerne les instabilités de la tension de seuil, mais aussi l'estimation de la durée de vie à des conditions d'opération nominales. Les résultats obtenus montrent que la durée de vie de l'oxyde de grille n'est plus un problème. Pourtant, le suivi du courant de grille pendant les tests ainsi que les caractérisations de la capacité de grille mettent en évidence des translations de la courbe C(V) à cause des phénomènes d’injection des porteurs et de piégeage, mais aussi la possible présence d’ions mobiles. Aussi, une bonne analyse des dégradations et dérives liées à l’oxyde de grille doit être réalisée
SiC power MOSFETs are called to replace Si IGBT for some medium and high power applications (hundreds of kVA). However, even if crystallographic defects have been drastically reduced, SiC MOSFETs are always concerned by some robustness issues such as the internal diode robustness or the robustness of the gate oxide. The last one especially affects MOSFETs devices and is linked to the apparition of instabilities in the threshold voltage. This thesis focuses on these two issues. The study of the internal diode robustness highlighted that the I-V curve (of the intrinsic diode) remains stable after the application of a current stress in static mode, but also with the DUT placed in a converter with inductive switchings. These are the most stressful conditions. However, a surprising drift in the threshold voltage has been observed when some devices operates under these conditions; in static mode or in a converter. Complementary tests stressing the channel instead of the internal diode in the same temperature and dissipated power, have not resulted in a drift of the threshold voltage. Thus, the application of a current stress when the device is in accumulation regime could favour the apparition of instabilities in the threshold voltage. The study of the gate oxide focus in the instabilities of the threshold voltage, but also on the expected lifetime of the oxide at nominal conditions. Results obtained shown that the expected lifetime (TDDB) of the oxide is no longer a problem. Indeed, tests realized in static mode, but also in a converter under inductive switching conditions resulted in expected lifetimes well above 100 years. However, the monitoring of the gate current during the test and gate capacitance characterizations C(V) highlighted a shift in the capacitance due to carrier injection and trapping phenomena and probably to the presence of mobile-ions. Still regarding the instabilities of the threshold voltage, classic tests resulted in no significant variations of the threshold voltage at 150 _C. However, at 200 _C the drift observed for some manufacturers is higher than +30%. This is unacceptable for high-temperature applications and evidence that the quality of the gate oxide and the SiC=SiO2 interface must continue to be improved, together with the manufacturing methods to minimize the presence of mobile ions in the substrate
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Molin, Quentin. "Contribution à l’étude de la robustesse des MOSFET-SiC haute tension : Dérive de la tension de seuil et tenue aux courts-circuits." Thesis, Lyon, 2018. http://www.theses.fr/2018LYSEI111.

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Ce manuscrit est une contribution à l’étude de la fiabilité et de la robustesse des composants MOSFET sur carbure de silicium, matériau semi-conducteur grand gap qui possède des caractéristiques bien meilleures que le silicium. Ces nouveaux interrupteurs de puissances permettent d’obtenir entre autres propriétés remarquables, des fréquences de commutations et des tenues en tension plus élevées dans les systèmes de conversions de puissance. Ils sont particulièrement mis en avant depuis un peu plus d’une dizaine d’années pour les gains en performances, diminution des tailles et poids qu’ils apportent à certaines topologies de convertisseurs pour les réseaux haute tension à courant continu. Puis sont répertoriés les principaux mécanismes de défaillances de ces MOSFET SiC induits par la faiblesse de la grille. Toutes les mesures nécessaires au suivi des paramètres clés lors des prochains vieillissements sont présentées. Les résultats de nos tests sur l’instabilité de la tension de seuil sont aussi détaillés et un modèle empirique pour valider le comportement de relaxation observé est proposé. Celui-ci nous aidera par la suite à établir un protocole de mesure rigoureux de la tension de seuil. Les tests expérimentaux et résultats de vieillissement en statique et dynamique sur les composants 1,7 kV vont permettre de se rendre compte de l’importance de la dérive de la tension de seuil sur 1000 h. Dans le cas d’un vieillissement statique, il y a environ 7 % de dérive positive du VTH et un pourcentage équivalent pour les tests dynamiques. Des analyses supplémentaires (C-V et pompage de charge) sur l’oxyde de grille en cours de vieillissement sont proposées pour une meilleure compréhension des mécanismes mis en jeu dans la dégradation de l’oxyde. Enfin, les derniers tests présentés seront focalisés sur le comportement en court-circuit et courts-circuits répétitifs des mêmes composants. Avec une énergie critique évaluée autour de 1,5 J nos tests sur les MOSFET 1,7 kV montrent les limites de la robustesse de ces composants, avec une tenue en court-circuit bien inférieure à 10 µs et une incapacité à résister à plus de 150 courts-circuits successifs. L’influence de la tension entre drain et source y est notamment étudiée, et montre que l’énergie critique supportée par le composant diminue avec l’augmentation de cette tension
This manuscript is a contribution to reliability and robustness study of MOSFET components on silicon carbide “SiC”, wide band gap semiconductor with better characteristics compared to silicon “Si” material. Those new power switches can provide better switching frequencies or voltage withstanding for example in power converter. SiC MOSFET are the results of approximately 10 years of research and development and can provide increased performances and weight to some converter topology for high voltage direct current networks. Others power switches available are still introduced and an introduction to reliability is explaining why such work on this new power switches is important. Transition from Si technologies to SiC ones require a lot of work regarding its robustness. Before showing reliability and robustness results is presented I give a lot of details regarding to the measurement and monitoring of key parameters used in the next chapters. The results of our tests on the threshold voltage instability are presented and how we validated an empirical model on this drift. This was used to propose an enhanced measurement protocol on the threshold voltage. Static and dynamic experimental results presented next will show if the voltage drift during ageing is significant or not. Further analysis is proposed to add more insight on the understanding of the oxide degradation mechanisms through C-V and charge pumping measurements. Finally, the ageing results presented on 1,7 kV SiC MOSFET are focused on the short-circuit and repetitive short-circuit behavior of the same components. Drain to source voltage influence on critical energy during this particular and stressful operation mode is studied. This time, the results are worrying.The last chapter is confidential
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Kim, Samuel H. "Addressing thermal and environmental reliability in GaN based high electron mobility transistors." Thesis, Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/52244.

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AlGaN/GaN high electron mobility transistors (HEMTs) have appeared as attractive candidates for high power, high frequency, and high temperature operation at microwave frequencies. In particular, these devices are being considered for use in the area of high RF power for microwave and millimeter wave communications transmitter applications at frequencies greater than 100 GHz and at temperatures greater than about 150 °C. However, there are concerns regarding the reliability of AlGaN/GaN HEMTs. First of all, thermal reliability is the chief concern since high channel temperatures significantly affect the lifetime of the devices. Therefore, it is necessary to find the solutions to decrease the temperature of AlGaN/GaN HEMTs. In this study, we explored the methods to reduce the channel temperature via high thermal conductivity diamond as substrates of GaN. Experimental verification of AlGaN/GaN HEMTs on diamond substrates was performed using micro-Raman spectroscopy, and investigation of the design space for devices was conducted using finite element analysis as well. In addition to the thermal impact on reliability, environmental effects can also play a role in device degradation. Using high density and pinhole free films deposited using atomic layer deposition, we also explore the use of ultra-thin barrier films for the protection of AlGaN/GaN HEMTs in high humidity and high temperature environments. The results show that it is possible to protect the devices from the effects of moisture under high negative gate bias stress testing, whereas devices, which were unprotected, failed under the same bias stress conditions. Thus, the use of the atomic layer deposition (ALD) coatings may provide added benefits in the protection and packaging of AlGaN/GaN HEMTs.
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Wang, Chih-Yu, and 王志宇. "Positive Bias Temperature Instability(PBTI) Analysis and Simulation in 22 nm High-k Metal Gate nMOSFETs." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/64063337299664947310.

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碩士
國立交通大學
電子研究所
99
In this dissertation a new method to predict the post-stress threshold voltage distribution is introduced. We proposed the fast transient measurement, which minimizes the switching delay between stress and measurement. Consequently, a staircase-like post-positive bias temperature (PBT) current instability caused by single electron trapping is investigated. To analyze the characteristic of PBTI stress induced threshold voltage degradation. First, we extract the probability distribution of the single electron trapping induced drain current degradation. Second, the time model is developed in stress and recovery phase. According to the characterization of the single charge phenomenon, we proposed a Monte Carlo simulation to simulate the post-stress threshold voltage distribution.
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Liao, Jing-chyi, and 廖竟淇. "Investigations of Gate Induced Drain Leakage (GIDL) and Bias Temperature Instability (BTI) on LTPS TFTs and Hf-based High-k CMOSFETs." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/70836009323483888143.

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博士
國立成功大學
微電子工程研究所碩博士班
97
In this thesis, the trapping characteristics of positive bias temperature instability (PBTI) on a high-k/metal gate n-type metal oxide semiconductor field effect transistor (nMOSFET) have been firstly investigated with a complementary multi-pulse technique (CMPT) in detail. With the CMPT technique, we find that the threshold voltage shifts after PBTI are higher than that with the conventional direct current method, and the thickness of the SiO2 interfacial layer has a significant effect on the measured results. The observation of these new results is attributed to the CMPT technique has the unique feature of effectively reducing the detrapping effect induced by the large bulk traps existed in high-k dielectrics. Besides, based on the results, the mechanism of PBTI in metal gate/high-k nMOSFETs is modeled. Furthermore, with the terrace high-k method and the frequency-dependent charge pumping technique, the profile of bulk traps in the Hf-based dielectric is sketched to further understand the mechanism of trapping in high-k dielectrics. Secondly, the bias temperature instability of dual metal gate CMOSFETs with Hf-based dielectrics including HfO2 and HfSiON has been extremely investigated. The influences of high-k gate stacks engineering including zirconium and nitrogen incorporation on performance and BTI of high-k/metal gate MOSFET are studied. We find that the density of bulk traps is reduced with increasing Zr content with a comparable Dit value. Consequently, mobility increases with increasing Zr content in the HfZrOX dielectric and ~25% mobility enhancement compared with that of HfO2 can be observed. The improvement in PBTI is also demonstrated with DC and pulse techniques. The smaller Vth shift in PBTI is attributed to the reduction of fast trapping and the generation of slow traps. On the other hand, experimental results revealed the high-k dielectric nitrogen annealing is a better solution for the trade-off between mobility and inversion oxide thickness (TOX, INV) than IL nitrogen annealing. In addition, the positive bias temperature instability (PBTI) characteristic is improved through reducing the quantity of bulk traps. However, the high-k dielectric nitrogen annealing also lowers the barrier of dielectric and thus results in an abnormally higher leakage current. Furthermore, the strain effect from a tensile SiN capping layer, as well as the channel length dependence, on both NBTI and PBTI of the high-k gate stack devices are studied. For channel length larger than 0.1 µm, both PBTI and NBTI are not affected by the tensile strain obviously. As the channel scaling down to less than 0.1 µm, the degradation after PBTI stress is still not influenced by the strain, however, the NBTI degradation is enhanced significantly. In addition, the dependence of BTI on channel length is extensively investigated under constant voltage and field stress. Thirdly, a comprehensive study on bulk trap enhanced gate induced drain leakage currents (BTE-GIDL) in high-k MOSFETs is reported. The dependence of GIDL for various parameters including the effect of Zr concentration in HfZrOX, high-k film thickness, and electrical stress is investigated. The incorporation of Zr into HfO2 reduces GIDL. GIDL is also found to reduce with thinner high-k film. In addition, a significant correlation between GIDL and bulk trap density in high-k film is established. Possible mechanisms are provided to explain the role of bulk trapping in BTE-GIDL. Furthermore, the effects of shallow trench isolation (STI) induce mechanical strain on GIDL current in Hf-based and SiON nMOSFETs are investigated in detail. The STI-induced mechanical strain enhances the GIDL current including the trap-assisted tunneling (TAT) component at low voltage and the band-to-band tunneling (BBT) component at high voltage. The compressive strain induced band narrowing and the increase of intrinsic carrier concentration are attributed to the root cause of GIDL increment, respectively. However, different strain sensitivities of GIDL are observed on HfO2 and SiON nMOSFETs. The higher density of interface states induced by mechanical strain is responsible for the higher strain sensitivity observed on HfO2 devices. The symmetric layout shows higher ability to suppress the STI-enhanced GIDL current with same active area length. Finally, the dynamic NBTI on low-temperature polycrystalline silicon thin film transistors (LTPS TFTs) is investigated in detail. Experimental results reveal the threshold voltage shift of LTPS TFTs after the NBTI stress decreases with increasing frequency, which is different to the frequency-independent of conventional CMOSFET. The difference of transit time between grain boundary and Si/SiO2 interface dominates the LTPS TFTs dynamic NBTI behaviors and results in the dependence of frequency.
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Book chapters on the topic "High Temperature Gate Bias - HTGB"

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"Negative Bias Temperature Instabilites in High-k Gate Dielectrics." In Defects in Microelectronic Materials and Devices, 375–96. CRC Press, 2008. http://dx.doi.org/10.1201/9781420043778-16.

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Houssa, M., M. Aoulaiche, S. De Gendt, G. Groeseneken, and M. Heyns. "Negative Bias Temperature Instabilities in High-k Gate Dielectrics." In Defects in Microelectronic Materials and Devices. CRC Press, 2008. http://dx.doi.org/10.1201/9781420043778.ch12.

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Kaneriya, Rakesh, Gunjan Rastogi, Palash Basu, Rajesh Upadhyay, and Apurba Bhattacharya. "A Novel Approach for Room-Temperature Intersubband Transition in GaN HEMT for Terahertz Applications." In Terahertz Technology [Working Title]. IntechOpen, 2021. http://dx.doi.org/10.5772/intechopen.98435.

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Terahertz (THz) technology has attracted tremendous attention recently due to its promising applications in various domains such as medical, biological, industrial imaging, broadband, safety, communication, radar, space science, and so on. Due to non-availability of powerful sources and highly sensitive and efficient detectors, the so-called THz gap remains largely unfilled. Despite seamless efforts from electronics and photonics technology researchers, the desired level of technology development to fill the THz gap still remains a challenge. GaN-based HEMT structures have been investigated as potential THz sources and detectors by a number of researchers. This chapter presents a very new and versatile mechanism for electrical tuning of intersubband transitions (ISBT) GaN high electron mobility transition (HEMT) devices. ISBT phenomena are usually demonstrated in photonic devices like a quantum cascade laser (QCL). Here we explore ISBT in an electronic GaN HEMT device. Conventional photonic devices like a QCL are operated at cryogenic temperature to minimize thermal effect. Tuning the conduction band through external gate bias is an advantage of an HEMT device for room temperature (RT) THz applications. This chapter demonstrates the theoretical and experimental novel ISBT phenomenon in GaN HEMT is for potential ambient applications in the THz range.
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Conference papers on the topic "High Temperature Gate Bias - HTGB"

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Maiga, C. O., B. Tala-Ighil, H. Toutah, and B. Boudart. "Non-punch-through insulated gate bipolar transistors under high temperature gate bias and high temperature reverse bias stresses-hard-switching performances evolution." In 2005 IEEE 11th European Conference on Power Electronics and Applications. IEEE, 2005. http://dx.doi.org/10.1109/epe.2005.219370.

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Krishnan, Siddarth, Vijay Narayanan, Eduard Cartier, Dimitris Ioannou, Kai Zhao, Takashi Ando, Unoh Kwon, et al. "Bias temperature instability in High-κ/metal gate transistors - Gate stack scaling trends." In 2012 IEEE International Reliability Physics Symposium (IRPS). IEEE, 2012. http://dx.doi.org/10.1109/irps.2012.6241838.

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Ioannou, D. P., S. Mittl, and G. LaRosa. "Positive Bias Temperature Instability Effects in advanced High-k / Metal Gate NMOSFETs." In 2008 IEEE International Integrated Reliability Workshop Final Report (IRW). IEEE, 2008. http://dx.doi.org/10.1109/irws.2008.4796085.

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Ioannou, Dimitris P., Steve Mittl, and Giuseppe LaRosa. "Positive Bias Temperature Instability Effects in advanced High-k / Metal Gate NMOSFETs." In 2008 IEEE International Integrated Reliability Workshop Final Report (IRW). IEEE, 2008. http://dx.doi.org/10.1109/irws.2008.4796131.

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Sreenidhi, T., Amitava DasGupta, and Nandita DasGupta. "Temperature and bias dependent gate leakage in AlInN/GaN High Electron Mobility Transistor." In 2012 International Conference on Emerging Electronics (ICEE 2012). IEEE, 2012. http://dx.doi.org/10.1109/icemelec.2012.6636260.

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"CMOS and Interconnect Reliability -- Bias-Temperature Instability in SiON and High-k Gate Dielectrics." In 2006 International Electron Devices Meeting. IEEE, 2006. http://dx.doi.org/10.1109/iedm.2006.346771.

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Habersat, Daniel B., Aivars J. Lelis, and Ronald Green. "Towards a Robust Approach to Threshold Voltage Characterization and High Temperature Gate Bias Qualification." In 2020 IEEE International Reliability Physics Symposium (IRPS). IEEE, 2020. http://dx.doi.org/10.1109/irps45951.2020.9128227.

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Wong, King-Yuen, Y. S. Lin, C. W. Hsiung, G. P. Lansbergen, M. C. Lin, F. W. Yao, C. J. Yu, et al. "AlGaN/GaN MIS-HFET with improvement in high temperature gate bias stress-induced reliability." In 2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD). IEEE, 2014. http://dx.doi.org/10.1109/ispsd.2014.6855974.

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Maiga, C. O., B. Tala-Ighil, H. Toutah, and B. Boudart. "Behaviour of punch-through and non-punch-through insulated gate bipolar transistors under high temperature gate bias stress." In 2004 IEEE International Symposium on Industrial Electronics. IEEE, 2004. http://dx.doi.org/10.1109/isie.2004.1571956.

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O'Connor, Robert, Vincent S. Chang, Luigi Pantisano, Lars-Ake Ragnarsson, Marc Aoulaiche, Barry O'Sullivan, Christoph Adelmann, et al. "Anomalous positive-bias temperature instability of high-κ/metal gate nMOSFET devices with Dy2O3 capping." In 2008 IEEE International Reliability Physics Symposium (IRPS). IEEE, 2008. http://dx.doi.org/10.1109/relphy.2008.4558981.

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