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Relevant bibliographies by topics / High Temperature Gate Bias - HTGB

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Academic literature on the topic 'High Temperature Gate Bias - HTGB'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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Journal articles on the topic "High Temperature Gate Bias - HTGB"

1

Principato, Fabio, Giuseppe Allegra, Corrado Cappello, et al. "Investigation of the Impact of Neutron Irradiation on SiC Power MOSFETs Lifetime by Reliability Tests." Sensors 21, no. 16 (2021): 5627. http://dx.doi.org/10.3390/s21165627.

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High temperature reverse-bias (HTRB), High temperature gate-bias (HTGB) tests and electrical DC characterization were performed on planar-SiC power MOSFETs which survived to accelerated neutron irradiation tests carried out at ChipIr-ISIS (Didcot, UK) facility, with terrestrial neutrons. The neutron test campaigns on the SiC power MOSFETs (manufactered by ST) were conducted on the same wafer lot devices by STMicroelectronics and Airbus, with different neutron tester systems. HTGB and HTRB tests, which characterise gate-oxide integrity and junction robustness, show no difference between the non

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2

Lee, Kwangwon, Young Ho Seo, Taeseop Lee, et al. "Effect of Phosphorus Doped Poly Annealing on Threshold Voltage Stability and Thermal Oxide Reliability in 4H-SiC MOSFET." Materials Science Forum 1004 (July 2020): 554–58. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.554.

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We have investigated the effect of high temperature annealing of phosphorus doped poly on gate oxide integrity and device reliability. In NMOS capacitance analysis, unstable flat band voltage characteristics and lower oxide breakdown electric field were observed in wafers which received high temperature poly annealing at 1100 °C. Gate oxide integrity (GOI/Vramp) tests and time dependent dielectric breakdown (TDDB) tests were performed to evaluate wafer level reliability. Degraded GOI characteristics and poor gate oxide lifetime were obtained for the high temperature poly annealed condition. To

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3

Das, Mrinal K., Sarah K. Haney, Jim Richmond, Anthony Olmedo, Q. Jon Zhang, and Zoltan Ring. "SiC MOSFET Reliability Update." Materials Science Forum 717-720 (May 2012): 1073–76. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.1073.

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Significant advancement has been made in the gate oxide reliability of SiC MOS devices to enable the commercial release of Cree’s Z-FET™ product. This paper discusses the key reliability results from Time-Dependent-Dielectric-Breakdown (TDDB) and High Temperature Gate Bias (HTGB) measurements that indicate that the SiC MOSFETs can demonstrate excellent lifetime and stable operation in the field.

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4

van Brunt, Edward, Michael O’Loughlin, Al Burk, et al. "Industrial and Body Diode Qualification of Gen-III Medium Voltage SiC MOSFETs: Challenges and Solutions." Materials Science Forum 963 (July 2019): 805–10. http://dx.doi.org/10.4028/www.scientific.net/msf.963.805.

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In this work, we report the results of industrial qualification tests run on medium voltage SiC MOSFETs rated for 3.3 kV/40 A and 10 kV/15 A. The JEDEC JESD47J.01 standard was used as a guideline to conduct HTRB (High Temperature, Reverse Bias), HTGB (High Temperature, Gate Bias), and TDDB (Time Dependent Dielectric Breakdown) tests. No devices were found to have failed the qualification tests, and long oxide lifetime was projected for constant operation under positive bias. This paper also reports for the first time the results of qualification testing of the MOSFET body diode on a large popu

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5

Habersat, Daniel B., Aivars Lelis, and Ronald Green. "Influence of High-Temperature Bias Stress on Room-Temperature V_T Drift Measurements in SiC Power MOSFETs." Materials Science Forum 963 (July 2019): 757–62. http://dx.doi.org/10.4028/www.scientific.net/msf.963.757.

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Our results reinforce the notion of the need for an improved high-temperature gate bias (HTGB) test method — one which discourages the use of slow (greater than ~1 ms) threshold-voltage (VT) measurements at elevated temperatures and includes biased cool-down if room temperature measurements are performed, to ensure that any ephemeral effects during the high-temperature stress are observed. The paper presents a series of results on both state-of-the-art commercially-available devices as well as older vintage devices that exhibit enhanced charge-trapping effects. Although modern devices appear t

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6

Lichtenwalner, Daniel J., Shadi Sabri, Edward Van Brunt, et al. "Accelerated Testing of SiC Power Devices under High-Field Operating Conditions." Materials Science Forum 1004 (July 2020): 992–97. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.992.

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Power metal-oxide-semiconductor field-effect transistors (MOSFETs) experience conditions of high field during normal operation. During switching conditions, unexpected transient events may occur which force devices into avalanche or short circuit conditions. Moreover, silicon carbide devices typically experience higher fields in the gate oxide and drift regions than comparable Si devices due to channel and drift property differences. A summary of SiC MOSFET reliability and ruggedness test results are reported here. Reliability tests under high field conditions: positive-bias and negative-bias

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7

Cheng, Lin, P. Martin, Michael S. Mazzola, et al. "High-Temperature Static and Dynamic Reliability Study of 4H-SiC Vertical-Channel JFETs for High-Power System Applications." Materials Science Forum 600-603 (September 2008): 1051–54. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.1051.

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In this work we report the most recent high-temperature long-term reliability results of the 600 V/14 A, 4H-SiC vertical-channel junction field-effect transistors (VJFETs). Two groups (A and B) devices were subjected to different thermal and electrical stresses. One device (Group A) reached 12,000 hours of continuous switching without a single failure. Four devices in Group A were thermally stressed at 250 °C over 4,670 hours in air, for which standard deviation of the specific on-resistance (RONSP) in linear region at gate bias (VGS) of 3 V were < 4.1% throughout the entire duration time.

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8

Gendron-Hansen, Amaury, Changsoo Hong, Yi Fan Jiang, et al. "Commercialization of Highly Rugged 4H-SiC 3300 V Schottky Diodes and Power MOSFETs." Materials Science Forum 1004 (July 2020): 822–29. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.822.

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In this paper, we present a new family of 3300 V silicon carbide (SiC) Schottky barrier diodes (SBDs) and power MOSFETs. The main design requirements are discussed with an emphasis on the design rules to improve the long-term reliability. Basic static and dynamic performance demonstrates low conduction and switching losses. Long-term tests such as high-temperature reverse bias (HTRB) and body diode forward bias stress were performed to evaluate the devices’ reliability. An emission microscopy (EMMI) study was conducted to assess the quality of the gate oxide. Outstanding surge and avalanche ca

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9

Chowdhury, Sauvik, Levi Gant, Blake Powell, Kasturirangan Rangaswamy, and Kevin Matocha. "Reliability and Ruggedness of 1200V SiC Planar Gate MOSFETs Fabricated in a High Volume CMOS Foundry." Materials Science Forum 924 (June 2018): 697–702. http://dx.doi.org/10.4028/www.scientific.net/msf.924.697.

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This paper presents the performance, reliability and ruggedness characterization of 1200V, 80mΩ rated SiC planar gate MOSFETs, fabricated in a high volume, 150mm silicon CMOS foundry. The devices showed a specific on-resistance of 5.1 mΩ.cm2 at room temperature, increasing to 7.5 mΩ.cm2 at 175 °C. Total switching losses were less than 300μJ (VDD = 800V, ID = 20A). The devices showed excellent gate oxide reliability with VTH shifts under 0.2V for extended HTGB stress testing at 175 °C for up to 5500 hours (VGS = 25V) and 2500 hours (VGS = -10V). Ruggedness performance such as unclamped inductiv

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10

Yang, L., and A. Castellazzi. "High temperature gate-bias and reverse-bias tests on SiC MOSFETs." Microelectronics Reliability 53, no. 9-11 (2013): 1771–73. http://dx.doi.org/10.1016/j.microrel.2013.07.065.

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