Journal articles: 'High Temperature Gate Bias - HTGB'

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Principato, Fabio, Giuseppe Allegra, Corrado Cappello, Olivier Crepel, Nicola Nicosia, Salvatore D′Arrigo, Vincenzo Cantarella, et al. "Investigation of the Impact of Neutron Irradiation on SiC Power MOSFETs Lifetime by Reliability Tests." Sensors 21, no. 16 (August 20, 2021): 5627. http://dx.doi.org/10.3390/s21165627.

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High temperature reverse-bias (HTRB), High temperature gate-bias (HTGB) tests and electrical DC characterization were performed on planar-SiC power MOSFETs which survived to accelerated neutron irradiation tests carried out at ChipIr-ISIS (Didcot, UK) facility, with terrestrial neutrons. The neutron test campaigns on the SiC power MOSFETs (manufactered by ST) were conducted on the same wafer lot devices by STMicroelectronics and Airbus, with different neutron tester systems. HTGB and HTRB tests, which characterise gate-oxide integrity and junction robustness, show no difference between the non irradiated devices and those which survived to the neutron irradiation tests, with neutron fluence up to 2× 1011 (n/cm2). Electrical characterization performed pre and post-irradiation on different part number of power devices (Si, SiC MOSFETs and IGBTs) which survived to neutron irradiation tests does not show alteration of the data-sheet electrical parameters due to neutron interaction with the device.

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Lee, Kwangwon, Young Ho Seo, Taeseop Lee, Kyeong Seok Park, Martin Domeij, Fredrik Allerstam, and Thomas Neyer. "Effect of Phosphorus Doped Poly Annealing on Threshold Voltage Stability and Thermal Oxide Reliability in 4H-SiC MOSFET." Materials Science Forum 1004 (July 2020): 554–58. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.554.

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We have investigated the effect of high temperature annealing of phosphorus doped poly on gate oxide integrity and device reliability. In NMOS capacitance analysis, unstable flat band voltage characteristics and lower oxide breakdown electric field were observed in wafers which received high temperature poly annealing at 1100 °C. Gate oxide integrity (GOI/Vramp) tests and time dependent dielectric breakdown (TDDB) tests were performed to evaluate wafer level reliability. Degraded GOI characteristics and poor gate oxide lifetime were obtained for the high temperature poly annealed condition. To evaluate package level reliability, high temperature gate bias (HTGB) stress tests were conducted. Some samples failed in positive gate bias stress and more severe negative threshold voltage shift was observed in negative gate bias stress for the high temperature poly annealed condition.

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Das, Mrinal K., Sarah K. Haney, Jim Richmond, Anthony Olmedo, Q. Jon Zhang, and Zoltan Ring. "SiC MOSFET Reliability Update." Materials Science Forum 717-720 (May 2012): 1073–76. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.1073.

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Significant advancement has been made in the gate oxide reliability of SiC MOS devices to enable the commercial release of Cree’s Z-FET™ product. This paper discusses the key reliability results from Time-Dependent-Dielectric-Breakdown (TDDB) and High Temperature Gate Bias (HTGB) measurements that indicate that the SiC MOSFETs can demonstrate excellent lifetime and stable operation in the field.

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van Brunt, Edward, Michael O’Loughlin, Al Burk, Brett Hull, Sei Hyung Ryu, Jim Richmond, Yuri Khlebnikov, et al. "Industrial and Body Diode Qualification of Gen-III Medium Voltage SiC MOSFETs: Challenges and Solutions." Materials Science Forum 963 (July 2019): 805–10. http://dx.doi.org/10.4028/www.scientific.net/msf.963.805.

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In this work, we report the results of industrial qualification tests run on medium voltage SiC MOSFETs rated for 3.3 kV/40 A and 10 kV/15 A. The JEDEC JESD47J.01 standard was used as a guideline to conduct HTRB (High Temperature, Reverse Bias), HTGB (High Temperature, Gate Bias), and TDDB (Time Dependent Dielectric Breakdown) tests. No devices were found to have failed the qualification tests, and long oxide lifetime was projected for constant operation under positive bias. This paper also reports for the first time the results of qualification testing of the MOSFET body diode on a large population of medium voltage SiC MOSFETs. Constant current stress at a current equal to the device forward rating was applied for 1000 hours. No degradation of any device parameter was observed for 3 lots of devices at both the 3.3 kV and 10 kV voltage rating.

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Habersat, Daniel B., Aivars Lelis, and Ronald Green. "Influence of High-Temperature Bias Stress on Room-Temperature V_T Drift Measurements in SiC Power MOSFETs." Materials Science Forum 963 (July 2019): 757–62. http://dx.doi.org/10.4028/www.scientific.net/msf.963.757.

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Our results reinforce the notion of the need for an improved high-temperature gate bias (HTGB) test method — one which discourages the use of slow (greater than ~1 ms) threshold-voltage (VT) measurements at elevated temperatures and includes biased cool-down if room temperature measurements are performed, to ensure that any ephemeral effects during the high-temperature stress are observed. The paper presents a series of results on both state-of-the-art commercially-available devices as well as older vintage devices that exhibit enhanced charge-trapping effects. Although modern devices appear to be robust, it is important to ensure that any new devices released commercially, especially by new vendors, are properly evaluated for VT stability.

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Lichtenwalner, Daniel J., Shadi Sabri, Edward Van Brunt, Brett Hull, Sei Hyung Ryu, Philipp Steinmann, Amy Romero, et al. "Accelerated Testing of SiC Power Devices under High-Field Operating Conditions." Materials Science Forum 1004 (July 2020): 992–97. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.992.

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Power metal-oxide-semiconductor field-effect transistors (MOSFETs) experience conditions of high field during normal operation. During switching conditions, unexpected transient events may occur which force devices into avalanche or short circuit conditions. Moreover, silicon carbide devices typically experience higher fields in the gate oxide and drift regions than comparable Si devices due to channel and drift property differences. A summary of SiC MOSFET reliability and ruggedness test results are reported here. Reliability tests under high field conditions: positive-bias and negative-bias temperature instability (PBTI, NBTI) to examine threshold stability; time-dependent dielectric breakdown (TDDB) for gate oxide lifetime extrapolation; high-temperature reverse bias (HTRB); and HTRB testing under high neutron flux to determine terrestrial neutron single-event burnout (SEB) rates. High-power ruggedness evaluation is presented for SiC MOSFETs under forced avalanche conditions (unclamped inductive switching (UIS)) and under short-circuit operation to bound device safe operating areas. Overall results demonstrate the intrinsic reliability of SiC MOSFETs.

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Cheng, Lin, P. Martin, Michael S. Mazzola, David C. Sheridan, R. L. Kelly, Volodymyr Bondarenko, S. Morrison, et al. "High-Temperature Static and Dynamic Reliability Study of 4H-SiC Vertical-Channel JFETs for High-Power System Applications." Materials Science Forum 600-603 (September 2008): 1051–54. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.1051.

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In this work we report the most recent high-temperature long-term reliability results of the 600 V/14 A, 4H-SiC vertical-channel junction field-effect transistors (VJFETs). Two groups (A and B) devices were subjected to different thermal and electrical stresses. One device (Group A) reached 12,000 hours of continuous switching without a single failure. Four devices in Group A were thermally stressed at 250 °C over 4,670 hours in air, for which standard deviation of the specific on-resistance (RONSP) in linear region at gate bias (VGS) of 3 V were < 4.1% throughout the entire duration time. The off-state characteristics were evaluated by high temperature reverse bias (HTRB) tests. Three devices (Group A) were biased at 50% rated BVDS at 250 °C for 2,278 hours. A higher reverse bias at 80 % rated BVDS was then applied to 14 devices (group B) at 200 °C for 1,000 hours. Variations of the leakage current were negligible throughout the entire HTRB test for all tested devices.

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Gendron-Hansen, Amaury, Changsoo Hong, Yi Fan Jiang, John May, Dumitru Sdrulla, Bruce Odekirk, and Avinash S. Kashyap. "Commercialization of Highly Rugged 4H-SiC 3300 V Schottky Diodes and Power MOSFETs." Materials Science Forum 1004 (July 2020): 822–29. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.822.

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In this paper, we present a new family of 3300 V silicon carbide (SiC) Schottky barrier diodes (SBDs) and power MOSFETs. The main design requirements are discussed with an emphasis on the design rules to improve the long-term reliability. Basic static and dynamic performance demonstrates low conduction and switching losses. Long-term tests such as high-temperature reverse bias (HTRB) and body diode forward bias stress were performed to evaluate the devices’ reliability. An emission microscopy (EMMI) study was conducted to assess the quality of the gate oxide. Outstanding surge and avalanche capabilities are reported with UIS ruggedness of 11.4 and 20.8 J.cm-2 for SBDs and MOSFETs, respectively.

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Chowdhury, Sauvik, Levi Gant, Blake Powell, Kasturirangan Rangaswamy, and Kevin Matocha. "Reliability and Ruggedness of 1200V SiC Planar Gate MOSFETs Fabricated in a High Volume CMOS Foundry." Materials Science Forum 924 (June 2018): 697–702. http://dx.doi.org/10.4028/www.scientific.net/msf.924.697.

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This paper presents the performance, reliability and ruggedness characterization of 1200V, 80mΩ rated SiC planar gate MOSFETs, fabricated in a high volume, 150mm silicon CMOS foundry. The devices showed a specific on-resistance of 5.1 mΩ.cm2 at room temperature, increasing to 7.5 mΩ.cm2 at 175 °C. Total switching losses were less than 300μJ (VDD = 800V, ID = 20A). The devices showed excellent gate oxide reliability with VTH shifts under 0.2V for extended HTGB stress testing at 175 °C for up to 5500 hours (VGS = 25V) and 2500 hours (VGS = -10V). Ruggedness performance such as unclamped inductive load switching and short circuit capability are also discussed.

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Yang, L., and A. Castellazzi. "High temperature gate-bias and reverse-bias tests on SiC MOSFETs." Microelectronics Reliability 53, no. 9-11 (September 2013): 1771–73. http://dx.doi.org/10.1016/j.microrel.2013.07.065.

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Franchi, Jimmy, Martin Domeij, and Kwang Won Lee. "1200 V SiC MOSFETs with Stable V_TH under High Temperature Gate Bias Stress." Materials Science Forum 963 (July 2019): 753–56. http://dx.doi.org/10.4028/www.scientific.net/msf.963.753.

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In this work, threshold voltage drift of SiC MOSFET devices have been investigated. The drift during positive gate bias application was found to be moderate for three commercial grade devices, while the results for negative gate bias application differ widely. We demonstrate ON Semiconductor SiC MOSFETs with threshold voltage stability under both positive and negative bias stress due to an improved gate oxide process, and the influence of high field stress on the threshold voltage is additionally discussed. A long term transient high temperature gate bias stress is shown to cause a slight positive shift in the threshold voltage of the ON Semiconductor devices, while the on resistance remains constant.

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Maïga, C. O., H. Toutah, B. Tala-Ighil, and B. Boudart. "Trench insulated gate bipolar transistors submitted to high temperature bias stress." Microelectronics Reliability 45, no. 9-11 (September 2005): 1728–31. http://dx.doi.org/10.1016/j.microrel.2005.07.098.

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CHOWDHURY, N. A., D. MISRA, and N. RAHIM. "NEGATIVE BIAS TEMPERATURE INSTABILITY IN TIN/HF-SILICATE BASED GATE STACKS." International Journal of High Speed Electronics and Systems 17, no. 01 (March 2007): 129–41. http://dx.doi.org/10.1142/s0129156407004345.

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This work studies the effects of negative bias temperature instability (NBTI) on p-channel MOSFETS with TiN/HfSi x O y (20% SiO 2 based high-κ gate stacks under different gate bias and elevated temperature conditions. For low bias conditions, threshold voltage shift (ΔVT) is most probably due to the mixed degradation within the bulk high-κ. For moderately high bias conditions, H-species dissociation in the presence of holes and subsequent diffusion may be initially responsible for interface state and positively charged bulk trap generation. Initial time, temperature and oxide electric field dependence of ΔVT in our devices shows an excellent match with that of SiO 2 based devices, which is explained by reaction-diffusion (R-D) model of NBTI. Under high bias condition at elevated temperatures, due to higher Si - H bond-annealing/bond-breaking ratio, the experimentally observed absence of the impact ionization induced hot holes at the interfacial layer (IL)/ Si interface probably limits the interface state generation and ΔVT as they quickly reach saturation.

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Kaplar, R. J., D. R. Hughart, S. Atcitty, J. D. Flicker, S. DasGupta, and M. J. Marinella. "Performance and Reliability Characterization of 1200 V Silicon Carbide Power MOSFETs at High Temperatures." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, HITEN (January 1, 2013): 000275–80. http://dx.doi.org/10.4071/hiten-wp11.

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Commercially available, 1200 V SiC power MOSFETs have been characterized under bias-temperature stress conditions. Two generations of devices from a single manufacturer were tested. For the first-generation MOSFETs, both plastic- and metal-packaged devices were evaluated, whereas for the second-generation MOSFETs, only plastic-packaged devices were tested. Threshold voltage was observed to decrease with increasing temperature in the absence of gate bias stress, as expected. Drain leakage current increased with increasing temperature above the rated temperature of 125°C for first-generation plastic-packaged parts, with the leakage ~10× higher for the plastic-packaged parts compared to the metal-packaged parts. A negative gate voltage was shown to reduce drain leakage current for the metal-packaged parts only, suggesting a parasitic leakage path associated with the plastic packaging. The threshold voltage shift ΔVT was minimal for T < 125°C. ΔVT increased with increasing temperature above 125°C, and was larger for negative gate voltage bias stress, suggesting that the oxide is more sensitive to trapping of holes than trapping of electrons. ΔVT was insensitive to the type of package. The second-generation SiC MOSFET showed significantly less susceptibility to bias temperature stress, especially for negative gate voltage, indicating improvement in device design and/or processing in the second-generation MOSFET. Switching gate stress showed complex behavior, with a rapid initial shift in VT followed by a much slower shift. Initial testing indicates a strong dependence on duty cycle and possible influence of self-heating. More detailed study of reliability under switching conditions is needed.

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Gonzalez, Jose Ortiz, Olayiwola Alatise, and Philip A. Mawby. "Novel Method for Evaluation of Negative Bias Temperature Instability of SiC MOSFETs." Materials Science Forum 963 (July 2019): 749–52. http://dx.doi.org/10.4028/www.scientific.net/msf.963.749.

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The material properties of SiC make SiC power devices a superior alternative to the conventional Si power devices. However, the reliability of the gate oxide has been a major concern, limiting the adoption of SiC power MOSFETs as the power semiconductor of choice in applications which demand a high reliability. The threshold voltage (VTH) shift caused by Bias Temperature Instability (BTI) has focused the attention of different researchers, with multiple publications on this topic. This paper presents a novel method for evaluating the threshold voltage shift due to negative gate bias and its recovery when the gate bias stress is removed. This method could enable gate oxide reliability assessment techniques and contribute to new qualification methods.

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Pons-Flores, C. A., I. Hernández, I. Garduno, I. Mejía, and M. Estrada. "Bias Stress Effects in Low Temperature Amorphous Hf-In-ZnO TFTs Using RF-sputtering HfO2 as High-k Gate Dielectric." Journal of Integrated Circuits and Systems 12, no. 1 (December 28, 2017): 18–23. http://dx.doi.org/10.29292/jics.v12i1.446.

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In this work we analyze the electrical performance, contact resistance and the effects of positive and negative gatebias stress of Hf-In-ZnO/HfO2 thin film transistors. Devices were fabricated using RF-magnetron sputtering at room temperature and fully patterned, with operation voltage below 6 V. Devices with drain-currents up to 2x10-6 A and threshold voltages of ~2 V were analyzed under negative and positive gate bias stress. Devices under negative gate-bias stress showed a slightly threshold voltage shift due to the transistor channel is depleted of electrons at the channel/dielectric interface. Devices under positive gate-bias stress, showed threshold voltage shifts in the negative direction due to the reversible charge/discharge effect of the electrons in pre-existing high-k HfO2 bulk traps. Positive gate-bias stress does not cause any degeneration, since stressed devices tend to recover after 5 mins.

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Suliman, S. A., O. O. Awadelkarim, J. Hao, and M. Rioux. "High-Temperature Reverse-Bias Stressing of Thin Gate Oxides in Power Transistors." ECS Transactions 64, no. 8 (August 9, 2014): 45–52. http://dx.doi.org/10.1149/06408.0045ecst.

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Weng, Wu-Te, Yao-Jen Lee, Horng-Chih Lin, and Tiao-Yuan Huang. "Plasma-Induced Damage on the Reliability of Hf-Based High-k/Dual Metal-Gates Complementary Metal Oxide Semiconductor Technology." International Journal of Plasma Science and Engineering 2009 (December 14, 2009): 1–10. http://dx.doi.org/10.1155/2009/308949.

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This study examines the effects of plasma-induced damage (PID) on Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO2/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for high-k/metal-gate CMOS technology.

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Wang, Mu Chun, and Hsin Chia Yang. "Instability Effect on CLC nTFTs with Positive-Bias Temperature Stress." Advanced Materials Research 314-316 (August 2011): 1918–21. http://dx.doi.org/10.4028/www.scientific.net/amr.314-316.1918.

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The positive-bias temperature instability (PBTI) test is one of effective reliability evaluation tests in negative-channel metal-oxide-semiconductor field-effect transistor (nMOSFET) to expose the bonding interface between channel surface and gate dielectric and the integrity of gate dielectric. Adopting this test metrology in thin-film transistor (TFT) on glass substrate to reveal the previous concerns is still suitable. Using this good methodology in continuous-wave (CW) green laser-crystallization (CLC) poly-Si TFT, demonstrating a greatly effective mobility 530 cm^2/V-s, is necessary to interpret the defect generation and the device degradation under high gate-voltage stress and temperature impact, 25 oC to 125 oC. Because the channel surface of the CLC poly-Si TFT was not strictly smooth, the micro roughness in this stress caused more generation of interface states. The grain-boundary trap states in poly-crystalline channel, additionally, were generated after stress.

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Tarr, N. G., K. Shortt, Yanbin Wang, and I. Thomson. "A sensitive, temperature-compensated, zero-bias floating gate MOSFET dosimeter." IEEE Transactions on Nuclear Science 51, no. 3 (June 2004): 1277–82. http://dx.doi.org/10.1109/tns.2004.829372.

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Cheng, Lin, Igor Sankin, Volodymyr Bondarenko, Michael S. Mazzola, James D. Scofield, David C. Sheridan, P. Martin, Janna R. B. Casady, and Jeff B. Casady. "High-Temperature Operation of 50 A (1600 A/cm²), 600 V 4H-SiC Vertical-Channel JFETs for High-Power Applications." Materials Science Forum 600-603 (September 2008): 1055–58. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.1055.

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In this work we have demonstrated the high-temperature operations of 600 V/50 A 4HSiC vertical-channel junction field-effect transistors (VJFETs) with an active area of 3 mm2. Specific-on resistance (RONSP) in the linear region of a single die is less than 2.6 mW.cm2 while the drain-source current is over 50 A under a gate bias (VGS) of 3 V. A reverse blocking gain of 54 is obtained at gate bias ranging from -13 V to -23 V and drain-source leakage current (IRDS) of 200 μA. To demonstrate the use of SiC VJFETs for high-power applications, eight 3 mm2 SiC VJFETs are bonded in a high current 600-V module. RONSP in the linear region of these eight-paralleled SiC VJFETs is 2.8 mW.cm2 at room temperature and increased to 5.35 mW.cm2 at an ambient temperature of 175 °C in air, corresponding to a shift of 0.61%/°C from room temperature to 175 °C. Meanwhile, the forward current is over 360 A at room temperature and reduces to 188 A at 175 °C at drain-source bias (VDS) of 5.25 V and VGS of 3 V.

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Gong, Xiao, Bin Liu, and Yee-Chia Yeo. "Gate Stack Reliability of MOSFETs With High-Mobility Channel Materials: Bias Temperature Instability." IEEE Transactions on Device and Materials Reliability 13, no. 4 (December 2013): 524–33. http://dx.doi.org/10.1109/tdmr.2013.2277935.

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DIDUCK, QUENTIN, HIROSHI IRIE, and MARTIN MARGALA. "A ROOM TEMPERATURE BALLISTIC DEFLECTION TRANSISTOR FOR HIGH PERFORMANCE APPLICATIONS." International Journal of High Speed Electronics and Systems 19, no. 01 (March 2009): 23–31. http://dx.doi.org/10.1142/s0129156409006060.

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The Ballistic Deflection Transistor (BDT) is a novel device that is based upon an electron steering and a ballistic deflection effect. Composed of an InGaAs - InAlAs heterostructure on an InP substrate, this material system provides a large mean free path and high mobility to support ballistic transport at room temperature. The planar nature of the device enables a two step lithography process, as well, implies a very low capacitance design. This transistor is unique in that no doping junction or barrier structure is employed. Rather, the transistor utilizes a two-dimensional electron gas (2DEG) to achieve ballistic electron transport in a gated microstructure, combined with asymmetric geometrical deflection. Motivated by reduced transit times, the structure can be operated such that current never stops flowing, but rather is only directed toward one of two output drain terminals. The BDT is unique in that it possesses both a positive and negative transconductance region. Experimental measurements have indicated that the transconductance of the device increases with applied drain-source voltage. DC measurements of prototype devices have verified small signal voltage gains of over 150, with transconductance values from 45 to 130 mS/mm depending upon geometry and bias. Gate-channel separation is currently 80nm, and allows for higher transconductance through scaling. The six terminal device enables a normally differential mode of operation, and provides two drain outputs. These outputs, depending on gate bias, are either complementary or non-complementary. This facilitates a wide variety of circuit design techniques. Given the ultralow capacitive design, initial estimates of ft, for the device fabricated with a 430nm gate width, are over a THz.

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Cheng, Lin, Michael S. Mazzola, and David C. Sheridan. "High-Temperature Reliability Assessment of 4H-SiC Vertical-Channel JFET Including Forward Bias Stress." Materials Science Forum 615-617 (March 2009): 723–26. http://dx.doi.org/10.4028/www.scientific.net/msf.615-617.723.

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In this work, we report the most recent reliability results of the 1200-V SiC vertical-channel JFETs (VJFETs) under reverse and forward bias of the gate-source diode at temperatures up to 200 °C. The preliminary results indicate that continuous forward bias stress of the gate-source diode at 200 °C for 112 hours produced no observable change in the forward conduction or transient or reverse blocking characteristics of the vertical-channel JFET. This preliminary result suggests that devices based on this structure, such as the enhancement-mode (normally off) SiC VJFET, may not be effected by the recombination enhanced defect creation process and the associated increase in on-resistance, related to body-diode conduction in the SiC DMOSFET and the SiC lateral-channel depletion-mode JFET. Since the vertical-channel JFET has no body diode, no degradation is possible from the reverse conduction mode of operation.

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Ťapajna, Milan. "Current Understanding of Bias-Temperature Instabilities in GaN MIS Transistors for Power Switching Applications." Crystals 10, no. 12 (December 18, 2020): 1153. http://dx.doi.org/10.3390/cryst10121153.

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GaN-based high-electron mobility transistors (HEMTs) have brought unprecedented performance in terms of power, frequency, and efficiency. Application of metal-insulator-semiconductor (MIS) gate structure has enabled further development of these devices by improving the gate leakage characteristics, gate controllability, and stability, and offered several approaches to achieve E-mode operation desired for switching devices. Yet, bias-temperature instabilities (BTI) in GaN MIS transistors represent one of the major concerns. This paper reviews BTI in D- and E-mode GaN MISHEMTs and fully recess-gate E-mode devices (MISFETs). Special attention is given to discussion of existing models describing the defects distribution in the GaN-based MIS gate structures as well as related trapping mechanisms responsible for threshold voltage instabilities. Selected technological approaches for improving the dielectric/III-N interfaces and techniques for BTI investigation in GaN MISHEMTs and MISFETs are also outlined.

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Matocha, Kevin, Sujit Banerjee, and Kiran Chatty. "Advanced SiC Power MOSFETs Manufactured on 150mm SiC Wafers." Materials Science Forum 858 (May 2016): 803–6. http://dx.doi.org/10.4028/www.scientific.net/msf.858.803.

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An advanced silicon carbide power MOSFET process was developed and implemented on a high-volume 150mm silicon production line. SiC power MOSFETs fabricated on this 150mm silicon production line were demonstrated with blocking voltage of 1700V with VGS=0V. These SiC MOSFETs have a specific on-resistance as low as 3.1 mΩ-cm2 at room temperature, increasing to 6.7 mΩ-cm2 at 175°C. Devices were packaged in TO-247 package and measured to have on-resistance of 45 mΩ with VGS=20V at room temperature. Clamped inductive switching characterization of these SiC MOSFETs shows turn-off losses as low as 110 uJ (700V, 19.5A). The high-temperature gate bias stability was characterized at positive (+20) and negative gate bias (-10V) at 175°C. After 750 hours of gate stress at a gate bias of VGS=+20V and 175°C, we observe less than a 250mV shift in the threshold voltage. After 750 hours of stress at VGS=-10V and 175°C, we characterize a threshold voltage shift less than 100mV. This shows promise for high-volume production of reliable SiC MOSFETs on 150mm wafers.

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O’Connor, Robert, Vincent S. Chang, Luigi Pantisano, Lars-Åke Ragnarsson, Marc Aoulaiche, Barry O’Sullivan, and Guido Groeseneken. "Anomalous positive-bias temperature instability of high-κ/metal gate devices with Dy2O3 capping." Applied Physics Letters 93, no. 5 (August 4, 2008): 053506. http://dx.doi.org/10.1063/1.2967454.

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Kerber, A., S. A. Krishnan, and E. A. Cartier. "Voltage Ramp Stress for Bias Temperature Instability Testing of Metal-Gate/High- $k$ Stacks." IEEE Electron Device Letters 30, no. 12 (December 2009): 1347–49. http://dx.doi.org/10.1109/led.2009.2032790.

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Kaczer, B., A. Veloso, Ph J. Roussel, T. Grasser, and G. Groeseneken. "Investigation of Bias-Temperature Instability in work-function-tuned high-k/metal-gate stacks." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 27, no. 1 (2009): 459. http://dx.doi.org/10.1116/1.3054352.

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Asaba, Shunsuke, Tatsuo Schimizu, Yukio Nakabayashi, Shigeto Fukatsu, Toshihide Ito, and Ryosuke Iijima. "Novel Gate Insulator Process by Nitrogen Annealing for Si-Face SiC MOSFET with High-Mobility and High-Reliability." Materials Science Forum 924 (June 2018): 457–60. http://dx.doi.org/10.4028/www.scientific.net/msf.924.457.

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The gate insulator process for SiC-MOSFET was examined and high-quality interface was realized by employing the pre-annealing process before high-temperature N2 annealing. The pre-annealing evidently activated the interface to introduce nitrogen, and then field-effect mobility exceeded 50 cm2/Vs. The fabricated sample also demonstrated superior bias temperature instability (BTI) and excellent breakdown electric field of 11.7 MV/cm.

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Franco, J., B. Kaczer, A. Vais, A. Alian, H. Arimura, V. Putcha, S. Sioncke, et al. "Bias Temperature Instability (BTI) in high-mobility channel devices with high-k dielectric stacks: SiGe, Ge, and InGaAs." MRS Advances 1, no. 49 (2016): 3329–40. http://dx.doi.org/10.1557/adv.2016.387.

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ABSTRACTWe present a review of our recent studies of Bias Temperature Instability (BTI) in Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) fabricated with different material systems, highlighting the reliability opportunities and challenges of each novel device family. We discuss first the intrinsic reliability improvement offered by SiGe and Gep-channel technologies, if a Si cap is used to passivate the channel, in order to fabricate a standard SiO2/HfO2gate stack. We focus on SiGe gate stack optimizations for maximum BTI reliability, and on a simple physics-based model able to reproduce the experimental trends. This model framework is then used to understand the suboptimal BTI reliability and excessive time-dependent variability induced by oxide defect charging in different high-mobility channel gate stacks, such as Ge/GeOx/high-k and InGaAs/high-k. Finally we discuss how to pursue a reduction of charge trapping in alternative material systems in order to boost the device reliability and minimize time-dependent variability.

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32

Martino, Márcio D. V., Felipe S. Neves, Paula Ghedini Der Agopian, João Antonio Martino, Rita Rooyackers, and Cor Claeys. "Nanowire Tunnel Field Effect Transistors at High Temperature." Journal of Integrated Circuits and Systems 8, no. 2 (December 28, 2013): 110–15. http://dx.doi.org/10.29292/jics.v8i2.381.

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The aim of this work is to study how the performance of nanowire tunnel field effect transistors (TFETs) is influenced by temperature variation. First of all, simulated energy band diagrams were presented to justify its fundamental working principle and this analysis was compared to experimental data obtained for temperature ranging from 300 to 420 K. This methodology was performed for different nanowire diameters and bias conditions, leading to a deep investigation of parameters such as the ratio of on-state and off-state current (ION/IOFF) and the subthreshold slope (S). Three different transport mechanisms (band-to-band tunneling, Shockley-Read-Hall generation/recombination and trap-assisted tunneling) were highlighted to explain the temperature influence on the drain current. As the final step, subthreshold slope values for each configuration were compared to the room temperature. Therefore, it was observed that larger nanowire diameters and lower temperatures tended to increase ION/IOFF ratio. Meanwhile, it was clear that band-to-band tunneling prevailed for higher gate voltage bias, resulting in a much slighter temperature effect on the drain current.

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33

Gao, Qingguo, Chongfu Zhang, Ping Liu, Yunfeng Hu, Kaiqiang Yang, ZiChuan Yi, Liming Liu, et al. "Effect of Back-Gate Voltage on the High-Frequency Performance of Dual-Gate MoS2 Transistors." Nanomaterials 11, no. 6 (June 17, 2021): 1594. http://dx.doi.org/10.3390/nano11061594.

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As an atomically thin semiconductor, 2D molybdenum disulfide (MoS2) has demonstrated great potential in realizing next-generation logic circuits, radio-frequency (RF) devices and flexible electronics. Although various methods have been performed to improve the high-frequency characteristics of MoS2 RF transistors, the impact of the back-gate bias on dual-gate MoS2 RF transistors is still unexplored. In this work, we study the effect of back-gate control on the static and RF performance metrics of MoS2 high-frequency transistors. By using high-quality chemical vapor deposited bilayer MoS2 as channel material, high-performance top-gate transistors with on/off ratio of 107 and on-current up to 179 μA/μm at room temperature were realized. With the back-gate modulation, the source and drain contact resistances decrease to 1.99 kΩ∙μm at Vbg = 3 V, and the corresponding on-current increases to 278 μA/μm. Furthermore, both cut-off frequency and maximum oscillation frequency improves as the back-gate voltage increases to 3 V. In addition, a maximum intrinsic fmax of 29.7 GHz was achieved, which is as high as 2.1 times the fmax without the back-gate bias. This work provides significant insights into the influence of back-gate voltage on MoS2 RF transistors and presents the potential of dual-gate MoS2 RF transistors for future high-frequency applications.

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34

Mohapatra, Sushanta, Kumar Pradhan, and Prasanna Sahu. "Resolving the bias point for wide range of temperature applications in High-k/Metal Gate nanoscale DG-MOSFET." Facta universitatis - series: Electronics and Energetics 27, no. 4 (2014): 613–19. http://dx.doi.org/10.2298/fuee1404613m.

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This article investigates the Zero-Temperature-Coefficient (ZTC) bias point and its associated performance metrics of a High-k Metal Gate (HKMG) DG-MOSFET in nanoscale. The ZTC bias point is defined as the point at which the device parameters are independent of temperature. The discussion includes sub threshold slope (SS), drain induced barrier lowering (DIBL), on-off current ratio (Ion/Ioff), transconductance (gm), output conductance (gd) and intrinsic gain (AV). From the results, it is confirmed that there are two different ZTC bias points, one for IDS (ZTCIDS) and the other for gm (ZTCgm). The points are obtained as: ZTCIDS=0.552 V and ZTCgm =0.410 V, which will open important opportunities in analog circuit design for wide range of temperature applications.

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35

Silva, Vanessa Cristina Pereira da, Gilson Wirth, Joao Antonio Martino, and Paula Ghedini Der Agopian. "Analysis of the Negative-Bias-Temperature-Instability on Omega-Gate Silicon Nanowire SOI MOSFETs with Different Dimensions." Journal of Integrated Circuits and Systems 15, no. 2 (July 31, 2020): 1–5. http://dx.doi.org/10.29292/jics.v15i2.126.

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This work presents an experimental andThis work presents an experimental and simulated analysis of the Negative-Bias-Temperature-Instability (NBTI) on omega-gate nanowire (NW) pMOSFETS transistors, focusing on the influence of channel length and width, since it is an important reliability parameter for advanced technology nodes. To better understand the obtained results of NBTI effect in NW, the 3D-numerical simulations were performed. The results shows a high NBTI in NW (ΔVT≈200-300mV – for WNW=10nm) due to the higher gate oxide electric field accelerating the NBTI effect providing a higher degradation. simulated analysis of the Negative-Bias-Temperature-Instability (NBTI) on omega-gate nanowire (NW) pMOSFETS transistors, focusing on the influence of channel length and width, since it is an important reliability parameter for advanced technology nodes. To better understand the obtained results of NBTI effect in NW, the 3D-numerical simulations were performed. The results shows a high NBTI in NW (ΔVT≈200-300mV – for WNW=10nm) due to the higher gate oxide electric field accelerating the NBTI effect providing a higher degradation.

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36

T, Sreenidhi, A. Azizur Rahman, Arnab Bhattacharya, Amitava DasGupta, and Nandita DasGupta. "Reduction in Gate Leakage Current of AlGaN/GaN HEMT by Rapid Thermal Oxidation." MRS Proceedings 1635 (2014): 3–8. http://dx.doi.org/10.1557/opl.2014.203.

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ABSTRACTRapid Thermal Oxidation (RTO) of AlGaN barrier has been employed to reduce the gate leakage current in AlGaN/GaN High Electron Mobility Transistors. Current Voltage (I – V) and Capacitance Voltage (C – V) characteristics of Schottky Barrier diodes and Metal Oxide Semiconductor diodes are compared. At room temperature, reduction in gate leakage current over an order of magnitude in reverse bias and four orders of magnitude in forward bias is achieved upon oxidation. While the gate current reduces upon RTO, gate capacitance does not change indicating gate control over the channel is not compromised. I – V and C – V characterization have been carried out at different temperatures to get more insight into the device operation.

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Liu, Ao, Song Bai, Run Hua Huang, Tong Tong Yang, and Hao Liu. "Research on Threshold Voltage Instability in SiC MOSFET Devices with Precision Measurement." Materials Science Forum 954 (May 2019): 133–38. http://dx.doi.org/10.4028/www.scientific.net/msf.954.133.

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The mechanism of threshold voltage shift was studied. It is believed that the instability in threshold voltage during gate bias stress is due to capture of electrons by the SiC/gate dielectric interface traps and the gate dielectric near interface traps. New experimental platform was designed and built successfully. When positive stress or negative stress is applied to the gate, the change of threshold voltage occur immediately. After stress removal, the recovery of the threshold voltage occur soon. The change and recovery of threshold voltage are very sensitive to time. In order to get accurate threshold voltage drift data after high-temperature gate bias experiment, test of threshold voltage must be carried out immediately after the experiment.

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38

Ren, Shangqing, Bo Tang, Hao Xu, Weichun Luo, Zhaoyun Tang, Yefeng Xu, Jing Xu, et al. "Characterization of positive bias temperature instability of NMOSFET with high-k/metal gate last process." Journal of Semiconductors 36, no. 1 (January 2015): 014007. http://dx.doi.org/10.1088/1674-4926/36/1/014007.

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Liao, Miao, and Zhenghao Gan. "New insight on negative bias temperature instability degradation with drain bias of 28nm High-K Metal Gate p-MOSFET devices." Microelectronics Reliability 54, no. 11 (November 2014): 2378–82. http://dx.doi.org/10.1016/j.microrel.2014.05.010.

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Park, Youngseo, Jiyeon Ma, Geonwook Yoo, and Junseok Heo. "Interface Trap-Induced Temperature Dependent Hysteresis and Mobility in β-Ga2O3 Field-Effect Transistors." Nanomaterials 11, no. 2 (February 16, 2021): 494. http://dx.doi.org/10.3390/nano11020494.

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Interface traps between a gate insulator and beta-gallium oxide (β-Ga2O3) channel are extensively studied because of the interface trap charge-induced instability and hysteresis. In this work, their effects on mobility degradation at low temperature and hysteresis at high temperature are investigated by characterizing electrical properties of the device in a temperature range of 20–300 K. As acceptor-like traps at the interface are frozen below 230 K, the hysteresis becomes negligible but simultaneously the channel mobility significantly degrades because the inactive neutral traps allow additional collisions of electrons at the interface. This is confirmed by the fact that a gate bias adversely affects the channel mobility. An activation energy of such traps is estimated as 170 meV. The activated trap charges’ trapping and de-trapping processes in response to the gate pulse bias reveal that the time constants for the slow and fast processes decrease due to additionally activated traps as the temperature increases.

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41

Nakata, Shuhei, and Shota Tanaka. "Temperature Dependence of dV/dt Impact on the SiC-MOSFET." Materials Science Forum 963 (July 2019): 596–99. http://dx.doi.org/10.4028/www.scientific.net/msf.963.596.

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Recentlly, high speed switching circuits using SiC power device have been developed for reduction of switching loss and downsizing of electric products. The high speed switching leads to the rapid changing of the drain voltage (dV/dt) during the switching period. This paper reports the effects of the dV/dt impact on the self-turn-on and the characteristics of SiC-MOSFET, especially the temperature dependence. The results shows that the gate bias voltage to suppress the self-turn-on is negatively correlated with the temperature. And it is also found that the dV/dt impact breaks down the gate source insulation and the dV/dt value to the breakdown is positively correlated with the temperature.

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42

Pala, N., R. Gaska, M. Shur, J. W Yang, and M. Asif Khan. "Low-Frequency Noise in SiO2 /AlGaN/GaN Heterostructures on SiC and Sapphire Substrates." MRS Internet Journal of Nitride Semiconductor Research 5, S1 (2000): 612–18. http://dx.doi.org/10.1557/s109257830000483x.

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The low-frequency noise in GaN-based Metal-Oxide-Semiconductor Heterostructure Field Effect Transistors (MOS-HFETs) and HFETs on sapphire and n-SiC substrates were studied. Hooge parameter at zero gate bias was calculated about 8 × 10−4 for both types of the devices. The AlGaN/GaN MOS-HFETs exhibited extremely low gate leakage current and much lower noise at both positive and negative gate biases. These features demonstrate the high quality of the SiO2/AlGaN heterointerface and feasibility of this technology for high-power microwave transmitter and high-power, high-temperature switches.

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43

Sveinbjörnsson, Einar Ö., G. Gudjónsson, Fredrik Allerstam, H. Ö. Ólafsson, Per Åke Nilsson, Herbert Zirath, T. Rödle, and R. Jos. "High Channel Mobility 4H-SiC MOSFETs." Materials Science Forum 527-529 (October 2006): 961–66. http://dx.doi.org/10.4028/www.scientific.net/msf.527-529.961.

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We report investigations of MOS and MOSFET devices using a gate oxide grown in the presence of sintered alumina. In contrast to conventionally grown dry or wet oxides these oxides contain orders of magnitude lower density of near-interface traps at the SiO2/SiC interface. The reduction of interface traps is correlated with enhanced oxidation rate. The absence of near-interface traps makes possible fabrication of Si face 4H-SiC MOSFETs with peak field effect mobility of about 150 cm2/Vs. A clear correlation is observed between the field effect mobility in n-channel MOSFETs and the density of interface states near the SiC conduction band edge in n-type MOS capacitors. Stable operation of such normally-off 4H-SiC MOSFET transistors is observed from room temperature up to 150°C with positive threshold voltage shift less than 1 V. A small decrease in current with temperature up to 150°C is related to a decrease in the field effect mobility due to phonon scattering. However, the gate oxides contain sodium, which originates from the sintered alumina, resulting in severe device instabilities during negative gate bias stressing.

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44

Ren, S., H. Yang, W. Wang, H. Xu, W. Luo, B. Tang, Z. Tang, et al. "Negative Bias Temperature Instability Characteristics and Degradation Mechanisms of pMOSFET with High-k/Metal Gate Stacks." ECS Transactions 52, no. 1 (March 8, 2013): 953–57. http://dx.doi.org/10.1149/05201.0953ecst.

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45

Whiteside, Matthew, Subramaniam Arulkumaran, Yilmaz Dikme, Abhinay Sandupatla, and Geok Ing Ng. "Demonstration of AlGaN/GaN MISHEMT on Si with Low-Temperature Epitaxy Grown AlN Dielectric Gate." Electronics 9, no. 11 (November 5, 2020): 1858. http://dx.doi.org/10.3390/electronics9111858.

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AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MISHEMT) with a low-temperature epitaxy (LTE)-grown single crystalline AlN gate dielectric were demonstrated for the first time and the post-gate annealing effects at 400 °C were studied. The as-deposited LTE-AlN MISHEMT showed a maximum drain current (IDmax) of 708 mA/mm at a gate bias of 4 V and a maximum extrinsic transconductance (gmmax) of 129 mS/mm. The 400 °C annealed MISHEMT exhibited an increase of 15% in gmmax, an order of magnitude reduction in reverse gate leakage and about a 3% suppression of drain current (ID) collapse. The increase of gmmax by post-gate annealing is consistent with the increase of 2DEG mobility. The suppression of ID collapse and the reduction of gate leakage current is attributed to the reduction of interface state density (5.0 × 1011 cm−2eV−1) between the AlN/GaN interface after post-gate annealing at 400 °C. This study demonstrates that LTE grown AlN is a promising alternate material as gate dielectric for GaN-based MISHEMT application.

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46

Liao, Yiming, Xiaoli Ji, Qiang Guo, and Feng Yan. "Transformation of Holes Emission Paths under Negative Bias Temperature Stress in Deeply Scaled pMOSFETs." Advances in Condensed Matter Physics 2015 (2015): 1–6. http://dx.doi.org/10.1155/2015/508610.

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We examine the impact of negative bias temperature (NBT) stress on the fluctuations inIDandIGfor deeply scaled pMOSFETs and find that the relative high NBT stress triggersIG-RTN andID-step. Through the analysis of the field dependence of emission constant and the carrier separation measurement, it is found that under the relative high NBT stress some traps keep charged state for very long time, as observing step-like behaviors inID, while other traps emit charged holes to the gate side through TAT process, which originate bothID-step and ID-RTN.

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47

Magnone, P., G. Barletta, and A. Magrì. "Investigation of degradation mechanisms in low-voltage p-channel power MOSFETs under High Temperature Gate Bias stress." Microelectronics Reliability 88-90 (September 2018): 438–42. http://dx.doi.org/10.1016/j.microrel.2018.06.029.

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48

Zhang, T., B. Allard, and J. Bi. "The synergetic effects of high temperature gate bias and total ionization dose on 1.2 kV SiC devices." Microelectronics Reliability 88-90 (September 2018): 631–35. http://dx.doi.org/10.1016/j.microrel.2018.06.046.

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Zorn, Christian, and Nando Kaminski. "Temperature–humidity–bias testing on insulated‐gate bipolartransistor modules – failure modes and acceleration due to high voltage." IET Power Electronics 8, no. 12 (December 2015): 2329–35. http://dx.doi.org/10.1049/iet-pel.2015.0031.

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Weng, Ming Hung, Rajat Mahapatra, Nicolas G. Wright, and Alton B. Horsfall. "Post Metallization Annealing Characterization of Interface Properties of High-κ Dielectrics Stack on Silicon Carbide." Materials Science Forum 600-603 (September 2008): 771–74. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.771.

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The interface properties of TiO2/SiO2/SiC metal-insulator-semiconductor (MIS) capacitors were investigated by C-V and G-V measurements over a range of frequencies between 10 kHz and 1 MHz from room temperature up to 500°C. Ledges from multiple traps were observed during high frequency (1 MHz) sweeps from inversion to accumulation during measurements at elevated temperatures. The high measuring temperature resulted in the annealing of the sample, where the existence of trap ledges was observed to be temperature dependent. For n-type substrate negative Qf causes the shift of the C-V curve to more negative gate bias with respect to the ideal C-V curve. These fixed oxide charge is substantially reduced after post metallization annealing (PMA). We report the flat band voltage, detail in reducing fixed oxide charge and temperature dependence of density of interface traps before and after annealing of TiO2 high-κ gate dielectric stacks on a 4H-SiC based device.

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Journal articles on the topic 'High Temperature Gate Bias - HTGB'

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