Relevant bibliographies by topics / Input buffer

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers
  5. Reports

Academic literature on the topic 'Input buffer'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Input buffer"

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Li, Cunlu, Dezun Dong, Shazhou Yang, Xiangke Liao, Guangyu Sun, and Yongheng Liu. "CIB-HIER." ACM Transactions on Architecture and Code Optimization 18, no. 4 (December 31, 2021): 1–21. http://dx.doi.org/10.1145/3468062.

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Hierarchical organization is widely used in high-radix routers to enable efficient scaling to higher switch port count. A general-purpose hierarchical router must be symmetrically designed with the same input buffer depth, resulting in a large amount of unused input buffers due to the different link lengths. Sharing input buffers between different input ports can improve buffer utilization, but the implementation overhead also increases with the number of shared ports. Previous work allowed input buffers to be shared among all router ports, which maximizes the buffer utilization but also introduces higher implementation complexity. Moreover, such design can impair performance when faced with long packets, due to the head-of-line blocking in intermediate buffers. In this work, we explain that sharing unused buffers between a subset of router ports is a more efficient design. Based on this observation, we propose Centralized Input Buffer Design in Hierarchical High-radix Routers (CIB-HIER), a novel centralized input buffer design for hierarchical high-radix routers. CIB-HIER integrates multiple input ports onto a single tile and organizes all unused input buffers in the tile as a centralized input buffer. CIB-HIER only allows the centralized input buffer to be shared between ports on the same tile, without introducing additional intermediate virtual channels or global scheduling circuits. Going beyond the basic design of CIB-HIER, the centralized input buffer can be used to relieve the head-of-line blocking caused by shallow intermediate buffers, by stashing long packets in the centralized input buffer. Experimental results show that CIB-HIER is highly effective and can significantly increase the throughput of high-radix routers.
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Lanyi, S., and M. Pisani. "A high-input-impedance buffer." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 49, no. 8 (August 2002): 1209–11. http://dx.doi.org/10.1109/tcsi.2002.801287.

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Scheinhardt, Werner R. W., and Bert Zwart. "A TANDEM FLUID QUEUE WITH GRADUAL INPUT." Probability in the Engineering and Informational Sciences 16, no. 1 (January 2002): 29–45. http://dx.doi.org/10.1017/s0269964802161031.

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For a two-node tandem fluid model with gradual input, we compute the joint steady-state buffer-content distribution. Our proof exploits martingale methods developed by Kella and Whitt. For the case of finite buffers, we use an insightful sample-path argument to extend an earlier proportionality result of Zwart to the network case.
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Paik, Jung Hoon, and Chae Tak Lim. "The Analysis of Input Queueing Techniques on a Crosspoint Packet Switch." Journal of Circuits, Systems and Computers 07, no. 04 (August 1997): 319–31. http://dx.doi.org/10.1142/s0218126697000231.

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In this paper, an N × N input-buffered crosspoint packet switch which selects a Head of the Line, HOL, packet in contention randomly is analyzed with a new approach. The approach is based on both a Markov chain representation of the input buffer and the probability that a HOL packet is successfully served. The probability as a function of N is derived, and it makes it possible to express the average packet delay and the average number of packets in the buffer as a function of N. The new contention resolution policy based on the occupancy of the input buffer is also presented and analyzed with this same approach and the relationship between the two selection policies is analyzed.
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Chan, P. K., L. Siek, T. Lim, and M. K. Han. "Adaptive-biased buffer with low input capacitance." Electronics Letters 36, no. 9 (2000): 775. http://dx.doi.org/10.1049/el:20000644.

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Bundalo, Z. V., and B. L. Dorić. "Three-state CMOS buffer with input hysteresis." Electronics Letters 24, no. 14 (1988): 885. http://dx.doi.org/10.1049/el:19880603.

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Jiang, Fei, Heather E. Preisendanz, Tamie L. Veith, Raj Cibin, and Patrick J. Drohan. "Riparian buffer effectiveness as a function of buffer design and input loads." Journal of Environmental Quality 49, no. 6 (October 11, 2020): 1599–611. http://dx.doi.org/10.1002/jeq2.20149.

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Kisriani, Shinta, Eri Prasetyo Wibowo, Busono Soerowirdjo, Hamzah Afandi, and Veronica Ernita Kristianti. "A Comparison Study of Three of Input Buffer Designed Using 0.35µm CMOS Technology." Advanced Materials Research 646 (January 2013): 184–90. http://dx.doi.org/10.4028/www.scientific.net/amr.646.184.

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In memory device that is contained in the digital application, there is a sequence of input buffer.The input buffer’s function is to improve a digital signal and remove noise. The buffer circuit take these input signal with imperfections and convert them in to full digital logic levels by slicing the signals at correct levels which depends upon the switching point voltage. In this paper,using three topologies, that are NMOS, PMOS and Parallel input buffer. It would be present into design, simulation and analysis of all topologies input buffer. The result in this paper to determine the best of the three topologies to used. The delay time used to determine the best of topologies. Mentor graphic is tools which used in this paper to design and simulation. The technology used in this paper is 0.35 µm CMOS Technology. Analysis of comparison all of topologies used in this paper based on six parameters. The result of comparison analysis can be seen in more details in this explanation.
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CITRO, R. "An Adaptive Dynamic Buffer Management (ADBM) Approach for Input Buffers in ATM Networks." IEICE Transactions on Communications E88-B, no. 3 (March 1, 2005): 1084–96. http://dx.doi.org/10.1093/ietcom/e88-b.3.1084.

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Zwart, A. P. "A fluid queue with a finite buffer and subexponential input." Advances in Applied Probability 32, no. 01 (March 2000): 221–43. http://dx.doi.org/10.1017/s000186780000985x.

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We consider a fluid model similar to that of Kella and Whitt [32], but with a buffer having finite capacity K. The connections between the infinite buffer fluid model and the G/G/1 queue established by Kella and Whitt are extended to the finite buffer case: it is shown that the stationary distribution of the buffer content is related to the stationary distribution of the finite dam. We also derive a number of new results for the latter model. In particular, an asymptotic expansion for the loss fraction is given for the case of subexponential service times. The stationary buffer content distribution of the fluid model is also related to that of the corresponding model with infinite buffer size, by showing that the two corresponding probability measures are proportional on [0,K) if the silence periods are exponentially distributed. These results are applied to obtain large buffer asymptotics for the loss fraction and the mean buffer content when the fluid queue is fed by N On-Off sources with subexponential on-periods. The asymptotic results show a significant influence of heavy-tailed input characteristics on the performance of the fluid queue.
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Dissertations / Theses on the topic "Input buffer"

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Niemelä, J. (Jari). "Design and verification of a logic input buffer." Master's thesis, University of Oulu, 2014. http://urn.fi/URN:NBN:fi:oulu-201402121090.

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Two low-power logic input buffer topologies are designed, simulated and compared. The most important parameters of the buffers are input threshold voltage level stability and minimal current consumption. Topologies have been implemented earlier for a wider line width process, and now the intention is to move them to a narrower line width process without losing performance. Based on the simulations, a topology with the better performance and smaller area is chosen and layout for particular topology is designed. Layout parasitics effect to the performance is also verified by simulations. In this thesis are also discussed common buffer structures and I/O structures shielding against outside of a circuit disturbances. Finally there is a measurement plan how an input buffer functionality could be measured and verified on a chip
Työssä suunnitellaan, simuloidaan ja verrataan kahta eri topologialla toteutettua kontrollitulopuskuria, joiden tärkeimmät parametrit ovat tulon kynnystason stabiilisuus ja minimaalinen virrankulutus. Topologiat ovat aiemmin toteutettuja leveämmällä viivanleveydellä, ja ne on tarkoitus siirtää kapeamman viivanleveyden prosessiin suorituskyky säilyttäen. Simulointien perusteella valitaan suorituskyvyltään parempi ja pinta-alaltaan pienempi tulopuskuri, ja sille piirretään piirikuvio ja varmennetaan parasiittisten komponenttien vaikutus toimintaan. Diplomityössä käsitellään myös yleisesti puskureita ja I/O-rakenteiden suojausta. Puskurit ovat yhteydessä piirin ulkopuoliseen maailmaan ja niiden täytyy kestää piirin ulkopuoliset häiriötekijät. Lopuksi esitetään mittaussuunnitelma, jolla tulopuskurin toiminta voitaisiin mitata ja varmentaa valmistetusta komponentista
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Lundberg, Jesper, and Ronja Mehtonen. "Utvärdering och analys av batchstorlekar, produktsekvenser och omställningstider." Thesis, Högskolan i Skövde, Institutionen för ingenjörsvetenskap, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:his:diva-11859.

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Volvo GTO is one of the strongest brands in the truck industry, with a long and proud history of world-leading innovations. The factory in Skövde produces diesel engines of various sizes to Volvo GTO. The project has been carried out on the processing part of grovdel crankshaft. Where the objective was to construct a simulation model that reflects flows 0, 1 and 2 on the crankshaft grovdel order to produce the best driving style for the size of the batches and sequences, focusing on PIA, between the stock and conversion-up times. A theoretical study intervention gave knowledge to the methodology to ensure that the data is collected and processed correctly. The data were collected in an Excel document, which was integrated with the simulation model for an overview and adjustments would be possible. The simulation program, Siemens Plant Simulation 12 used in the construction of the complex model of the three flows, which where verified and validated against the real flows. Optimization on the simulation model was made with a high and a low demand for crankshafts. Several objects were taken into consideration as: minimal waiting processing Findel, minimal setup time and minimal total-PIA from a truly viable perspective. The optimization showed a possible production planning in order to best be able to run such large batches as possible with reduced readjustment time and for delays of production in processing rawflows to not occur in the refined flow. For maximum capacity in the company there are two different optimal solutions one solution focused on reducing setup time and the second solution to minimize the number of additional production hours per week. Discrete simulation of production flows are being used to support production planning and simulation model is created for the continued use of the Volvo GTO, either in simulation group or future researches and theses in collaboration with the University of Skövde. The project objectives were achieved with good results and resulted as a standing basis for future planning of batches and sequences of processing crankshaft Volvo GTO.
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Jacobson, Mark Alan. "Input and response buffers in transcription handwriting." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/28862.

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Nguyen, Kim-Minh Carleton University Dissertation Engineering Electronics. "Module generators for the layout synthesis of BiCMOS input/output buffers." Ottawa, 1993.

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Charny, Anna. "Providing QoS guarantees in input buffered crossbar switches with speedup." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/9628.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.
Includes bibliographical references (p. 103-105).
This dissertation investigates a number of issues related to providing Quality of Service guarantees in input-buffered crossbar switches with speedup. It is shown that speedup of 4 is sufficient to ensure 100% asymptotic throughput with any maximal matching algorithm employed by the arbiter. It is also demonstrated that the crossbar architecture is capable of providing delay guarantees comparable to those known for output-buffered switch architecture. Several algorithms which ensure different delay guarantees with different values of speedup are presented and analyzed.
by Anna Charny.
Ph.D.
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Tabatabaee, Vahid. "Scheduling and rate provisioning for input-buffered cell based switch fabrics." College Park, Md. : University of Maryland, 2003. http://hdl.handle.net/1903/141.

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Thesis (Ph. D.) -- University of Maryland, College Park, 2003.
Thesis research directed by: Electrical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
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Pisár, Peter. "Metody návrhu aktivních kmitočtových filtrů na základě pasivního RLC prototypu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-218107.

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The aim of this diploma thesis is to design active frequency filters based on passive RLC prototype. Three methods of the design of active filters and active functional blocks of electronic circuits working in current or mixed mode are used to this purpose. These blocks allow to process electrical signals with frequencies up to low tens of megahertz. In addition they feature for instance with high slew rate and low supply voltage power. Active high-pass and low-pass 2nd order filters are designed using simulation of inductor by active subcircuit method. Grounded and subsequently floating synthetic inductor is made with the current conveyors in the first case and with the current operational amplifiers with single input and differential output in the second case. This method advantage is relatively simple design and disadvantage is great quantity of active functional blocks. Active filters based on passive frequency ladder 3rd order filter while only one floating inductor is connected, are designed with circuit equation method. In the first design differential input / output current followers are used and in the second case current-differencing buffered amplifiers are used. This method benefits by smaller active blocks number and disadvantage is more complex design of the active filter. Active filter based on passive prototype of low-pass 3rd order filter with two floating inductors is designed with Bruton transformation method. Final active filter uses current operational amplifiers with single input and differential output which together with other passive elements replace frequency depending negative resistor, which arise after previous Bruton transform. This method usage is advantageous if the design consists of larger quantity of inductors and less number of capacitors. High-pass 2nd order filter is simulated by tolerance and parametrical analyses. Physical realisation utilising current feedback operational amplifier which substitute commercially hardly accessible current conveyors is subsequently made. Measurements of constructed active filter show that additional modifications, which allow better amplitude frequency characteristics conformity, are necessary.
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Liu, Dequan. "Joint buffer management and scheduling for input queued switches." Thesis, 2003. http://library1.njit.edu/etd/fromwebvoyage.cfm?id=njit-etd2003-024.

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Wang, Chen-Tai, and 王振泰. "The Design of a Serial Input Random Output Buffer." Thesis, 1993. http://ndltd.ncl.edu.tw/handle/07289474930284679804.

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Hu, Ting-Wei, and 胡庭維. "Input Buffer Improved High Speed Asynchronous Successive Approximation Register ADC." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/70012398542253459114.

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碩士
國立中興大學
電機工程學系所
104
This thesis presents an input buffer improved high speed Asynchronous successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). The application is as a sub-ADC of a time-interleaved ADC. In order to enhance the converter’s effective number of bits, the input buffer is added. The frist design, Sarf2_34 ,has oscillations found during measurement. Thus a second design Sarf2_35 improve the input buffer circuit to solve, the output waveform oscillation issue. With TSMC 90nm GUTM manufacturing process, and sampling frequency as 166MHZ, measurement results of Sarf2_35 chip is obtained. When input frequency is 10MHZ ,the effective number of bits is 6.09bit.When input frequency is 1GHZ, the effective number of bits is 3.48bit.
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Book chapters on the topic "Input buffer"

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Shakir, Hasan, Yasser Najeeb, and M. Nizamuddin. "CNTFET-Based Input Buffer for High-Speed Data Transmission." In Lecture Notes in Civil Engineering, 661–68. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-2545-2_54.

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Kim, Che Soong, Valentina Klimenok, and Alexander Dudin. "Retrial Queueing System with Correlated Input, Finite Buffer, and Impatient Customers." In Analytical and Stochastic Modeling Techniques and Applications, 262–76. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-39408-9_19.

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Weik, Martin H. "buffered input." In Computer Science and Communications Dictionary, 150. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_1913.

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Kempa, Wojciech M. "Time to Start a Crowded Period in a Finite-Buffer Queue with Poisson Input Flow and General Processing Times." In Finite Difference Methods. Theory and Applications, 329–36. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-11539-5_37.

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Dunsmuir, M. R. M., and G. J. Davies. "Buffered Input and Output." In Programming the UNIXTM System, 80–95. London: Macmillan Education UK, 1985. http://dx.doi.org/10.1007/978-1-349-07371-9_5.

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Banik, A. D., Souvik Ghosh, and M. L. Chaudhry. "On the Consecutive Customer Loss Probabilities in a Finite-Buffer Renewal Batch Input Queue with Different Batch Acceptance/Rejection Strategies Under Non-renewal Service." In Advances in Intelligent Systems and Computing, 45–62. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-1592-3_4.

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Lee, Tsern-Huei, and Ying-Che Kuo. "Performance Evaluation of Combined Input Output Queued Switch with Finite Input and Output Buffers." In Information Networking: Wired Communications and Management, 203–14. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-45803-4_19.

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Lund, Carsten, Steven Phillips, and Nick Reingold. "Fair Prioritized Scheduling in an Input-Buffered Switch." In Broadband Communications, 358–69. Boston, MA: Springer US, 1996. http://dx.doi.org/10.1007/978-0-387-34987-9_30.

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Manjunath, D., and Biplab Sikdar. "Variable Length Packet Switches: Input Queued Fabrics with Finite Buffers, Speedup, and Parallelism." In High Performance Computing — HiPC 2001, 372–82. Berlin, Heidelberg: Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/3-540-45307-5_33.

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Radusinovic, Igor, and Zoran Veljovic. "New Round-Robin Scheduling Algorithm for Combined Input-Crosspoint Buffered Switch." In Networking - ICN 2005, 857–64. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/978-3-540-31956-6_101.

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Conference papers on the topic "Input buffer"

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Hribik, Jan, Stefan Lanyi, and Miloslav Hruskovic. "A High-Input-Impedance Buffer." In 2008 18th International Conference Radioelektronika. IEEE, 2008. http://dx.doi.org/10.1109/radioelek.2008.4542707.

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Mashin, Stanislav, Martin Sira, and Tereza Skalicka. "Precision Buffer with Low Input Capacitance." In 2018 Conference on Precision Electromagnetic Measurements (CPEM 2018). IEEE, 2018. http://dx.doi.org/10.1109/cpem.2018.8501232.

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Wu, Zekai, Chengwei Wang, Yang Ding, Fule Li, and Zhihua Wang. "An ADC Input Buffer with Optimized Linearity." In 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, 2018. http://dx.doi.org/10.1109/icsict.2018.8564827.

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Thiem, Chu Van, and Shigeru Oyanagi. "An Input Buffer Architecture for On-chip Routers." In 2011 Second International Conference on Networking and Computing (ICNC). IEEE, 2011. http://dx.doi.org/10.1109/icnc.2011.51.

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Cao, Fubiao, Yongzhen Chen, Zhiyuan Dai, Fan Ye, and Junyan Ren. "An input buffer for 12bit 2GS/s ADC." In 2017 IEEE 12th International Conference on ASIC (ASICON). IEEE, 2017. http://dx.doi.org/10.1109/asicon.2017.8252584.

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Nicolae, Cojan, Cracan Arcadie, and Cojan Radu. "Test buffer with extended common mode input voltage." In Melecon 2010 - 2010 15th IEEE Mediterranean Electrotechnical Conference. IEEE, 2010. http://dx.doi.org/10.1109/melcon.2010.5476002.

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Yaming Yin, Shuming Chen, and Xiao Hu. "Input buffer planning for network-on-chip router design." In 2010 International Conference on Computer Application and System Modeling (ICCASM 2010). IEEE, 2010. http://dx.doi.org/10.1109/iccasm.2010.5622722.

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Wang, Jun, Kun Huang, Ge Zhang, Weiwu Hu, and Feng Zhang. "Energy-Efficient Input Buffer Design using Data-Transition Oriented Model." In 2007 International Symposium on Integrated Circuits. IEEE, 2007. http://dx.doi.org/10.1109/isicir.2007.4441837.

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Boyer, A., M. Fer, L. Courau, E. Sicard, and S. BenDhia. "Modelling of the susceptibility of 90 nm input output buffer." In Exhibition. IEEE, 2008. http://dx.doi.org/10.1109/apemc.2008.4559804.

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Neishabouri, M. H., and Zeljko Zilic. "Reliability aware NoC router architecture using input channel buffer sharing." In the 19th ACM Great Lakes symposium. New York, New York, USA: ACM Press, 2009. http://dx.doi.org/10.1145/1531542.1531658.

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Reports on the topic "Input buffer"

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Cheng, Angela. Input/Output Buffers for ASP. Fort Belvoir, VA: Defense Technical Information Center, May 1989. http://dx.doi.org/10.21236/ada632212.

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