Relevant bibliographies by topics / Input buffer

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Input buffer'

Author: Grafiati
Published: 4 June 2021
Last updated: 25 July 2025

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Journal articles on the topic "Input buffer"

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Li, Cunlu, Dezun Dong, Shazhou Yang, Xiangke Liao, Guangyu Sun, and Yongheng Liu. "CIB-HIER." ACM Transactions on Architecture and Code Optimization 18, no. 4 (2021): 1–21. http://dx.doi.org/10.1145/3468062.

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Hierarchical organization is widely used in high-radix routers to enable efficient scaling to higher switch port count. A general-purpose hierarchical router must be symmetrically designed with the same input buffer depth, resulting in a large amount of unused input buffers due to the different link lengths. Sharing input buffers between different input ports can improve buffer utilization, but the implementation overhead also increases with the number of shared ports. Previous work allowed input buffers to be shared among all router ports, which maximizes the buffer utilization but also intro
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Dudin, Alexander, Olga Dudina, Sergei Dudin, and Agassi Melikov. "Analysis of a Queueing Model with Flexible Priority, Batch Arrival, and Impatient Customers." Computation 13, no. 3 (2025): 77. https://doi.org/10.3390/computation13030077.

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In this study, we consider a multi-server priority queueing model with batch arrivals of two types of customers, a finite buffer, and two input finite buffers for storing customers that cannot be admitted for service immediately upon arrival. The transition of a customer from an input buffer to the main buffer can occur after an exponentially distributed time. Customers residing in the input and main buffers are impatient. The four-dimensional Markov chain is used to describe the dynamics of the system under consideration. It is analyzed via the derivation of its generator and providing an eff
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Lanyi, S., and M. Pisani. "A high-input-impedance buffer." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 49, no. 8 (2002): 1209–11. http://dx.doi.org/10.1109/tcsi.2002.801287.

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Scheinhardt, Werner R. W., and Bert Zwart. "A TANDEM FLUID QUEUE WITH GRADUAL INPUT." Probability in the Engineering and Informational Sciences 16, no. 1 (2002): 29–45. http://dx.doi.org/10.1017/s0269964802161031.

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For a two-node tandem fluid model with gradual input, we compute the joint steady-state buffer-content distribution. Our proof exploits martingale methods developed by Kella and Whitt. For the case of finite buffers, we use an insightful sample-path argument to extend an earlier proportionality result of Zwart to the network case.
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Paik, Jung Hoon, and Chae Tak Lim. "The Analysis of Input Queueing Techniques on a Crosspoint Packet Switch." Journal of Circuits, Systems and Computers 07, no. 04 (1997): 319–31. http://dx.doi.org/10.1142/s0218126697000231.

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In this paper, an N × N input-buffered crosspoint packet switch which selects a Head of the Line, HOL, packet in contention randomly is analyzed with a new approach. The approach is based on both a Markov chain representation of the input buffer and the probability that a HOL packet is successfully served. The probability as a function of N is derived, and it makes it possible to express the average packet delay and the average number of packets in the buffer as a function of N. The new contention resolution policy based on the occupancy of the input buffer is also presented and analyzed with
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AZAROV, Olexiy, and Оlexiy STAKHOV. "PUSH-PULL VOLTAGE BUFFER DEVICES ON BIPOLAR TRANSISTORS." Herald of Khmelnytskyi National University. Technical sciences 311, no. 4 (2022): 18–22. http://dx.doi.org/10.31891/2307-5732-2022-311-4-18-22.

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The article proposes linear push-pull buffer devices on bipolar transistors. A highly linear push-pull voltage buffer device with parametric zero shift compensation is considered. A variant of the construction of a highly linear push-pull voltage buffer device on bipolar transistors with a minimum value of the input current is proposed. The purpose of the work is to minimize the additive error of the buffer device by significantly reducing the input current. Analytical relations are given that allow estimating the additive error of the zero shift. The schematic diagram of a two-stroke buffer d
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Tabash, I. K., M. A. Mamun, and A. Negi. "A Fuzzy Logic Based Network Congestion Control Using Active Queue Management Techniques." Journal of Scientific Research 2, no. 2 (2010): 273–84. http://dx.doi.org/10.3329/jsr.v2i2.2786.

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Conventional IP routers are passive devices that accept packets and perform the routing function on any input. Usually the tail-drop (TD) strategy is used where the input which exceeds the buffer capacity are simply dropped. In active queue management (AQM) methods routers manage their buffers by dropping packets selectively. We study one of the AQM methods called as random exponential marking (REM). We propose an intelligent approach to AQM based on fuzzy logic controller (FLC) to drop packets dynamically, keep the buffer size around desired level and also prevent buffer overflow. Our propose
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Prabhakar, Balaji, Nicholas Bambos, and T. S. Mountford. "The synchronization of Poisson processes and queueing networks with service and synchronization nodes." Advances in Applied Probability 32, no. 3 (2000): 824–43. http://dx.doi.org/10.1239/aap/1013540246.

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This paper investigates the dynamics of a synchronization node in isolation, and of networks of service and synchronization nodes. A synchronization node consists of M infinite capacity buffers, where tokens arriving on M distinct random input flows are stored (there is one buffer for each flow). Tokens are held in the buffers until one is available from each flow. When this occurs, a token is drawn from each buffer to form a group-token, which is instantaneously released as a synchronized departure. Under independent Poisson inputs, the output of a synchronization node is shown to converge we
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Prabhakar, Balaji, Nicholas Bambos, and T. S. Mountford. "The synchronization of Poisson processes and queueing networks with service and synchronization nodes." Advances in Applied Probability 32, no. 03 (2000): 824–43. http://dx.doi.org/10.1017/s0001867800010272.

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This paper investigates the dynamics of a synchronization node in isolation, and of networks of service and synchronization nodes. A synchronization node consists of M infinite capacity buffers, where tokens arriving on M distinct random input flows are stored (there is one buffer for each flow). Tokens are held in the buffers until one is available from each flow. When this occurs, a token is drawn from each buffer to form a group-token, which is instantaneously released as a synchronized departure. Under independent Poisson inputs, the output of a synchronization node is shown to converge we
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Zwart, A. P. "A fluid queue with a finite buffer and subexponential input." Advances in Applied Probability 32, no. 1 (2000): 221–43. http://dx.doi.org/10.1239/aap/1013540031.

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We consider a fluid model similar to that of Kella and Whitt [32], but with a buffer having finite capacity K. The connections between the infinite buffer fluid model and the G/G/1 queue established by Kella and Whitt are extended to the finite buffer case: it is shown that the stationary distribution of the buffer content is related to the stationary distribution of the finite dam. We also derive a number of new results for the latter model. In particular, an asymptotic expansion for the loss fraction is given for the case of subexponential service times. The stationary buffer content distrib
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Dissertations / Theses on the topic "Input buffer"

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Niemelä, J. (Jari). "Design and verification of a logic input buffer." Master's thesis, University of Oulu, 2014. http://urn.fi/URN:NBN:fi:oulu-201402121090.

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Two low-power logic input buffer topologies are designed, simulated and compared. The most important parameters of the buffers are input threshold voltage level stability and minimal current consumption. Topologies have been implemented earlier for a wider line width process, and now the intention is to move them to a narrower line width process without losing performance. Based on the simulations, a topology with the better performance and smaller area is chosen and layout for particular topology is designed. Layout parasitics effect to the performance is also verified by simulations. In this
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Lundberg, Jesper, and Ronja Mehtonen. "Utvärdering och analys av batchstorlekar, produktsekvenser och omställningstider." Thesis, Högskolan i Skövde, Institutionen för ingenjörsvetenskap, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:his:diva-11859.

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Volvo GTO is one of the strongest brands in the truck industry, with a long and proud history of world-leading innovations. The factory in Skövde produces diesel engines of various sizes to Volvo GTO. The project has been carried out on the processing part of grovdel crankshaft. Where the objective was to construct a simulation model that reflects flows 0, 1 and 2 on the crankshaft grovdel order to produce the best driving style for the size of the batches and sequences, focusing on PIA, between the stock and conversion-up times. A theoretical study intervention gave knowledge to the methodolo
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Jacobson, Mark Alan. "Input and response buffers in transcription handwriting." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/28862.

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Nguyen, Kim-Minh Carleton University Dissertation Engineering Electronics. "Module generators for the layout synthesis of BiCMOS input/output buffers." Ottawa, 1993.

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Charny, Anna. "Providing QoS guarantees in input buffered crossbar switches with speedup." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/9628.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.<br>Includes bibliographical references (p. 103-105).<br>This dissertation investigates a number of issues related to providing Quality of Service guarantees in input-buffered crossbar switches with speedup. It is shown that speedup of 4 is sufficient to ensure 100% asymptotic throughput with any maximal matching algorithm employed by the arbiter. It is also demonstrated that the crossbar architecture is capable of providing delay guarantees comparable to those known for output-bu
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Tabatabaee, Vahid. "Scheduling and rate provisioning for input-buffered cell based switch fabrics." College Park, Md. : University of Maryland, 2003. http://hdl.handle.net/1903/141.

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Thesis (Ph. D.) -- University of Maryland, College Park, 2003.<br>Thesis research directed by: Electrical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
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Pisár, Peter. "Metody návrhu aktivních kmitočtových filtrů na základě pasivního RLC prototypu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-218107.

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The aim of this diploma thesis is to design active frequency filters based on passive RLC prototype. Three methods of the design of active filters and active functional blocks of electronic circuits working in current or mixed mode are used to this purpose. These blocks allow to process electrical signals with frequencies up to low tens of megahertz. In addition they feature for instance with high slew rate and low supply voltage power. Active high-pass and low-pass 2nd order filters are designed using simulation of inductor by active subcircuit method. Grounded and subsequently floating synth
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Wang, Chen-Tai, and 王振泰. "The Design of a Serial Input Random Output Buffer." Thesis, 1993. http://ndltd.ncl.edu.tw/handle/07289474930284679804.

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Liu, Dequan. "Joint buffer management and scheduling for input queued switches." Thesis, 2003. http://library1.njit.edu/etd/fromwebvoyage.cfm?id=njit-etd2003-024.

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Peng, Chih-Yang, and 彭志洋. "Block and Input/Ouput Buffer Placement in Flip-Chip Design." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/61649670636516290542.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>91<br>The flip-chip package gives the highest chip density of any packaging method to support the pad-limited ASIC design. One of the most important characteristics of flip chip designs is that the input/output buffers could be placed anywhere inside a chip. For most practical designs, we have to control the timing of the input/output signals. This can be achieved through controlling the positions of bump balls, input/output buffers, and first stage/last-stage cells in a flip chip. Specifically, we intend to minimize the path length between blocks and bump balls as
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Books on the topic "Input buffer"

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Natarajan, Shantha. 5 GHz 1: 2 LVPECL Fanout Buffer/Translator with Internal Input Termination. Microchip Technology Incorporated, 2020.

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Nelson, Taylor. SY58012U - 5 GHz 1: 2 LVPECL Fanout Buffer/Translator with Internal Input Termination. Microchip Technology Incorporated, 2020.

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Nelson, Taylor. SY58606U - 4. 25Gbps Precision, 1: 2 CML Fanout Buffer with Internal Termination and Fail Safe Input. Microchip Technology Incorporated, 2019.

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Nelson, Taylor. SY58607U - 3. 2 Gbps Precision, 1: 2 LVPECL Fanout Buffer with Internal Termination and Fail Safe Input. Microchip Technology Incorporated, 2019.

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Nelson, Taylor. SY58608U - 3. 2 Gbps Precision, 1: 2 LVDS Fanout Buffer with Internal Termination and Fail Safe Input. Microchip Technology Incorporated, 2018.

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Book chapters on the topic "Input buffer"

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Shakir, Hasan, Yasser Najeeb, and M. Nizamuddin. "CNTFET-Based Input Buffer for High-Speed Data Transmission." In Lecture Notes in Civil Engineering. Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-2545-2_54.

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Kim, Che Soong, Valentina Klimenok, and Alexander Dudin. "Retrial Queueing System with Correlated Input, Finite Buffer, and Impatient Customers." In Analytical and Stochastic Modeling Techniques and Applications. Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-39408-9_19.

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Leonardo, David, and João Goes. "An Energy-Efficient Wideband Input-Buffer for High-Speed CMOS ADCs." In Technological Innovation for Digitalization and Virtualization. Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-07520-9_18.

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Bernardi, Giovanni, Ilaria Castellani, Paul Laforgue, and Léo Stefanesco. "Constructive characterisations of the MUST-preorder for asynchrony." In Lecture Notes in Computer Science. Springer Nature Switzerland, 2025. https://doi.org/10.1007/978-3-031-91118-7_4.

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Abstract De Nicola and Hennessy’s $$\textsc {must}$$ M U S T -preorder is a liveness preserving refinement which states that a server $$q$$ q refines a server $$p$$ p if all clients satisfied by $$p$$ p are also satisfied by $$q$$ q . Owing to the universal quantification over clients, this definition does not yield a practical proof method, and alternative characterisations are necessary to reason over it. Finding these characterisations for asynchronous semantics, i.e. where outputs are non-blocking, has thus far proven to be a challenge, usually tackled via ad-hoc definitions. We show that
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Weik, Martin H. "buffered input." In Computer Science and Communications Dictionary. Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_1913.

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Kempa, Wojciech M. "Time to Start a Crowded Period in a Finite-Buffer Queue with Poisson Input Flow and General Processing Times." In Finite Difference Methods. Theory and Applications. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-11539-5_37.

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Dunsmuir, M. R. M., and G. J. Davies. "Buffered Input and Output." In Programming the UNIXTM System. Macmillan Education UK, 1985. http://dx.doi.org/10.1007/978-1-349-07371-9_5.

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Banik, A. D., Souvik Ghosh, and M. L. Chaudhry. "On the Consecutive Customer Loss Probabilities in a Finite-Buffer Renewal Batch Input Queue with Different Batch Acceptance/Rejection Strategies Under Non-renewal Service." In Advances in Intelligent Systems and Computing. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-1592-3_4.

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Lee, Tsern-Huei, and Ying-Che Kuo. "Performance Evaluation of Combined Input Output Queued Switch with Finite Input and Output Buffers." In Information Networking: Wired Communications and Management. Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-45803-4_19.

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Lund, Carsten, Steven Phillips, and Nick Reingold. "Fair Prioritized Scheduling in an Input-Buffered Switch." In Broadband Communications. Springer US, 1996. http://dx.doi.org/10.1007/978-0-387-34987-9_30.

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Conference papers on the topic "Input buffer"

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Kang, Donggeun, Donghyeon Kim, Dongin Jung, Siuk Roh, and Jiyong Kim. "Sustainable production of L-lactic acid from lignocellulosic biomass using an alternative buffer system: Process development and techno-economic and environmental analysis." In The 35th European Symposium on Computer Aided Process Engineering. PSE Press, 2025. https://doi.org/10.69997/sct.174326.

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L-lactic acid (L-LA), a key monomer in biodegradable plastics, is a sustainable alternative that can be derived from LCB. The L-LA production process typically involves various technologies such as fermentation, filtration, and distillation. In the L-LA production process, large amounts of buffers are used to maintain proper pH during fermentation, so conventional buffers (e.g., CaCO3) are often selected because of their low cost. However, these buffers cannot be recycled efficiently, and the potential for alternative buffers remains uncertain. In this work, we aim to develop and evaluate nove
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Tang, Chao, Dawei Li, Xuan Guo, et al. "A 106.5 dB SNDR Delta Sigma Modulator with an Improved Input Buffer." In 2023 International Conference on Information Processing and Network Provisioning (ICIPNP). IEEE, 2023. https://doi.org/10.1109/icipnp62754.2023.00059.

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Zhang, Wei, Xizhu Peng, and He Tang. "A 1.2-V 2-GS/s Trimming-Free Input Buffer with Robust Output Common-Mode Voltage." In 2024 IEEE 17th International Conference on Solid-State & Integrated Circuit Technology (ICSICT). IEEE, 2024. https://doi.org/10.1109/icsict62049.2024.10832065.

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Chen, Zhuoyi, Siyuan Ye, Jihang Gao, et al. "An Easy-Drive 16MS/s Pipelined-SAR ADC Using Split Coarse-Fine Input-Buffer-Sampling Scheme and Fast Robust Background Inter-Stage Gain Calibration." In 2025 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 2025. https://doi.org/10.1109/isscc49661.2025.10904526.

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Ye, Siyuan, Jiajia Cui, Jihang Gao, et al. "18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting." In 2025 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 2025. https://doi.org/10.1109/isscc49661.2025.10904773.

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Hribik, Jan, Stefan Lanyi, and Miloslav Hruskovic. "A High-Input-Impedance Buffer." In 2008 18th International Conference Radioelektronika. IEEE, 2008. http://dx.doi.org/10.1109/radioelek.2008.4542707.

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Mashin, Stanislav, Martin Sira, and Tereza Skalicka. "Precision Buffer with Low Input Capacitance." In 2018 Conference on Precision Electromagnetic Measurements (CPEM 2018). IEEE, 2018. http://dx.doi.org/10.1109/cpem.2018.8501232.

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Wu, Zekai, Chengwei Wang, Yang Ding, Fule Li, and Zhihua Wang. "An ADC Input Buffer with Optimized Linearity." In 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, 2018. http://dx.doi.org/10.1109/icsict.2018.8564827.

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Zitkovich, Mirko, and Danilo Bórquez-Paredes. "Input Buffer in Dynamic Elastic Optical Networks." In 2023 42nd IEEE International Conference of the Chilean Computer Science Society (SCCC). IEEE, 2023. http://dx.doi.org/10.1109/sccc59417.2023.10315754.

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Nicolae, Cojan, Cracan Arcadie, and Cojan Radu. "Test buffer with extended common mode input voltage." In Melecon 2010 - 2010 15th IEEE Mediterranean Electrotechnical Conference. IEEE, 2010. http://dx.doi.org/10.1109/melcon.2010.5476002.

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Reports on the topic "Input buffer"

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Cheng, Angela. Input/Output Buffers for ASP. Defense Technical Information Center, 1989. http://dx.doi.org/10.21236/ada632212.

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Saltus, Christina, Richard Johansen, Molly Reif, Weston Nowlin, Benjamin Schwartz, and Joshuah Perkins. Next Generation Ecological Models - Central Texas Watersheds: Geospatial Layers and Related Tables. Engineer Research and Development Center (U.S.), 2023. http://dx.doi.org/10.21079/11681/47608.

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Relevant geospatial data layers are required for developing next generation ecological response models for specific reaches of 5 rivers in Central Texas: Colorado, Concho, San Saba, Llano, and Pedernales Rivers. Therefore, a collaborative effort between Engineer Research and Development Center (ERDC), Texas State University, and Texas A&amp;M University was undertaken to acquire and curate a collection of biological and physical datasets to be utilized as inputs for next generation ecological response models at various spatial scales (watershed, river buffer, and point). The objective was to a
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Strengthening recovery actions for Southern Resident killer whales. Raincoast Conservation Foundation, 2025. https://doi.org/10.70766/32.7300.

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An ad hoc science panel was convened in Vancouver, Canada from March 4-6, 2025, to address the conservation and recovery of the endangered Southern Resident killer whale (SRKW) population – which, as of the July 2024 census, numbered only 73 individuals. The panel assembled 31 international experts from universities, government agencies, and NGOs across Canada, the United States, and the European Union to assess the efficacy and limitations of existing threat-reduction strategies, and propose new or revised measures. Their expertise covered a range of disciplines, including killer whale biolog
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