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Journal articles on the topic 'Input buffer'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 July 2025

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1

Li, Cunlu, Dezun Dong, Shazhou Yang, Xiangke Liao, Guangyu Sun, and Yongheng Liu. "CIB-HIER." ACM Transactions on Architecture and Code Optimization 18, no. 4 (2021): 1–21. http://dx.doi.org/10.1145/3468062.

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Hierarchical organization is widely used in high-radix routers to enable efficient scaling to higher switch port count. A general-purpose hierarchical router must be symmetrically designed with the same input buffer depth, resulting in a large amount of unused input buffers due to the different link lengths. Sharing input buffers between different input ports can improve buffer utilization, but the implementation overhead also increases with the number of shared ports. Previous work allowed input buffers to be shared among all router ports, which maximizes the buffer utilization but also intro

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2

Dudin, Alexander, Olga Dudina, Sergei Dudin, and Agassi Melikov. "Analysis of a Queueing Model with Flexible Priority, Batch Arrival, and Impatient Customers." Computation 13, no. 3 (2025): 77. https://doi.org/10.3390/computation13030077.

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In this study, we consider a multi-server priority queueing model with batch arrivals of two types of customers, a finite buffer, and two input finite buffers for storing customers that cannot be admitted for service immediately upon arrival. The transition of a customer from an input buffer to the main buffer can occur after an exponentially distributed time. Customers residing in the input and main buffers are impatient. The four-dimensional Markov chain is used to describe the dynamics of the system under consideration. It is analyzed via the derivation of its generator and providing an eff

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3

Lanyi, S., and M. Pisani. "A high-input-impedance buffer." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 49, no. 8 (2002): 1209–11. http://dx.doi.org/10.1109/tcsi.2002.801287.

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4

Scheinhardt, Werner R. W., and Bert Zwart. "A TANDEM FLUID QUEUE WITH GRADUAL INPUT." Probability in the Engineering and Informational Sciences 16, no. 1 (2002): 29–45. http://dx.doi.org/10.1017/s0269964802161031.

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For a two-node tandem fluid model with gradual input, we compute the joint steady-state buffer-content distribution. Our proof exploits martingale methods developed by Kella and Whitt. For the case of finite buffers, we use an insightful sample-path argument to extend an earlier proportionality result of Zwart to the network case.

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5

Paik, Jung Hoon, and Chae Tak Lim. "The Analysis of Input Queueing Techniques on a Crosspoint Packet Switch." Journal of Circuits, Systems and Computers 07, no. 04 (1997): 319–31. http://dx.doi.org/10.1142/s0218126697000231.

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In this paper, an N × N input-buffered crosspoint packet switch which selects a Head of the Line, HOL, packet in contention randomly is analyzed with a new approach. The approach is based on both a Markov chain representation of the input buffer and the probability that a HOL packet is successfully served. The probability as a function of N is derived, and it makes it possible to express the average packet delay and the average number of packets in the buffer as a function of N. The new contention resolution policy based on the occupancy of the input buffer is also presented and analyzed with

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AZAROV, Olexiy, and Оlexiy STAKHOV. "PUSH-PULL VOLTAGE BUFFER DEVICES ON BIPOLAR TRANSISTORS." Herald of Khmelnytskyi National University. Technical sciences 311, no. 4 (2022): 18–22. http://dx.doi.org/10.31891/2307-5732-2022-311-4-18-22.

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The article proposes linear push-pull buffer devices on bipolar transistors. A highly linear push-pull voltage buffer device with parametric zero shift compensation is considered. A variant of the construction of a highly linear push-pull voltage buffer device on bipolar transistors with a minimum value of the input current is proposed. The purpose of the work is to minimize the additive error of the buffer device by significantly reducing the input current. Analytical relations are given that allow estimating the additive error of the zero shift. The schematic diagram of a two-stroke buffer d

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Tabash, I. K., M. A. Mamun, and A. Negi. "A Fuzzy Logic Based Network Congestion Control Using Active Queue Management Techniques." Journal of Scientific Research 2, no. 2 (2010): 273–84. http://dx.doi.org/10.3329/jsr.v2i2.2786.

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Conventional IP routers are passive devices that accept packets and perform the routing function on any input. Usually the tail-drop (TD) strategy is used where the input which exceeds the buffer capacity are simply dropped. In active queue management (AQM) methods routers manage their buffers by dropping packets selectively. We study one of the AQM methods called as random exponential marking (REM). We propose an intelligent approach to AQM based on fuzzy logic controller (FLC) to drop packets dynamically, keep the buffer size around desired level and also prevent buffer overflow. Our propose

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8

Prabhakar, Balaji, Nicholas Bambos, and T. S. Mountford. "The synchronization of Poisson processes and queueing networks with service and synchronization nodes." Advances in Applied Probability 32, no. 3 (2000): 824–43. http://dx.doi.org/10.1239/aap/1013540246.

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This paper investigates the dynamics of a synchronization node in isolation, and of networks of service and synchronization nodes. A synchronization node consists of M infinite capacity buffers, where tokens arriving on M distinct random input flows are stored (there is one buffer for each flow). Tokens are held in the buffers until one is available from each flow. When this occurs, a token is drawn from each buffer to form a group-token, which is instantaneously released as a synchronized departure. Under independent Poisson inputs, the output of a synchronization node is shown to converge we

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Prabhakar, Balaji, Nicholas Bambos, and T. S. Mountford. "The synchronization of Poisson processes and queueing networks with service and synchronization nodes." Advances in Applied Probability 32, no. 03 (2000): 824–43. http://dx.doi.org/10.1017/s0001867800010272.

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This paper investigates the dynamics of a synchronization node in isolation, and of networks of service and synchronization nodes. A synchronization node consists of M infinite capacity buffers, where tokens arriving on M distinct random input flows are stored (there is one buffer for each flow). Tokens are held in the buffers until one is available from each flow. When this occurs, a token is drawn from each buffer to form a group-token, which is instantaneously released as a synchronized departure. Under independent Poisson inputs, the output of a synchronization node is shown to converge we

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10

Zwart, A. P. "A fluid queue with a finite buffer and subexponential input." Advances in Applied Probability 32, no. 1 (2000): 221–43. http://dx.doi.org/10.1239/aap/1013540031.

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We consider a fluid model similar to that of Kella and Whitt [32], but with a buffer having finite capacity K. The connections between the infinite buffer fluid model and the G/G/1 queue established by Kella and Whitt are extended to the finite buffer case: it is shown that the stationary distribution of the buffer content is related to the stationary distribution of the finite dam. We also derive a number of new results for the latter model. In particular, an asymptotic expansion for the loss fraction is given for the case of subexponential service times. The stationary buffer content distrib

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Zwart, A. P. "A fluid queue with a finite buffer and subexponential input." Advances in Applied Probability 32, no. 01 (2000): 221–43. http://dx.doi.org/10.1017/s000186780000985x.

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We consider a fluid model similar to that of Kella and Whitt [32], but with a buffer having finite capacity K. The connections between the infinite buffer fluid model and the G/G/1 queue established by Kella and Whitt are extended to the finite buffer case: it is shown that the stationary distribution of the buffer content is related to the stationary distribution of the finite dam. We also derive a number of new results for the latter model. In particular, an asymptotic expansion for the loss fraction is given for the case of subexponential service times. The stationary buffer content distrib

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12

Bundalo, Z. V., and B. L. Dorić. "Three-state CMOS buffer with input hysteresis." Electronics Letters 24, no. 14 (1988): 885. http://dx.doi.org/10.1049/el:19880603.

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13

Chan, P. K., L. Siek, T. Lim, and M. K. Han. "Adaptive-biased buffer with low input capacitance." Electronics Letters 36, no. 9 (2000): 775. http://dx.doi.org/10.1049/el:20000644.

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14

Jiang, Fei, Heather E. Preisendanz, Tamie L. Veith, Raj Cibin, and Patrick J. Drohan. "Riparian buffer effectiveness as a function of buffer design and input loads." Journal of Environmental Quality 49, no. 6 (2020): 1599–611. http://dx.doi.org/10.1002/jeq2.20149.

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15

CITRO, R. "An Adaptive Dynamic Buffer Management (ADBM) Approach for Input Buffers in ATM Networks." IEICE Transactions on Communications E88-B, no. 3 (2005): 1084–96. http://dx.doi.org/10.1093/ietcom/e88-b.3.1084.

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16

Li, Shuo, Xiaomeng Zhang, and Saiyu Ren. "High Frequency Unity Gain Buffer in 90-nm CMOS Technology." Journal of Circuits, Systems and Computers 25, no. 07 (2016): 1650071. http://dx.doi.org/10.1142/s0218126616500717.

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A new unity gain buffer architecture is presented for on-chip CMOS mixed signal applications. The proposed two-stage common source active load (CSAL) buffer with source feedback offers improved performance compared to previously published source follower and source-coupled differential-pair-based unity gain buffers. A 90-nm CMOS design ([Formula: see text] equals 1.2[Formula: see text]V) of the buffer has the following performance parameters. With [Formula: see text]/[Formula: see text] of 10 fF/250 fF, [Formula: see text] is 4.4[Formula: see text]GHz, low frequency gain is 0.16[Formula: see t

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17

Xu, Zhuofan, Biao Hu, Tianxiang Wu, et al. "A 12-Bit 50 MS/s Split-CDAC-Based SAR ADC Integrating Input Programmable Gain Amplifier and Reference Voltage Buffer." Electronics 11, no. 12 (2022): 1841. http://dx.doi.org/10.3390/electronics11121841.

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This article describes an asynchronous split-CDAC-based SAR ADC with integrated input PGA and an RV-Buffer. The split CDAC structure not only reduces the area of the ADC, but also relieves the driving pressure of the input PGA and RV-Buffer. Using the input PGA instead of the traditional input buffer as the driving circuit of the ADC increases the dynamic input range of the ADC. The proposed on-chip RV-Buffer can provide 1.1 V positive and 0.1 V negative voltage, avoiding the disturbance caused by off-chip reference. This prototype is implemented in a 65 nm CMOS process and occupies an active

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18

Sequeira, Luis, Julián Fernández-Navajas, Jose Saldana, José Ramón Gállego, and María Canales. "Describing the Access Network by means of Router Buffer Modelling: A New Methodology." Scientific World Journal 2014 (2014): 1–9. http://dx.doi.org/10.1155/2014/238682.

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The behaviour of the routers’ buffer may affect the quality of service (QoS) of network services under certain conditions, since it may modify some traffic characteristics, as delay or jitter, and may also drop packets. As a consequence, the characterization of the buffer is interesting, especially when multimedia flows are transmitted and even more if they transport information with real-time requirements. This work presents a new methodology with the aim of determining the technical and functional characteristics of real buffers (i.e., behaviour, size, limits, and input and output rate) of a

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19

Li, Peng, Jonathan C. Beard, and Jeremy D. Buhler. "Deadlock-free buffer configuration for stream computing." International Journal of High Performance Computing Applications 31, no. 5 (2016): 441–50. http://dx.doi.org/10.1177/1094342016675679.

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Stream computing is a popular paradigm for parallel and distributed computing, where compute nodes are connected by first-in first-out data channels. Each channel can be considered as a concatenation of several data buffers, including an output buffer for the sender and an input buffer for the receiver. The configuration of buffer sizes impacts the performance as well as the correctness of the application. In this article, we focus on application deadlocks that are caused by incorrect configuration of buffer sizes. We describe three types of deadlock in streaming applications, categorized by h

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20

Huang, Xing Fa, Rong Bin Hu, and Liang Li. "A CMOS Input Buffer for High-Resolution A/D Converters with High Sampling Rates." Applied Mechanics and Materials 678 (October 2014): 497–500. http://dx.doi.org/10.4028/www.scientific.net/amm.678.497.

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With respect to the application of high-speed, high-resolution A/D converter, the design and implementation of a CMOS input buffer is introduced. The buffer features high-speed and high-linearity. Its performances have been verified in a 14-bit 250MSPS pipelined A/D converter which is developed in 0.18um CMOS-based process technology. The simulation shows that the SFDR of the buffer is up to 104dB at an input clock of 250MHz with an input signal of 25MHz.

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21

Yoo, Mookyoung, Kyeongsik Nam, Gyuri Choi, et al. "A Single-Bit Incremental Second-Order Delta-Sigma Modulator with Coarse-Fine Input Buffer." Applied Sciences 12, no. 22 (2022): 11651. http://dx.doi.org/10.3390/app122211651.

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This paper presents an incremental second-order delta-sigma modulator with a coarse-fine input buffer in 180-nm CMOS. The modulator’s architecture was implemented as a second-order cascade of integrators with a feedback structure. The switched-capacitor integrator was operated in discrete time, with high-gain amplifiers required to achieve improved performance during the integration phase. The amplifier comprised rail-to-rail input and gain-boosted cascode intermediate stages, thus achieving a high gain and wide input voltage range. The circuit adopts a coarse-fine buffer for higher performanc

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22

GRAMMATIKAKIS, MILTOS D., ERIC FLEURY, and MIRO KRAETZL. "CONTINUOUS ROUTING IN PACKET SWITCHES." International Journal of Foundations of Computer Science 09, no. 02 (1998): 121–37. http://dx.doi.org/10.1142/s0129054198000106.

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Considering continuous routing, we analyze the transient behavior of n×n routers with input buffering, split input buffering, output buffering, and central buffering with dedicated virtual circuits, one for each source-destination pair in a network. Assuming similar buffer space requirements, output buffering has the highest throughput. Split input buffering and central buffering have comparable performance; split input buffering slightly outperforms central buffering for large switches. Input buffering is known to saturate at packet generating rates above 0.586. By extending these models, two

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23

Alnasser, Emad. "A Novel High Input Impedance AC-Coupled Buffer." Communications on Applied Electronics 5, no. 4 (2016): 17–22. http://dx.doi.org/10.5120/cae2016652278.

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24

Kao, Tzu‐Cheng, Chung‐Yu Hung, Jian‐Hsing Lee, et al. "Failure mechanism for input buffer under CDM test." Electronics Letters 50, no. 9 (2014): 667–69. http://dx.doi.org/10.1049/el.2013.4094.

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25

Sasaki, Galen H. "Input buffer requirements for round robin polling systems." Performance Evaluation 18, no. 3 (1993): 237–61. http://dx.doi.org/10.1016/0166-5316(93)90019-q.

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26

Arslan, Emre. "A high performance differential input CMOS current buffer." AEU - International Journal of Electronics and Communications 82 (December 2017): 1–6. http://dx.doi.org/10.1016/j.aeue.2017.07.037.

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Zvyozdochkin, M. Yu, and V. V. Mironov. "Control of video buffering for videostreams decoded from cyclic structures." Teoriâ i sistemy upravleniâ, no. 2 (September 24, 2024): 143–53. http://dx.doi.org/10.31857/s0002338824020124.

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The article formulates a problem of compliance of time inter-frame delays via video frames decoding from input cyclic-structured video stream. Implementation of software buffer or buffers set is reviewed as a general approach to solving this problem. Some methods of implementation of such buffers for video processing and transmission systems are proposed. Experimental research of these methods is conducted; recommendations for use are offered.

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C.D., Jaidhar, and A. V. Reddy. "Efficient Variable Length Block Switching Mechanism." International Journal of Computers Communications & Control 2, no. 3 (2007): 269. http://dx.doi.org/10.15837/ijccc.2007.3.2359.

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Most popular and widely used packet switch architecture is the crossbar. Its attractive characteristics are simplicity, non-blocking and support for simultaneous multiple packet transmission across the switch. The special version of crossbar switch is Combined Input Crossbar Queue (CICQ) switch. It overcomes the limitations of un-buffered crossbar by employing buffers at each crosspoint in addition to buffering at each input port. Adoption of Crosspoint Buffer (CB) simplifies the scheduling complexity and adapts the distributed nature of scheduling. As a result, matching operation is not neede

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LU, CHIH-WEN. "LOW-POWER HIGH-SPEED CLASS-AB BUFFER AMPLIFIERS FOR LIQUID-CRYSTAL DISPLAY SIGNAL DRIVER APPLICATION." Journal of Circuits, Systems and Computers 11, no. 04 (2002): 427–44. http://dx.doi.org/10.1142/s0218126602000550.

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Two types of low-power, high-speed, but with a large input dynamic range and output swing class-AB output buffer amplifiers which are suitable for the liquid-crystal display signal driver application are proposed. The driving capabilities of the circuits are achieved by adding comparators which sense the rising and falling edges of the input waveform and then turn on an auxiliary driving transistor to help charging/discharging the output load. The auxiliary driving transistors stay at "off" in the stable state, thus drawing no static power. Hence, the buffers draw little current during static

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30

Yiannopoulos, Konstantinos, Kyriakos G. Vlachos, and Emmanouel Varvarigos. "Multiple-Input-Buffer and Shared-Buffer Architectures for Optical Packet- and Burst-Switching Networks." Journal of Lightwave Technology 25, no. 6 (2007): 1379–89. http://dx.doi.org/10.1109/jlt.2007.896804.

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31

Chan, F. T. S. "Evaluation of combined dispatching and routeing strategies for a flexible manufacturing system." Proceedings of the Institution of Mechanical Engineers, Part B: Journal of Engineering Manufacture 216, no. 7 (2002): 1033–46. http://dx.doi.org/10.1243/09544050260174229.

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This paper is concerned with the evaluation of combined dispatching and routeing strategies on the performance of a flexible manufacturing system. Three routeing policies: no alternative routeings, alternative routeings dynamic and alternative routeings planned are considered with four dispatching rules with finite buffer capacity. In addition, the effect of changing part mix ratios is also discussed. The performance measures considered are makespan, average machine utilization, average flow time and average delay at local input buffers. Simulation results indicate that the alternative routein

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32

Jaya R. Suryavanshi, Et al. "Round Robin based Arbitration Mechanism for Signaling Approach based Router Architecture." International Journal on Recent and Innovation Trends in Computing and Communication 11, no. 10 (2023): 1254–59. http://dx.doi.org/10.17762/ijritcc.v11i10.8666.

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In Network-on-Chip the effectiveness of the network resource allocation is demonstrated by the flow control mechanism. There are two types of flow control mechanisms: buffered and bufferless. Compared to buffered flow control methods, buffer less flow control mechanisms are easier to use, need less power, and take up less space. When there are congestion and resource conflicts, it experiences higher packet loss and packet misrouting inside the network. A good buffered control mechanism useful as it overcomes the limitations of buffer less mechanism. There are numerous buffered and bufferless f

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33

Yang, Shuna, and Norvald Stol. "A novel delay line buffering architecture for asynchronous optical packet switched networks." International Journal of Information, Communication Technology and Applications 1, no. 1 (2015): 69–82. http://dx.doi.org/10.17972/ajicta20151112.

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Optical buffering is one major challenge in realizing all-optical packet switching. In this paper we focus on a delay-line buffer architecture, named a Multiple-Input Single-Output (MISO) optical buffer, which is realized by cascaded fiber delay lines (FDLs). This architecture reduces the physical size of a buffer by up to an order of magnitude or more by allowing reuse of its delay line elements. We consider the MISO buffers in a network scenario where the incoming packets are asynchronous and of fixed length. A novel Markov model is developed to analyze the performance of our buffering schem

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34

Kisriani, Shinta, Eri Prasetyo Wibowo, Busono Soerowirdjo, Hamzah Afandi, and Veronica Ernita Kristianti. "A Comparison Study of Three of Input Buffer Designed Using 0.35µm CMOS Technology." Advanced Materials Research 646 (January 2013): 184–90. http://dx.doi.org/10.4028/www.scientific.net/amr.646.184.

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In memory device that is contained in the digital application, there is a sequence of input buffer.The input buffer’s function is to improve a digital signal and remove noise. The buffer circuit take these input signal with imperfections and convert them in to full digital logic levels by slicing the signals at correct levels which depends upon the switching point voltage. In this paper,using three topologies, that are NMOS, PMOS and Parallel input buffer. It would be present into design, simulation and analysis of all topologies input buffer. The result in this paper to determine the best of

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35

Jankowski, Mariusz, and Andrzej Napieralski. "High-voltage high input impedance unity-gain voltage buffer." Microelectronics Journal 44, no. 7 (2013): 576–85. http://dx.doi.org/10.1016/j.mejo.2013.03.006.

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36

Changsik Yoo, Min-Kyu Kim, and Wonchan Kim. "A static power saving TTL-to-CMOS input buffer." IEEE Journal of Solid-State Circuits 30, no. 5 (1995): 616–20. http://dx.doi.org/10.1109/4.384180.

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37

Kumar, R., V. K. Garg, and S. I. Marcus. "Finite buffer realization of input-output discrete-event systems." IEEE Transactions on Automatic Control 40, no. 6 (1995): 1042–53. http://dx.doi.org/10.1109/9.388681.

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38

Del Grosso, C., G. Antoniol, E. Merlo, and P. Galinier. "Detecting buffer overflow via automatic test input data generation." Computers & Operations Research 35, no. 10 (2008): 3125–43. http://dx.doi.org/10.1016/j.cor.2007.01.013.

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Azarov, Oleksiy, Maxim Obertyukh, Mikhailo Prokofiev, Aliya Kalizhanova, and Olena Kosaruk. "Push-pull voltage buffer with improved load capacity." Informatyka, Automatyka, Pomiary w Gospodarce i Ochronie Środowiska 15, no. 2 (2025): 100–103. https://doi.org/10.35784/iapgos.7257.

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The article considers a method of increasing the load capacity of high-linear push-pull voltage buffer devices built on bipolar transistors. Buffer devices are designed to match the impedance of the signal generator to the impedance of the load and are essentially power amplifiers and act as an impedance converter with high input and low output impedances with a voltage transfer factor as close to unity as possible. The most common is the construction of buffer devices based on operational amplifiers with deep feedback in the voltage follower mode. At the present time, special attention is als

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40

Kumar, Anuj, and Rabi N. Mahapatra. "An integrated scheduling and buffer management scheme for input queued switches with finite buffer space." Computer Communications 29, no. 1 (2005): 42–51. http://dx.doi.org/10.1016/j.comcom.2005.03.006.

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41

Liu, Jiajun, Mingchao Ma, Xin Liu, and Haokun Xu. "High-Voltage Cable Buffer Layer Ablation Fault Identification Based on Artificial Intelligence and Frequency Domain Impedance Spectroscopy." Sensors 24, no. 10 (2024): 3067. http://dx.doi.org/10.3390/s24103067.

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In recent years, the occurrence of high-voltage cable buffer layer ablation faults has become frequent, posing a serious threat to the safe and stable operation of cables. Failure to promptly detect and address such faults may lead to cable breakdowns, impacting the normal operation of the power system. To overcome the limitations of existing methods for identifying buffer layer ablation faults in high-voltage cables, a method for identifying buffer layer ablation faults based on frequency domain impedance spectroscopy and artificial intelligence is proposed. Firstly, based on the cable distri

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42

Zhang, Jianhua, and Guilong Ma. "A novel programmable wide swing buffer for OLED source driver." Journal of Physics: Conference Series 2810, no. 1 (2024): 012017. http://dx.doi.org/10.1088/1742-6596/2810/1/012017.

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Abstract This paper presents the design of an output buffer with DAC functionality, which meets the requirements of small size, low power consumption, and high precision for OLED source driver chips. The two-stage DAC has a smaller area compared to traditional resistor string DACs, providing higher precision grayscale voltages that better meet the requirements of display drivers. The buffer utilizes a rail-to-rail input stage and Class AB output stage to achieve a wide input-output voltage range. Cascode Miller compensation is employed to improve stability, and a programmable tail current sour

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Li, Liang, Xing Fa Huang, Ming Yuan Xu, Xiao Feng Shen, and Xi Chen. "A Novel Input Buffer Used for SHA-Less Pipeline ADC." Applied Mechanics and Materials 678 (October 2014): 501–4. http://dx.doi.org/10.4028/www.scientific.net/amm.678.501.

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This paper discussed a input buffer structure with replica load, analysed its theory of improving input signal linearity and decreasing distortion, gived some circuit embodiments, one of which was used for a 12-bit 500MSPS SHA-less ADC based on BiCMOS technolgy, Spurious Free Dynamic Range (SFDR) reached above 90dB with a 250MHz input signal.

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DEVILLERS, OLIVIER, and PHILIPPE GUIGUE. "THE SHUFFLING BUFFER." International Journal of Computational Geometry & Applications 11, no. 05 (2001): 555–72. http://dx.doi.org/10.1142/s021819590100064x.

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The complexity of randomized incremental algorithms is analyzed with the assumption of a random order of the input. To guarantee this hypothesis, the n data have to be known in advance in order to be mixed what contradicts with the on-line nature of the algorithm. We present the shuffling buffer technique to introduce sufficient randomness to guarantee an improvement on the worst case complexity by knowing only k data in advance. Typically, an algorithm with O(n2) worst-case complexity and O(n) or O(n log n) randomized complexity has an [Formula: see text] complexity for the shuffling buffer.

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Kuusemets, V., Ü. Mander, K. Lõhmus, and M. Ivask. "Nitrogen and phosphorus variation in shallow groundwater and assimilation in plants in complex riparian buffer zones." Water Science and Technology 44, no. 11-12 (2001): 615–22. http://dx.doi.org/10.2166/wst.2001.0888.

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The study of purification efficiency and nutrient assimilation in plants was made in two riparian buffer zones with a complex of wet meadow and grey alder (Alnus incana) stand. In the less polluted Porijõgi test site, the 31 m wide buffer zone removed 40% of total nitrogen (total-N) and 78% of total phosphorus (total-P), while a heavily polluted 51 m wide buffer zone in Viiratsi retained 85% of total-N and 84% of total-P. The input of nutrients and purification efficiency displayed a significant relationship. The total-N removal in buffer zone was negative when the input value was less than 0.

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Lee, Thomas Y. S. "Analysis of Single Buffer Random Polling System With State-Dependent Input Process and Server/Station Breakdowns." International Journal of Operations Research and Information Systems 9, no. 1 (2018): 22–50. http://dx.doi.org/10.4018/ijoris.2018010102.

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Models and analytical techniques are developed to evaluate the performance of two variations of single buffers (conventional and buffer relaxation system) multiple queues system. In the conventional system, each queue can have at most one customer at any time and newly arriving customers find the buffer full are lost. In the buffer relaxation system, the queue being served may have two customers, while each of the other queues may have at most one customer. Thomas Y.S. Lee developed a state-dependent non-linear model of uncertainty for analyzing a random polling system with server breakdown/re

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Gautam, N., V. G. Kulkarni, Z. Palmowski, and T. Rolski. "BOUNDS FOR FLUID MODELS DRIVEN BY SEMI-MARKOV INPUTS." Probability in the Engineering and Informational Sciences 13, no. 4 (1999): 429–75. http://dx.doi.org/10.1017/s026996489913403x.

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In this paper we consider an infinite buffer fluid model whose input is driven by independent semi-Markov processes. The output capacity of the buffer is a constant. We derive upper and lower bounds for the limiting distribution of the stationary buffer content process. We discuss examples and applications where the results can be used to determine bounds on the loss probability in telecommunication networks.

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48

Ott, Teunis J., and J. George Shanthikumar. "On a buffer problem for packetized voice with an N-periodic strongly interchangeable input process." Journal of Applied Probability 28, no. 3 (1991): 630–46. http://dx.doi.org/10.2307/3214497.

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Consider a slotted communication channel which carries packetized voice and which can transmit exactly one packet every timeslot. Assume that every conversation routed over this channel generates exactly one packet every N timeslots. We study, for the case of an infinite buffer and an N-periodic strongly interchangeable input process, buffer behavior and packet delays as functions of the number of calls routed over the channel, as long as that number is less than or equal to N. Among our results are a simple algorithm which computes the marginal distribution of the buffer content and an algori

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49

Ott, Teunis J., and J. George Shanthikumar. "On a buffer problem for packetized voice with an N-periodic strongly interchangeable input process." Journal of Applied Probability 28, no. 03 (1991): 630–46. http://dx.doi.org/10.1017/s0021900200042479.

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Abstract:

Consider a slotted communication channel which carries packetized voice and which can transmit exactly one packet every timeslot. Assume that every conversation routed over this channel generates exactly one packet every N timeslots. We study, for the case of an infinite buffer and an N-periodic strongly interchangeable input process, buffer behavior and packet delays as functions of the number of calls routed over the channel, as long as that number is less than or equal to N. Among our results are a simple algorithm which computes the marginal distribution of the buffer content and an algori

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50

Jing, Fan, Wang, et al. "Improved Optical Waveguide Microcantilever for Integrated Nanomechanical Sensor." Sensors 19, no. 19 (2019): 4346. http://dx.doi.org/10.3390/s19194346.

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This paper reports on an improved optical waveguide microcantilever sensor with high sensitivity. To improve the sensitivity, a buffer was introduced into the connection of the input waveguide and optical waveguide cantilever by extending the input waveguide to reduce the coupling loss of the junction. The buffer-associated optical losses were examined for different cantilever thicknesses. The optimum length of the buffer was found to be 0.97 μm for a cantilever thickness of 300 nm. With this configuration, the optical loss was reduced to about 40%, and the maximum sensitivity was more than tw

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