Relevant bibliographies by topics / Kogge Stone Adder

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Kogge Stone Adder'

Author: Grafiati
Published: 2 June 2025
Last updated: 31 July 2025

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Journal articles on the topic "Kogge Stone Adder"

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Yagain, Deepa, Vijaya Krishna A, and Akansha Baliga. "Design of High-Speed Adders for Efficient Digital Design Blocks." ISRN Electronics 2012 (September 26, 2012): 1–9. http://dx.doi.org/10.5402/2012/253742.

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The core of every microprocessor and digital signal processor is its data path. The heart of data-path and addressing units in turn are arithmetic units which include adders. Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are well suited for VLSI implementations. This paper involves the design and comparison of high-speed, parallel-prefix adders such as Kogge-Stone, Brent-Kung, Sklansky, and Kogge-Stone Ling adders. It is found that Kogge-Stone Ling adder performs much efficiently when compared to the other adders. Here, Kogge-Stone Ling adders and
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Aritra, Mitra, Bakshi Amit, Sharma Bhavesh, and Didwania Nilesh. "Design of a High Speed Adder." International Journal of Scientific & Engineering Research 6, no. 4 (2015): 918–21. https://doi.org/10.5281/zenodo.33243.

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In this paper we have compared different addition algorithms such as Ripple Carry Adder, Carry Save Adder, Carry Select Adder, Carry Look Ahead Adder & Kogge Stone Adder for different performance parameters i.e. Area Utilization, Speed of operation and Power Consumption. A high speed Adder is then designed by merging Kogge Stone & Carry Select Algorithms. The circuits have been designed using Verilog HDL & Synthesize using TSMC 180 nm standard cell. The performance parameters are obtained with the help of Cadence Encounter RTL Compiler.
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Kumar V G, Kiran, and Shantharama Rai C,. "Low Power High Speed Arithmetic Circuits." International Journal of Recent Technology and Engineering (IJRTE) 8, no. 2 (2019): 807–13. http://dx.doi.org/10.35940/ijrte.a1064.078219.

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In the Design of arithmetic circuits reducing area, high speed and power are the major areas in VLSI system design. In this paper parallel prefix adders like Kogge-stone adder, Breunt-Kung adder, Ladner-Fischer adder is designed .Radix-4 Booth multiplier is designed by using Kogge-Stone adder. 16 bit Vedic multiplier is done by using Urdhwa Triyambaka sutra .8bit Vedic division is implemented by using Crumbs method so as to reduce the area, LUT tables and increase the speed as well as to reduce the Power dissipiation. The design is synthesized using Xilinx ISE 14.1 design suite.
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Anagani, Vamsidhar, Kasi Geethanjali, Anusha Gorantla, and Annamreddy Devi. "An improved approximate parallel prefix adder for high performance computing applications: a comparative analysis." International Journal of Informatics and Communication Technology (IJ-ICT) 14, no. 2 (2025): 382. https://doi.org/10.11591/ijict.v14i2.pp382-392.

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Binary adders are fundamental in digital circuit designs, including digital signal processors and microprocessor data path units. Consequently, significant research has focused on improving adders’ power-delay efficiency. The carry tree adder (CTA) is alternatively referred to as the parallel prefix adder (PPA), is among the fastest adders, achieving superior performance in very large scale integrated (VLSI) implementations through efficient concurrent carry generation and propagation. This study introduces approximate PPAs (AxPPAs) by applying approximations in prefix operators (POs). Four ty
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S., Nithin, and Ramesh K.B. "Design of High Speed Carry Select Adder Using Kogge-Stone and Carry-Lookahead Adders." Recent Trends in Analog Design and Digital Devices 7, no. 3 (2024): 23–33. https://doi.org/10.5281/zenodo.13709580.

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<em>The adder is acknowledged as the fundamental component in various arithmetic and logical operations. In efforts to enhance operational efficiency, the Carry Select Adder (CSLA) has been devised. By integrating multiple high-speed adder logics within a conventional CSLA framework, operational speed is further enhanced. This study presents the design of a hybrid CSLA that amalgamates the advantages of both Kogge Stone Adder and Look Ahead Adder (CLA) methodologies to achieve superior performance. Kogge Stone Adder, distinguished for its rapid carry generation, is incorporated to bolster spee
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Naga Babu, Ch, P. Naga Siva Sai, Ch Priyanka, K. Hari Kishore, M. Bindu Bhargavi, and K. Karthik. "Comparative Analysis of High Speed Carry Skip Adders." International Journal of Engineering & Technology 7, no. 2.24 (2018): 121. http://dx.doi.org/10.14419/ijet.v7i2.24.12015.

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In this paper we compared a high speed carry skip adders by considering parameters such as area, LUT’S, delay, power. When compared to conventional CSKA and other adders. Here in this project in first stage CSKA designed by using multiplexer as skip logic so by using this speed gets increased by skipping of carry. so here area gets increased so to reduce area another hybrid variable latency carry skip adder(Brent-kung adder) is designed .here power utilization also gets decreased, speed gets increased, but some delay is produced here to overcome that we followed a another method called Kogge-S
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BKondalkar, Mangesh, Arunkumar P Chavan, and P. Narashimaraja. "Improved Fault Tolerant Sparse KOGGE Stone ADDER." International Journal of Computer Applications 75, no. 10 (2013): 36–41. http://dx.doi.org/10.5120/13150-0582.

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Swetha, Potharla, and R. Rajkumar. "A Novel Design of a 4 Bit Reversible ALU using Kogge Stone Adder." International Journal of Trend in Scientific Research and Development 1, no. 6 (2017): 1296–301. https://doi.org/10.31142/ijtsrd5758.

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Reversible circuits are one promising direction withapplications in the field of low power design or quantumcomputation. However, no real design flow for this new kind ofcircuits exists so far. Significant contributions have been madein the literature towards the design of reversible logic gatestructures and arithmetic units, however, there are not manyefforts directed towards the design of reversible ALUs. In thispaper, a novel programmable reversible Kogge Stone adder ispresented and verified, and its implementation in the design ofa reversible Arithmetic Logic Unit is demonstrated. Then,rev
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Mahammad, Masood Ahmad, Appala Raju Uppala, Suggala Ram Prasad, and Anusha Marouthu. "Performance analysis of parallel prefix adders developed with field programmable gate array technology." International Journal of Reconfigurable and Embedded Systems (IJRES) 14, no. 1 (2025): 109. https://doi.org/10.11591/ijres.v14.i1.pp109-116.

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In many digital systems like high-performance computing and digital signal processing, parallel prefix adders are vital. Field programmable gate array (FPGA) technology is a well-known platform for developing parallel prefix adders. FPGA performance depends on bit size of the adder, the adder structure chosen, and the implementation specifications. An examination of the performance and area of parallel prefix adders developed using FPGA technology is presented in this research work. We look into how different design factors, such as the adder structure and the number of input bits, affect the
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Mahammad, Masood Ahmad, Appala Raju Uppala, Ram Prasad Suggala, and Anusha Marouthu. "Performance analysis of parallel prefix adders developed with field programmable gate array technology." International Journal of Reconfigurable and Embedded Systems (IJRES) 14, no. 1 (2025): 109–16. https://doi.org/10.11591/ijres.v14.i1.pp109-116.

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In many digital systems like high-performance computing and digital signal processing, parallel prefix adders are vital. Field programmable gate array (FPGA) technology is a well-known platform for developing parallel prefix adders. FPGA performance depends on bit size of the adder, the adder structure chosen, and the implementation specifications. An examination of the performance and area of parallel prefix adders developed using FPGA technology is presented in this research work. We look into how different design factors, such as the adder structure and the number of input bits, affect the
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Dissertations / Theses on the topic "Kogge Stone Adder"

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Åslund, Anders. "Power Estimation of High Speed Bit-Parallel Adders." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2390.

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<p>Fast addition is essential in many DSP algorithms. Various structures have been introduced to speed up the time critical carry propagation. For high throughput applications, however, it may be necessary to introduce pipelining. In this report the power consumption of four different adder structures, with varying word length and different number of pipeline cuts, is compared. </p><p>Out of the four adder structures compared, the Kogge-Stone parallel prefix adder proves to be the best choice most of the time. The Brent-Kung parallel prefix adder is also a good choice, but the maximal throughp
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Book chapters on the topic "Kogge Stone Adder"

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Babu, Arava Rahim, Vikas Mittal, and Veeravasantarao Dandasi. "Vedic Multiplier Using Modified Kogge Stone Adder." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2025. https://doi.org/10.1007/978-981-97-7384-8_37.

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Dantla, Sudhakar Reddy, Prudhvi Tummala, Sarada Musala, and Satish Kanapala. "High-Speed Area Efficient Approximate Kogge–Stone Adder." In Lecture Notes in Networks and Systems. Springer Nature Singapore, 2024. https://doi.org/10.1007/978-981-97-1943-3_18.

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Srikanth, B., Dodda Sai Pranathi, Padmaraju Sai Kumar Raju, and Vemula Sarika. "Performance Analysis of Dadda Multiplier Using Kogge Stone Adder." In Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering. Springer Nature Switzerland, 2025. https://doi.org/10.1007/978-3-031-81171-5_3.

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Frustaci, Fabio, and Marco Lanuzza. "A New Optimized High-Speed Low-Power Data-Driven Dynamic (D3L) 32-Bit Kogge-Stone Adder." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-11802-9_40.

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Rajesh, Masarla, and B. Bala Tripura Sundari. "FPGA Implementation of Efficient 32-Bit 3-Operand Addition Using Kogge–Stone (KS) Parallel Prefix Adder." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-19-7753-4_22.

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Agarwal, Vipul, Gurrampati Preethi Reddy, and Guduru Balaji Induja. "Design and Implementation of Parallel Prefix Based 16-Bit Kogge Stone Adder for High-Speed Binary Addition." In Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering. Springer Nature Switzerland, 2025. https://doi.org/10.1007/978-3-031-77081-4_26.

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Raghav, Himadri Singh, Sachin Maheshwari, and B. Prasad Singh. "Performance Analysis of Subthreshold 32-Bit Kogge-Stone Adder for Worst-Case-Delay and Power in Sub-micron Technology." In Communications in Computer and Information Science. Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-42024-5_13.

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Lokesh Chowdary, M., A. Mallaiah, and A. Jaya Lakshmi. "Design of Wallace Tree Multiplier Using Sparse Kogge-Stone and Brent–Kung Adders." In Lecture Notes in Networks and Systems. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-8204-7_20.

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Conference papers on the topic "Kogge Stone Adder"

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K R, Kavitha, S. Vijayalakshmi, B. Murali Babu, Preetha K, and Nithyadevi S. "High-Performance Wallace Tree Multiplier with Kogge-Stone Adder." In 2024 International Conference on Sustainable Communication Networks and Application (ICSCNA). IEEE, 2024. https://doi.org/10.1109/icscna63714.2024.10864344.

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Shirahatti, Sunita, Sowmya R. Bangari, Deepika A. J, Haritha D, and Yashaswini B. M. "Reversible Logic based Kogge -Stone Adder: Implementation and Analysis." In 2025 4th International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE). IEEE, 2025. https://doi.org/10.1109/icdcece65353.2025.11035318.

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Shirahatti, Sunita, D. Haritha, P. Thejaswini, A. J. Deepika, and B. M. Yashaswini. "Performance Analysis of Vedic Multiplier using Kogge Stone Adder and Reversible Logic." In 2024 International Conference on Recent Advances in Science and Engineering Technology (ICRASET). IEEE, 2024. https://doi.org/10.1109/icraset63057.2024.10895585.

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Morasa, Balaji, N. Sai Bhagya Lakshmi, M. Kumar Sai, K. Monish, M. Thoushif Ahamed, and A. Yasmine Begum. "Optimized FIR Filter Design with RNS, Array Multiplier, And Kogge Stone Adder." In 2025 International Conference on Advances in Modern Age Technologies for Health and Engineering Science (AMATHE). IEEE, 2025. https://doi.org/10.1109/amathe65477.2025.11081269.

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Mohakud, Suvendu, Abhyarthana Bisoyi, and Aruna Tripathy. "Implementation of Low Power Kogge Stone Adder on Zynq 7000 SoC Evaluation Kit FPGA." In 2024 International Conference on Communication, Computing and Energy Efficient Technologies (I3CEET). IEEE, 2024. https://doi.org/10.1109/i3ceet61722.2024.10993684.

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Malagar, Suraj, Dinesha P, and Rohith S. "Implementation of a 16-bit Multiplier Leveraging the Kogge-Stone Adder With Memristor IMPLY Logic." In 2024 International Conference on Distributed Systems, Computer Networks and Cybersecurity (ICDSCNC). IEEE, 2024. https://doi.org/10.1109/icdscnc62492.2024.10939928.

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Bhat, Prathiksha R., and Krishnamurthy Nayak. "RTL to GDS II Simulation of SAD algorithm with Kogge stone adder using Cadence tools." In 2025 International Conference on Advances in Modern Age Technologies for Health and Engineering Science (AMATHE). IEEE, 2025. https://doi.org/10.1109/amathe65477.2025.11081257.

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Prasad, S. V. S., N. Shyam Sunder Sagar, M. V. Nitya Pushkala, Siddartha Silveri, Baindla Harshitha, and Sreeja Chenna. "Enhancing VLSI Performance: An Innovative Approach to 3-Parallel Polyphase Odd-Length FIR Filtering with Kogge-Stone Adder and Booth Multiplier." In 2024 International Conference on Electrical Electronics and Computing Technologies (ICEECT). IEEE, 2024. http://dx.doi.org/10.1109/iceect61758.2024.10739232.

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Shashikala, B. N., Pooja R, Pavan Prahallad, Ramya S K, and M. V. Ramyashree. "Design and implementation of Kogge-stone, Sparse Kogge-stone and Spanning tree adder." In 2023 International Conference on Smart Systems for applications in Electrical Sciences (ICSSES). IEEE, 2023. http://dx.doi.org/10.1109/icsses58299.2023.10200644.

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Anjana, R., B. Abishna, M. S. Harshitha, E. Abhishek, V. Ravichandra, and M. S. Suma. "Implementation of vedic multiplier using Kogge-stone adder." In 2014 International Conference on Embedded Systems (ICES). IEEE, 2014. http://dx.doi.org/10.1109/embeddedsys.2014.6953044.

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