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Journal articles on the topic 'Microprocessors'
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Bindu, A. "A rigorous approach to microprocessor verification using UVM." i-manager’s Journal on Electronics Engineering 13, no. 1 (2022): 39. http://dx.doi.org/10.26634/jele.13.1.19344.
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In today's fast-paced technology industry, microprocessors play an increasingly important role in a wide range of applications. However, verifying the correctness of complex microprocessor designs remains a significant challenge. To address this issue, a rigorous approach to microprocessor verification using the Universal Verification Methodology (UVM) is proposed. UVM provides a standardised and scalable approach to verifying digital designs, including microprocessors, and has been widely adopted in the industry. This research proposes a UVM-based verification framework for microprocessors that can identify and eliminate design errors early in the development cycle. The proposed approach covers functional verification, performance verification, and hardware-software co-verification. The effectiveness of the proposed approach is evaluated through a case study of a commercial microprocessor design, where the UVM-based verification framework successfully detected and resolved several design bugs. The results demonstrate the potential of the proposed rigorous approach to microprocessor verification using UVM to enhance the quality and reliability of microprocessor designs.
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Abdullayevich, Hakimov Zohid. "History, Structure And Types Of Microprocessors." American Journal of Interdisciplinary Innovations and Research 02, no. 11 (November 16, 2020): 39–46. http://dx.doi.org/10.37547/tajiir/volume02issue11-08.
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This article gives you a brief overview on microprocessor types, performance, and computer hardware. The article also provides basic concepts about Microprocessors. Learn about microprocessor types, Intel, Intel Celeron, VIA, NVIDIA, Elbrus, Philips, Hitachi, Sun, AMD Athlon and more. You will learn about the functional parts of the microprocessor, the block diagram of the microprocessor, the command register of the microprocessor.
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Приходько, Д. И. "Basic typing of multibit microprocessor in the structure of modern microprocessors." Vestnik of Russian New University. Series «Complex systems: models, analysis, management», no. 2 (July 8, 2023): 203–9. http://dx.doi.org/10.18137/rnu.v9187.23.02.p.203.
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Рассматриваются мультиразрядные микропроцессы – особый класс значительно улучшенных микропроцессоров, в которые встроены механизмы, отвечающие за повышение надежности работы программного обеспечения, запускаемого на данном микропроцессоре, – табличная структура регистров и система резервного копирования. Рассматривается месторасположение указанного микропроцессора и основные характеристики модельного ряда: система команд (самые популярные типы CISC и RISK), тип организации стэка (Неймана – Лебедева, гарвардская архитектура), тип распределения команд (статический или динамический). В качестве примера взят доработанный вариант микропроцессора AMD64, в котором применена табличная модель организации регистров и использовано резервное копирование. The article considers a special class of microprocessors – multi-bit microprocessors, which are significantly improved microprocessors. They have built-in mechanisms to improve the reliability of software running on a given microprocessor. The main ones are a tabular register structure, and a backup system. The location of the specified microprocessor and the main characteristics of the lineup are considered, which include the command system (the most popular CISC and RISK types), the type of stack organization (Neumann – Lebedev, Harvard architecture), the type of command distribution (static or dynamic). An example for an analysis will be a modified version of the AMD64 microprocessor, in which a tabular model of register organization is applied and backup is used.
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Yim, Joon-Seo, Chang-Jae Park, In-Cheol Park, and Chong-Min Kyung. "Design Verification of Complex Microprocessors." Journal of Circuits, Systems and Computers 07, no. 04 (August 1997): 301–18. http://dx.doi.org/10.1142/s021812669700022x.
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As the complexity of microprocessors increases, functional verification becomes more difficult and emerges as the bottleneck of the design cycle. In this paper, we suggest a functional verification methodology, especially for compatible microprocessor designs. To guarantee perfect compatibility with previous microprocessors, we developed three C models in different abstraction levels, i.e. Polaris, MCV and StreC. An instruction behavioral level C model (Polaris) is verified using the slowed-down PC. In the implemetation of micro-architecture, a micro-operational level model (MCV) and RTL model (StreC) are co-simulated with consistency checking between these two models. The simulation speed of C models makes it possible to test the "real-world" application programs on the RTL design with a software board model (VPC). To increase the confidence level of verifications, Profiler reports the verification coverage of the test program, which is fed-back to the automatic test program generator (Pandora). The Restartability feature also helps to significantly reduce the total simulation time. Using the proposed verification methodology, we designed and verified the HK486, an Intel 80486 pin-compatible microprocessor successfully.
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Mazlan, M., A. Rahim, Mohd Mustafa Al Bakri Abdullah, W. Razak, A. F. Zubair, Y. M. Najib, and A. Bakir Azman. "Thermal Management of Electronic Components by Using Computational Fluid Dynamic (CFD) Software, FLUENTTM in Several Material Applications (Epoxy, Composite Material & Nanosilver)." Advanced Materials Research 795 (September 2013): 141–47. http://dx.doi.org/10.4028/www.scientific.net/amr.795.141.
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This paper presents the thermal management of electronic components, microprocessor by using three dimensional numerical analysis of heat and fluid flow in computer. 3D model of microprocessors is built using GAMBIT and simulated using FLUENT software. The study was made for four microprocessors arranged in line under different types of materials, inlet velocities and package (chip) powers. The results are presented in terms of average junction temperature and thermal resistance of each package The junction temperature is been observed and it was found that the junction temperature of the microprocessors is not exceed 70o C. It also found that the (chip) powers and inlet velocities are the most important elements to control and manage the junction temperature. The strength of CFD software in handling heat transfer problems is proved to be excellent.
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Chertok, Nikita Dmitrievich, and Mikhail Mikhaylovich Chupilko. "Survey of Methods for Functional Online Testing of Microprocessors." Proceedings of the Institute for System Programming of the RAS 33, no. 6 (2021): 131–48. http://dx.doi.org/10.15514/ispras-2021-33(6)-9.
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Online testing is a process of functional verification of microprocessors produced in silicon or their FPGA-prototypes, i.e. post-silicon verification. This type of testing differs both from the manufacturing testing, aimed at checking the workability of manufactured chips (e.g., absence of physical defects, admissibility of physical characteristics) and from simulation-based pre-silicon functional verification of microprocessors models (where internal microprocessor signals are available for observing, and the execution process can be controlled). Post-silicon verification enables to rapidly run huge numbers of tests and detect bugs missed during pre-silicon functional verification. Tests for microprocessors are usually represented by executable programs. Accordingly, the main tasks of online testing are high-performance generation of test programs in the given ISA and creation of a test environment responsible for launching programs, assessing the correctness of their execution by a microprocessor, diagnosing errors, and interacting with the outside world. This paper examines the problems arising in the development of online testing systems (online test program generators), reviews existing solutions in this area, and, on the base on them, proposes a promising approach to organizing online testing.
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Moses, Melanie E., Stephanie Forrest, Alan L. Davis, Mike A. Lodder, and James H. Brown. "Scaling theory for information networks." Journal of The Royal Society Interface 5, no. 29 (May 9, 2008): 1469–80. http://dx.doi.org/10.1098/rsif.2008.0091.
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Networks distribute energy, materials and information to the components of a variety of natural and human-engineered systems, including organisms, brains, the Internet and microprocessors. Distribution networks enable the integrated and coordinated functioning of these systems, and they also constrain their design. The similar hierarchical branching networks observed in organisms and microprocessors are striking, given that the structure of organisms has evolved via natural selection, while microprocessors are designed by engineers. Metabolic scaling theory (MST) shows that the rate at which networks deliver energy to an organism is proportional to its mass raised to the 3/4 power. We show that computational systems are also characterized by nonlinear network scaling and use MST principles to characterize how information networks scale, focusing on how MST predicts properties of clock distribution networks in microprocessors. The MST equations are modified to account for variation in the size and density of transistors and terminal wires in microprocessors. Based on the scaling of the clock distribution network, we predict a set of trade-offs and performance properties that scale with chip size and the number of transistors. However, there are systematic deviations between power requirements on microprocessors and predictions derived directly from MST. These deviations are addressed by augmenting the model to account for decentralized flow in some microprocessor networks (e.g. in logic networks). More generally, we hypothesize a set of constraints between the size, power and performance of networked information systems including transistors on chips, hosts on the Internet and neurons in the brain.
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Wang, Xingyang, and Yutong Zhu. "Intelligent Art Design Management Based on Wireless Communication Microprocessor and Mobile Internet." Wireless Communications and Mobile Computing 2022 (May 18, 2022): 1–12. http://dx.doi.org/10.1155/2022/5012875.
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Art design management is the fusion of art design and business management and the collision between design management and other disciplines. In order to study art design management students in a scientific way, this article combines wireless communication microprocessors and mobile Internet to design a new art design management mode. This paper proposes the inspection technology and its algorithm description, combines the T2 microprocessor and the SOA service architecture of the mobile Internet, and then integrates the theoretical knowledge of art design management to build an intelligent art design management based on wireless communication microprocessors and mobile Internet model. Then this paper designs the finite impulse response (FIR) filter test experiment and the end-to-end delay test experiment. The data collected in the experiment is optimized for the new art design management mode, and the optimized mode is subjected to a control experiment and a favorable opinion survey analysis. The experimental results show that the art design management model based on wireless communication microprocessors and mobile Internet has increased the artistic creation ability by 21.78% compared with the traditional art design model; compared with the traditional art design management mode, the art design management mode based on wireless communication microprocessor and mobile Internet has improved the management ability by 10.61%.
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Tural Suleymanov, Kamaladdin Ramazanov, Tural Suleymanov, Kamaladdin Ramazanov. "MICROPROCESSORS AND DIGITAL COMPUTER TECHNOLOGIES: A COMPREHENSIVE OVERVIEW." PAHTEI-Procedings of Azerbaijan High Technical Educational Institutions 35, no. 12 (December 8, 2023): 122–31. http://dx.doi.org/10.36962/pahtei35122023-122.
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In the fast-paced world of technology, microprocessors and digital computer technologies play a vital role in powering the devices and systems we rely on every day. From smartphones and laptops to cars and industrial machinery, these technologies have revolutionized the way we live and work. In this comprehensive article, we will delve into the intricacies of microprocessors and digital computer technologies, exploring their history, functionality, and applications. Microprocessors and digital computer technologies play a significant role in the energy supply of the devices and systems we use daily in the rapidly evolving world of technology. These technologies transform and enhance various application areas, from smartphones to laptops, and from automobiles to industrial machinery. In this comprehensive article, we will provide an in-depth analysis of microprocessors and digital computer technologies. We will discuss their history, functionality, and recent applications, providing insights into the fascinating world of these technological marvels. The history of these technologies encompasses a range of developments, and their functionalities have evolved significantly. While microprocessors were initially used for basic calculations and data processing, they are now more complex and powerful than ever. We will provide a detailed description of the fundamental components and functions that constitute digital computers. The principles of operation, application fields, and prospects of these technologies are analyzed in detail. This article emphasizes the significance of microprocessors and digital computer technologies in the technological world and highlights the broader prospects of this field. These essential components of the technological world enhance our daily lives and work, making them more efficient and comfortable. Detailed information in this field serves as a valuable resource, providing insights into the development of technology and how it shapes our future. Therefore, let's delve into the fascinating world of microprocessors and digital computer technologies. Keywords: microprocessor, digital computer, modern technology, important components
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SAMEERA A'AMER ABDUL-KADER. "EMULATION OF THE MICROPROCESSOR INTEL 80386." Diyala Journal of Engineering Sciences 2, no. 1 (June 1, 2009): 13–34. http://dx.doi.org/10.24237/djes.2009.01102.
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Microprocessor simulation is one of the recent applications of computer design. It is used for emulating the microprocessors for some purposes such as; learning microprocessor structure and assembly language in laboratories in universities. In this research simulation for the microprocessor Intel 80386 was suggested, designed and implemented. Implementation was verified for some data transfer instructions like MOV instructions in deferent addressing modes. The designed simulation program was implemented using Visual Basic programming. Examples were tested successfully for some MOV instructions.
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Bekayev, Е., and А. Kaharman. "Features of analysis and selection of microprocessors in modern control systems." Q A Iasaýı atyndaǵy Halyqaralyq qazaq-túrіk ýnıversıtetіnіń habarlary (fızıka matematıka ınformatıka serııasy) 24, no. 1 (March 30, 2023): 139–53. http://dx.doi.org/10.47526/2023-1/2524-0080.13.
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The article discusses the results of a brief retrospective review of the current microprocessors in control systems and the main directions of their development. The main requirements and selection criteria presented at the stage of the microprocessor design process in modern control systems, classification and architectural features of microprocessors are described. In addition, the «pipeline» processing method for maximizing processor performance, features of the analysis and selection of microprocessors in modern control systems using various architectural solutions for the elimination of contradictions arising in it related to conflicts are studied. According to the «pipeline» principle, three main types of processor architecture (VLIW – Very Long Instruction Word) with superscalar and multiple computing devices working in parallel are defined - depending on data, management and structural conflicts. Therefore, their use in VLIW processors and the limitation of their application in the field of scientific research is justified, due to the fact that the source codes are transmitted in a «closed» form. The main advantage of superscalar microprocessors is the independence of program-executable codes from their structure and the possibility of their execution on any processor models. In addition, the features of the EPIC architecture are described, which combines the advantages of the two different architectural solutions considered.
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Fathia, Nurul Fitri, Ivan Hanafi, and Muhammad Rif’an. "Development of microprocessor learning media using zilog z-80 for vocational school students of electronic engineering expert program." Jurnal Pendidikan Vokasi 8, no. 3 (November 29, 2018): 238. http://dx.doi.org/10.21831/jpv.v8i3.20795.
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This development research aims to develop microprocessor learning media using Zilog Z80. The Learning Media quality is based on the following aspects: (1) media feasibility according to subject matter experts and media experts; (2) effective based on students ability test by pre test and post-test. The developed cycles and procedures refer to the ADDIE model (analysis, design, development, implementation, and evaluation). This development research produces learning media as microprocessor kits training and e-Learning namely “µProsessor” as learning support. Data analysis techniques to test the effectiveness of learning media using Paired Samples T-Test and Using a Likert scale to test the feasibility of learning media. The research results show that the feasibility of learning media is enough with a high score of above 88% and Paired Samples Test results for media effectiveness show an increase in the value of significant microprocessor capabilities. Measuring the improvement of the ability of students' microprocessors using N-gain (normalized gain). The results of the calculation of N-gain in the large group is 0.72 in the high category. Interpretation of the results of the research can be concluded that effective learning media as a learning media for microprocessors.
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DRACH, N., A. GEFFLAUT, P. JOUBERT, and A. SEZNEC. "ABOUT CACHE ASSOCIATIVITY IN LOW-COST SHARED MEMORY MULTI-MICROPROCESSORS." Parallel Processing Letters 05, no. 03 (September 1995): 475–87. http://dx.doi.org/10.1142/s0129626495000436.
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Sizes of on-chip caches on current commercial microprocessors range from 16 Kbytes to 36 Kbytes. These microprocessors can be directly used in the design of a low cost single-bus shared memory multiprocessors without using any second-level cache. In this paper, we explore the viability of such a multi-microprocessor. Simulations results clearly establish that performance of such a system will be quite poor if on-chip caches are direct-mapped. On the other hand, when the on-chip caches are partially associative, the achieved level of performance is quite promising. In particular, two recently proposed innovative cache structures, the skewed-associative cache organization and the semi-unified cache organization are shown to work fine.
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Zahid Nuri, Samad Yusifov, Zahid Nuri, Samad Yusifov. "MICROPROCESSOR MEMORY MANAGEMENT AND CONTROL DIRECTIVES FOR OPTIMAL PERFORMANCE." PAHTEI-Procedings of Azerbaijan High Technical Educational Institutions 35, no. 12 (November 8, 2023): 139–47. http://dx.doi.org/10.36962/pahtei35122023-139.
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Microprocessors are one of the most important components that underpin our digital world. These miniature-looking devices run all of our electronics and manage the basic functions of all kinds of devices. From computers, televisions, cars and smartphones, microprocessors play a key role in the operation of every technology device. The performance of microprocessors is determined by many factors, but one that plays an important role in providing the basic control of many devices is memory management and control directives. These directives and control method help to execute computer programs effectively and the advancement in technology is a major factor in the rapid execution of new programs. Memory management helps in how data is stored, retrieved, and retrieved after storage. These operations help ensure that programs run quickly and efficiently. The memory hierarchy is important in clarifying the structure and functions of memory and describes the functions of memory classifications such as cache, RAM, and virtual memory. Control directives regulate how computers execute their programs and ensure that programs function correctly. These directives help control the operation of programs and ensure that data is processed correctly. The review process and the role of supervisory directives are analyzed. This article describes the topics of microprocessor memory management and control directives in more detail and explains how to ensure optimal performance in the technology. Keywords: Microprocessor, Memory management, control directives, optimal performance, memory hierarchy, performance guidelines.
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Thangamuthu, Tamilarasi, Rajasekar Rathanasamy, Saminathan Kulandaivelu, Ravichandran Kuttiappan, Mohanraj Thangamuthu, Moganapriya Chinnasamy, and Velu Kaliyannan Gobinath. "Experimental investigation on the influence of carbon-based nanoparticle coating on the heat transfer characteristics of the microprocessor." Journal of Composite Materials 54, no. 1 (June 27, 2019): 61–70. http://dx.doi.org/10.1177/0021998319859926.
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In the current scenario, thermal management plays a vital role in electronic system design. The temperature of the electronic components should not exceed manufacturer-specified temperature levels in order to maintain safe operating range and service life. The reduction in heat build-up will certainly enhance the component life and reliability of the system. The aim of this research work is to analyze the effect of multi-walled carbon nanotube and graphene coating on the heat transfer capacity of a microprocessor used in personal computers. The performance of coating materials was investigated at three different usages of central processing unit. Multi-walled carbon nanotube-coated and graphene-coated microprocessors showed better enhancement in heat transfer as compared with uncoated microprocessors. Maximum decrease in heat build-up of 7 and 9℃ was achieved for multi-walled carbon nanotube-coated and graphene-coated microprocessors compared to pure substrate. From the results, graphene has been proven to be a suitable candidate for effective heat transfer compared to with multi-walled carbon nanotubes due to high thermal conductivity characteristics of the former compared to the latter.
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Petrov, I. A. "Development of memory controller for today’s Elbrus microprocessors." Radio industry (Russia) 29, no. 3 (August 21, 2019): 41–47. http://dx.doi.org/10.21778/2413-9599-2019-29-3-41-47.
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The introduction of a new generation of microprocessors that belong to the Elbrus family and involve the introduction of a network-on-chip, requires the development of efficient means of access to DDR random access memory channels for network nodes. The paper includes a solution to this issue related to the interaction between DDR4 RAM and Elbrus-16СВ, 16-core microprocessor, which demands higher standards of an available capacity and peak bandwidth of memory channels. When designing Elbrus-16CB microprocessor, higher energy efficiency and reliability are also between main objectives. When performing the tasks set, an important component was adaptation of the memory controller, successfully applied in the microprocessors produced by MCST JSC, to DDR4 3DS standard compliance, taken as a basis for the use in a number of recent developments. It provides a four-time higher available RAM capacity without a directly proportional growth of energy consumption. The paper includes a structure of the memory controller and made decisions. These make it possible to increase the target frequency in operations of the device by 30% up to 800 MHz and increase operation reliability of the memory channel.
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Walsemann, A., M. Karagounis, A. Stanitzki, and D. Tutsch. "STRV — a radiation hard RISC-V microprocessor for high-energy physics applications." Journal of Instrumentation 18, no. 02 (February 1, 2023): C02032. http://dx.doi.org/10.1088/1748-0221/18/02/c02032.
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Abstract While microprocessors are used in various applications, they are precluded from the use in high-energy physics applications due to the harsh radiation present. To overcome this limitation a microprocessor design must withstand high doses of radiation and mitigate radiation induced soft errors. A TMR protection scheme is applied to protect a RISC-V microprocessor core against these faults. The protection of the integrated SRAM by an independent scrubbing algorithm is discussed. Initial irradiation results and power consumption measurements of the radiation-resistant RISC-V microprocessor implemented in 65 nm CMOS technology are presented.
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Atluri, Vasudeva P., Ravi V. Mahajan, Priyavadan R. Patel, Debendra Mallik, John Tang, Vijay S. Wakharkar, Gregory M. Chrysler, Chia-Pin Chiu, Gaurang N. Choksi, and Ram S. Viswanath. "Critical Aspects of High-Performance Microprocessor Packaging." MRS Bulletin 28, no. 1 (January 2003): 21–34. http://dx.doi.org/10.1557/mrs2003.14.
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AbstractHistorically, the primary function of microprocessor packaging has been to facilitate electrical connectivity of the complex and intricate silicon microprocessor chips to the printed circuit board while providing protection to the chips from the external environment. However, as microprocessor performance continues to follow Moore's law, the package has evolved from a simple protective enclosure to a key enabler of performance. The art and science of semiconductor packaging has advanced radically over the past few decades as faster and more powerful microprocessors with tens of millions of transistors continue to be available, which require more signal and power input/output connections as well as greater power-dissipation capabilities. Key drivers for the development of packaging technologies include power delivery, thermal management, and interconnect scaling, in which the space transformation from fine-featured silicon interconnects to the relatively coarse features seen on motherboards has to be enabled by the package. These drivers, under constant market-driven cost pressure, have led to increased demands on new materials and new package architectures to enable silicon performance. Significant advances have already been made in the areas of heat dissipation, power delivery, high-speed signaling, and high-density interconnects. It is expected that the future evolution of microprocessors will be increasingly challenging in these areas. This article focuses on providing a broad perspective view of the evolution of microprocessor packaging and discusses future challenges.
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Bowen, Jonathan. "Microprocessors." Microprocessors and Microsystems 9, no. 8 (October 1985): 413–14. http://dx.doi.org/10.1016/0141-9331(85)90059-6.
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Sulaiman, Diary R. "Multi-objective Pareto front and particle swarm optimization algorithms for power dissipation reduction in microprocessors." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 6 (December 1, 2020): 6549. http://dx.doi.org/10.11591/ijece.v10i6.pp6549-6557.
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The progress of microelectronics making possible higher integration densities, and a considerable development of on-board systems are currently undergoing, this growth comes up against a limiting factor of power dissipation. Higher power dissipation will cause an immediate spread of generated heat which causes thermal problems. Consequently, the system's total consumed energy will increase as the system temperature increase.
High temperatures in microprocessors and large thermal energy of computer systems produce huge problems of system confidence, performance, and cooling expenses. Power consumed by processors are mainly due to the increase in number of cores and the clock frequency, which is dissipated in the form of heat and causes thermal challenges for chip designers. As the microprocessor’s performance has increased remarkably in
Nano-meter technology, power dissipation is becoming non-negligible. To solve this problem, this article addresses power dissipation reduction issues for high performance processors using multi-objective Pareto front (PF), and particle swarm optimization (PSO) algorithms to achieve power dissipation as a prior computation that reduces the real delay of a target microprocessor unit. Simulation is verified the conceptual fundamentals and optimization of joint body and supply voltages (Vth-VDD) which showing satisfactory findings.
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Vozniak, Oleksandr, Andrii Shtuts, and Mykhailo Zamrii. "COLLECTOR ENGINE CONTROL SYSTEM." ENGINEERING, ENERGY, TRANSPORT AIC, no. 2(113) (June 29, 2021): 57–66. http://dx.doi.org/10.37128/2520-6168-2021-2-7.
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One of the main features of the current stage of scientific and technological progress is the wider use of microelectronics in various sectors of the economy, which is constantly growing. The role of microelectronics in the development of social production is determined by its almost unlimited possibilities in solving various problems in all sectors of the economy, its profound impact on the culture and life of modern man. Particular attention is now paid to the introduction of microprocessors that solve the problem of automation of control of mechanisms, devices and equipment. Adapting the microprocessor to the conditions of a particular task is mostly done by developing appropriate software, which is then stored in program memory. Hardware adaptation in most cases is performed by connecting the necessary integrated circuits and I / O that meet the problem to be solved. In the given work the microprocessor system of regulation of turns of the collector motor of a direct current is developed. The microprocessor system is developed on the basis of the KM1816 BE 51 microprocessor using a DAC. The microprocessor program changes the engine speed in the range from 1000 to 3000 rpm. In microprocessor technology there is an independent class of large integrated circuits (BIS) - single-chip microcomputers (OMEOM), which are designed to "intellectualize" devices for various purposes. The architecture of single-chip microcomputers is the result of the evolution of microprocessors and microprocessor systems, due to the desire to significantly reduce their hardware costs and cost. Typically, these goals are achieved both by increasing the integration of the BIS and by finding a compromise between cost, hardware costs and technical characteristics of the OMEOM. Development of control systems on single-chip microcomputers is one of the most promising areas in the field of process automation, control and management.
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Приходько, Д. И., А. В. Мокряков, and В. В. Горшков. "Overview of the basic mechanisms of a multi-bit microprocessor compatible with the AMD64 architecture." Vestnik of Russian New University. Series «Complex systems: models, analysis, management», no. 4 (December 29, 2023): 147–62. http://dx.doi.org/10.18137/rnu.v9187.23.04.p.147.
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Представлены необходимые доработки для улучшения микропроцессоров, которые предназначены для эксплуатации вычислительных систем в различных экстремальных условиях окружающей среды, в частности в космосе. Рассмотрены технические аспекты процесса смены разрядности вычислений (режима работы) микропроцессора под воздействием агрессивной окружающей среды. Этот эффект направлен на повышение надежности работы микропроцессора; с этой целью рассмотрены механизмы микропроцессора, а также сопроцессора как одного из компонентов современных микропроцессоров. Также рассмотрен принцип динамического управления операциями чтения/записи в регистр и новые операции: понижение разрядности вычислений, что подразумевает смену режима работы микропроцессора, и снижения числа ядер – «логическое» изолирование поврежденного ядра в микропроцессоре от работающего функционала. Для сопроцессора предложен механизм раздельного хранения компонент чисел с плавающей точкой стандарта IEEE-754 и показаны способы его реализации. The article focuses on the necessary improvements to the microprocessors that are designed to operate computer systems in various extreme environmental conditions, especially space. Technical aspects of the process of changing the bit ratio (operating mode) of the microprocessor under the influence of aggressive environment are viewed. This effect is aimed at improving the reliability of the microprocessor, and for these purposes the mechanisms of the microprocessor as well as the coprocessor (as one of the components of modern microprocessors) are considered. The principle of dynamic control of read/write operations to the register is addressed, as well as new operations were considered - reducing the bit capacity of calculations, which implies changing the mode of operation of the microprocessor, and reducing the number of cores – “logical” isolation of the damaged core in the microprocessor from the operating functionality. A mechanism for separately storing floating point components of the IEEE-754 standard has been proposed for the coprocessor, and methods of implementation have been shown.
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Gabbay, Freddy, and Avi Mendelson. "Electromigration-Aware Memory Hierarchy Architecture." Journal of Low Power Electronics and Applications 13, no. 3 (July 11, 2023): 44. http://dx.doi.org/10.3390/jlpea13030044.
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New mission-critical applications, such as autonomous vehicles and life-support systems, set a high bar for the reliability of modern microprocessors that operate in highly challenging conditions. However, while cutting-edge integrated circuit (IC) technologies have intensified microprocessors by providing remarkable reductions in the silicon area and power consumption, they also introduce new reliability challenges through the complex design rules they impose, creating a significant hurdle in the design process. In this paper, we focus on electromigration (EM), which is a crucial factor impacting IC reliability. EM refers to the degradation process of IC metal nets when used for both power supply and interconnecting signals. Typically, EM concerns have been addressed at the backend, circuit, and layout levels, where EM rules are enforced assuming extreme conditions to identify and resolve violations. This study presents new techniques that leverage architectural features to mitigate the effect of EM on the memory hierarchy of modern microprocessors. Architectural approaches can reduce the complexity of solving EM-related violations, and they can also complement and enhance common existing methods. In this study, we present a comprehensive simulation analysis that demonstrates how the proposed solution can significantly extend the lifetime of a microprocessor’s memory hierarchy with minimal overhead in terms of performance, power, and area while relaxing EM design efforts.
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Ishihara, Hidenori, and Toshio Fukuda. "Micro Autonomous Robotic System." Journal of Robotics and Mechatronics 11, no. 5 (October 20, 1999): 443–47. http://dx.doi.org/10.20965/jrm.1999.p0443.
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Miniaturized autonomous robots have been developed by several research groups. The miniaturized autonomous robot is defined as a miniaturized closed-loop system with microprocessors, microactuators, and microsensors. We developed a micro autonomous robot (MARS) consisting of a microprocessor, microsensors, microactuators, communication units, and batteries. MARS controls itself by a downloaded program supplied through infrared communication. We demonstrate performance of MARS, and discuss system features.
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LI, YINGFENG, and LASZLO B. KISH. "HEAT, SPEED AND ERROR LIMITS OF MOORE'S LAW AT THE NANO SCALES." Fluctuation and Noise Letters 06, no. 02 (June 2006): L127—L131. http://dx.doi.org/10.1142/s0219477506003215.
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The evolution of microprocessor miniaturization and performance, often described by Moore's law [1, 2], is close to the saturation limit. This paper discusses the limitation of the evolution of performance and minimization process for high performance microprocessors related to noise and power dissipation. In particular, the predictions provided in a previous paper [3] are refined in order to take into account the increasing effect of leakage currents on power dissipation.
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Gong, Longyu. "Wireless Communication-Based Design and Implementation of Digital Protection Platform on Folk Art." Wireless Communications and Mobile Computing 2022 (February 11, 2022): 1–11. http://dx.doi.org/10.1155/2022/5819719.
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Numbers no longer only have a purely mathematical meaning but a code that can change the way of human existence, cognition, and thinking, and a basic element to convey information. With the advent of the “Internet+” era, the development of digital media technology, digitization, and informatization has been integrated into all walks of life and has a vital impact on the development of all walks of life, and also brought about the ideological change of fine arts. Nowadays, the digitization of fine arts is a new product of the computer age, and how to protect it is also an important topic. The continuous development of wireless mobile communications has promoted the rapid development of microprocessors. In this article, we will study the protective effect of microprocessors on the digitization of fine arts. This paper designs a microprocessor-based art digital protection website, with the purpose of preserving, inheriting, and disseminating folk art works through the website. The result of the experiment shows that the sampling rate of the microprocessor has reached the requirement of the signal. The largest number of users of the folk art digital website is young people aged 18–29, accounting for 32%; the highest average score for the website is those over 59 years old, with an average score of 90.
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Ma, Yi Fei. "Laser Far-Field Spot Test System." Advanced Materials Research 823 (October 2013): 331–34. http://dx.doi.org/10.4028/www.scientific.net/amr.823.331.
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Measurement of the energy distribution of laser spots is an effective way in characterizing and diagnosing laser beam quality. After comparing conventional direct-detection and indirect-detection methods, a novel direct-detection scheme, which is based on detector-array controlled by single-chip microprocessors, is proposed. On the basis of analyzing key technologies such as data transmission and optical-electrical conversion, a block diagram of the system is proposed. In this system, a distributed structure was adopted which was composed of a host PC, a main microprocessor and lower microprocessors. This system is capable of measuring the parameters of laser beam in outfield such as size and shape of the spot, the energy of pulse and its distribution etc. It is suitable for most of lasers with repetition rate ranging from single pulse to several hundred per second and different energy up to moderate-high level. The system is more accurate than any former systems.
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Sundararajan, D., M. Ahmad, and S. Ganesan. "Multi-microprocessors." IEEE Transactions on Circuits and Systems 32, no. 6 (June 1985): 620–22. http://dx.doi.org/10.1109/tcs.1985.1085751.
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Flynn, M. J., and R. I. Winner. "ASIC microprocessors." ACM SIGMICRO Newsletter 20, no. 3 (August 1989): 237–43. http://dx.doi.org/10.1145/75395.75425.
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ANTOSHCHENKOV, Roman, Anton NIKYFOROV, Galina CHEREVATENKO, and Viktor ANTOSHCHENKOV. "MICROPROCESSOR MEASURING SYSTEM FOR DYNAMICS AND ENERGY OF MOBILE MACHINES." Ukrainian Journal of Applied Economics 6, no. 4 (November 26, 2021): 241–48. http://dx.doi.org/10.36887/2415-8453-2021-4-29.
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The paper presents a synthesis of a microprocessor-based measuring system for the dynamics and energy of mobile machines. It was determined that the measuring systems used to study the operation of cars, tractors and machine-tractor units today are not able to measure many parameters of functioning in dynamics during the execution of technological processes in agriculture. The use of microprocessors changes the structure of the digital part of devices. Significant computing capabilities of microprocessors allow the use of more complex work algorithms. At the same time, the requirements for the analog part of the measuring device are reduced and high metrological and operational characteristics are ensured. Based on the microprocessor, a measuring system was created to determine the dynamic and traction-energy indicators of the functioning of mobile machines. The main element of this system is a computing module consisting of an STM32F407 microprocessor computing element that processes data from sensors and a microprocessor element for data collection and storage. A hard disk, solid-state drive or USB Flash drive is used as an information storage device. The computing module has a touch display for displaying parameters and controlling the measuring system, so it can be used without an external personal computer. The number and types of sensors with which the machine is equipped during testing depends on its type and parameters required for study. To determine the dynamics of the tractor or unit elements, an inertial measuring device is used, consisting of gyroscopes and acceleration sensors, the number of which depends on the number of tested elements. The measuring system of dynamic and energy parameters of tractors and machine-tractor units was used in the study of the KhTZ-242T wheeled tractor. The dependence of the traction force of the seeder and the spectral density was determined. The results of experimental studies proved the effectiveness of using a microprocessor measuring system during field and laboratory tests of tractors and machine-tractor units. Keywords: microprocessor, measuring system, tractor, experimental studies.
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Trofimov, V. E., A. L. Pavlov, and A. S. Storozhuk. "CFD-simulation of impact jet radiator for thermal testing of microprocessors." Технология и конструирование в электронной аппаратуре, no. 5-6 (2018): 30–36. http://dx.doi.org/10.15222/tkea2018.5-6.30.
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One of the final stages of microprocessor development is thermal testing. This procedure is performed on a special stand, the main element of which is a switching PCB with mounted microprocessor sockets, chipsets, interfaces, jumpers and other components which provide various modes of microprocessor operation. Changing the case temperature of the microprocessor is carried out typically using a thermoelectric module. The cold surface of the module with controlled temperature is in direct thermal contact with the microprocessor housing designed for cooler installation. On the hot surface of the module, the radiator is mounted which dissipates the total heat flux from the microprocessor and the module. High density PCB layout, the requirement of free access to the jumpers and interfaces, and the presence of numerous sensors restrict the space for radiator mounting and require the use of an extremely compact radiator, especially in air cooling conditions. One of possible solutions for this problem may be to reduce the area of the heat-transfer surfaces of the radiator due to a sharp growth of the heat transfer coefficient without increasing the air flow rate. A sharp growth of heat transfer coefficient of the radiator can be achieved by making several conic or combined conic-cylindrical dead-end cavities with extra finning in the heat-transfer surface. Such cavities should absorb the impact air jets. In this study, CFD simulation of such radiators has been conducted. It is determined that when the air velocity at the nozzle entrances is 50—100 m/s, the investigated designs of impact-jet radiators have a thermal resistance in the range of 0.5—2.2°Ñ/W. This is quite sufficient for the thermal testing of some types of microprocessors with setting a number of operational modes and performing of certain types of test computations. It is shown that the use of combined dead-end cavities with extra finning is the best of the considered solutions and allows for a sharp (up to 44%) intensification of heat transfer in the radiator in comparison with cylindrical dead-end cavities, but at a cost — the loss of air pressure increases up to 20%. As a result of the study, it was found that the impact-jet radiator with dead-end tapering cone shaped cavities and combined cone-cylinder shaped cavities with extra finning, can successfully solve the problem of heat removal from microprocessors during thermal testing. However, it should be noted, that such radiators have a high aerodynamic resistance and require a high pressure air source for operation.
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Sharma1, Nikhil. "The Future of Computing: Microprocessor Advancements in 2024." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 04 (April 13, 2024): 1–5. http://dx.doi.org/10.55041/ijsrem30690.
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In 2024, the microprocessor landscape witnessed a revolutionary shift, marked by cutting-edge advancements and transformative trends across various industries. The relentless pursuit of Moore's Law drove innovation, leading to the creation of highly efficient processors through state-of-the-art fabrication technologies. Embracing sub-3nm processes, semiconductor manufacturers enhanced performance metrics while reducing power consumption. The rise of heterogeneous computing architectures and specialized edge processors tailored for decentralized environments further diversified the microprocessor ecosystem, setting the stage for unprecedented levels of performance, efficiency, and adaptability. These developments not only shaped the future of computing but also underscored the pivotal role of microprocessors in driving digital innovation Keywords Artificial Intelligence (AI), Sports Bikes, Ride Quality, User Experience, Safety, Adaptive Cruise Control, Collision Avoidance Systems, Rider Safety, Engine Performance Improvements, Predictive Maintenance Algorithms, Bike Performance, Dependability, AI Driven Design Techniques Keywords: Microprocessor, Fabrication technologies, Sub-3nm processes, Microprocessor ecosystem.
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Khan, Fatima Hameed, Muhammad Adeel Pasha, and Shahid Masud. "Advancements in Microprocessor Architecture for Ubiquitous AI—An Overview on History, Evolution, and Upcoming Challenges in AI Implementation." Micromachines 12, no. 6 (June 6, 2021): 665. http://dx.doi.org/10.3390/mi12060665.
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Artificial intelligence (AI) has successfully made its way into contemporary industrial sectors such as automobiles, defense, industrial automation 4.0, healthcare technologies, agriculture, and many other domains because of its ability to act autonomously without continuous human interventions. However, this capability requires processing huge amounts of learning data to extract useful information in real time. The buzz around AI is not new, as this term has been widely known for the past half century. In the 1960s, scientists began to think about machines acting more like humans, which resulted in the development of the first natural language processing computers. It laid the foundation of AI, but there were only a handful of applications until the 1990s due to limitations in processing speed, memory, and computational power available. Since the 1990s, advancements in computer architecture and memory organization have enabled microprocessors to deliver much higher performance. Simultaneously, improvements in the understanding and mathematical representation of AI gave birth to its subset, referred to as machine learning (ML). ML includes different algorithms for independent learning, and the most promising ones are based on brain-inspired techniques classified as artificial neural networks (ANNs). ANNs have subsequently evolved to have deeper and larger structures and are often characterized as deep neural networks (DNN) and convolution neural networks (CNN). In tandem with the emergence of multicore processors, ML techniques started to be embedded in a range of scenarios and applications. Recently, application-specific instruction-set architecture for AI applications has also been supported in different microprocessors. Thus, continuous improvement in microprocessor capabilities has reached a stage where it is now possible to implement complex real-time intelligent applications like computer vision, object identification, speech recognition, data security, spectrum sensing, etc. This paper presents an overview on the evolution of AI and how the increasing capabilities of microprocessors have fueled the adoption of AI in a plethora of application domains. The paper also discusses the upcoming trends in microprocessor architectures and how they will further propel the assimilation of AI in our daily lives.
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Znamenskiy, D. V., and V. N. Kutsevol. "Development of a cycle-accurate simulator of the Elbrus processor core memory subsystem." Radio industry (Russia) 29, no. 2 (May 30, 2019): 17–27. http://dx.doi.org/10.21778/2413-9599-2019-29-2-17-27.
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Increasing complexity of modern microprocessors, combined with semiconductor technology progress slowdown, make a further increase in performance more difficult. Under these circumstances, the relevance of the performance estimations of prospective microprocessors by dint of cycle-accurate simulation prior to their production in silicon is of growing importance. The approach to implementation of cycle-accurate simulator of core memory subsystem for Elbrus architecture, controlled by the existing functional simulator of this architecture, is presented herein. The method for validation of a cycleaccurate simulator by comparison with modeling of the RTL description of the prospective microprocessor is considered. The data on the speed of the cycle-accurate simulator and the main optimization methods, which were used to achieve acceptable performance, are presented. The preliminary estimates of the impact on the performance of some changes in the prospective processor core, including the cache access latency and hardware support for virtualization, obtained with the help of the cycle-accurate simulator are given. These assessments are important for making architectural decisions when designing the prospective Elbrus architecture processors.
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Barbirotta, Marcello, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Marco Ottavi, and Mauro Olivieri. "Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core." Journal of Low Power Electronics and Applications 13, no. 1 (December 28, 2022): 2. http://dx.doi.org/10.3390/jlpea13010002.
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Functional safety is a key requirement in several application domains in which microprocessors are an essential part. A number of redundancy techniques have been developed with the common purpose of protecting circuits against single event upset (SEU) faults. In microprocessors, functional redundancy may be achieved through multi-core or simultaneous-multi-threading architectures, with techniques that are broadly classifiable as Double Modular Redundancy (DMR) and Triple Modular Redundancy (TMR), involving the duplication or triplication of architecture units, respectively. RISC-V plays an interesting role in this context for its inherent extendability and the availability of open-source microarchitecture designs. In this work, we present a novel way to exploit the advantages of both DMR and TMR techniques in an Interleaved-Multi-Threading (IMT) microprocessor architecture, leveraging its replicated threads for redundancy, and obtaining a system that can dynamically switch from DMR to TMR in the case of faults. We demonstrated the approach for a specific family of RISC-V cores, modifying the microarchitecture and proving its effectiveness with an extensive RTL fault-injection simulation campaign.
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XIA, XIAO XIN, and TENG TIOW TAY. "INTRA-APPLICATION ENERGY REDUCTION FOR MICROPROCESSOR LOW-POWER DESIGN." Journal of Circuits, Systems and Computers 18, no. 01 (February 2009): 181–98. http://dx.doi.org/10.1142/s0218126609005010.
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Energy consumption is one of the most important design constraints for modern microprocessors, and designers have proposed many energy-saving techniques. Looking beyond the traditional hardware low-power designs, software optimization is becoming a significant strategy for the microprocessor to lower its energy consumption. This paper describes an intra-application identification and reconfiguration mechanism for microprocessor energy reduction. Our mechanism employs a statistical sampling method during training runs to identify code sections among application that have appropriate IPC (Instructions per Cycle) values and could make contributions to program runtime energy reduction, and then profiles them to dynamically scale the voltage and frequency of the microprocessor at appropriate points during execution. In our simulation, our approach achieves energy savings by an average of 39% with minor performance degradation, compared to a processor running at a fixed voltage and speed.
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Li, Xin, and Meng Tian Rong. "Temperature Sensor Allocation Strategy and Full Thermal Reconstruction for Microprocessors." Applied Mechanics and Materials 380-384 (August 2013): 2986–89. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.2986.
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On-chip thermal sensors are employed by dynamic thermal management techniques to measure runtime thermal behavior of microprocessors so as to prevent the on-set of high temperatures. The allocation and the placement of thermal sensors directly impact the effectiveness of the dynamic thermal management mechanisms. In this paper, we propose systematic and effective strategies for determining the optimal locations for temperature sensors based on thermal gradient analysis to provide the trade-off between hot spot estimation and full thermal reconstruction. Experimental results indicate the superiority of our techniques and confirm that our proposed methods are able to create a sensor distribution for a given microprocessor architecture.
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Barajas Higuera, Julián Adolfo, José Miguel Rojas Quintero, and Carlos Abizahir Romero Araiza. "Revisión sistemática de literatura de las actuales tecnologías de los microprocesadores." Revista de Investigación en Tecnologías de la Información 12, no. 25 (June 2024): 38–47. http://dx.doi.org/10.36825/riti.12.25.004.
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This work analyzed the main factors, components, architecture, and instructions for microprocessors designed between 1970 and 2022. Although the way microprocessors are built has changed over the years, in work presented, we investigate the technological advancements of microprocessors and analyze which areas are implemented to automatize and make the processes most accessible.
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Nikolic, Goran, Bojan Dimitrijevic, Tatjana Nikolic, and Mile Stojcev. "Fifty years of microprocessor evolution: from single CPU to multicore and manycore systems." Facta universitatis - series: Electronics and Energetics 35, no. 2 (2022): 155–86. http://dx.doi.org/10.2298/fuee2202155n.
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Nowadays microprocessors are among the most complex electronic systems that man has ever designed. One small silicon chip can contain the complete processor, large memory and logic needed to connect it to the input-output devices. The performance of today's processors implemented on a single chip surpasses the performance of a room-sized supercomputer from just 50 years ago, which cost over $ 10 million [1]. Even the embedded processors found in everyday devices such as mobile phones are far more powerful than computer developers once imagined. The main components of a modern microprocessor are a number of general-purpose cores, a graphics processing unit, a shared cache, memory and input-output interface and a network on a chip to interconnect all these components [2]. The speed of the microprocessor is determined by its clock frequency and cannot exceed a certain limit. Namely, as the frequency increases, the power dissipation increases too, and consequently the amount of heating becomes critical. So, silicon manufacturers decided to design new processor architecture, called multicore processors [3]. With aim to increase performance and efficiency these multiple cores execute multiple instructions simultaneously. In this way, the amount of parallel computing or parallelism is increased [4]. In spite of mentioned advantages, numerous challenges must be addressed carefully when more cores and parallelism are used. This paper presents a review of microprocessor microarchitectures, discussing their generations over the past 50 years. Then, it describes the currently used implementations of the microarchitecture of modern microprocessors, pointing out the specifics of parallel computing in heterogeneous microprocessor systems. To use efficiently the possibility of multi-core technology, software applications must be multithreaded. The program execution must be distributed among the multi-core processors so they can operate simultaneously. To use multi-threading, it is imperative for programmer to understand the basic principles of parallel computing and parallel hardware. Finally, the paper provides details how to implement hardware parallelism in multicore systems.
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Khudaverdiyeva, Mahabbat. "MULTIPLICATIVE APPROXIMATION METHOD OF FUNCTIONAL DEPENDENCIES BY LINE SEGMENTS." Системи управління, навігації та зв’язку. Збірник наукових праць 2, no. 68 (June 7, 2022): 37–40. http://dx.doi.org/10.26906/sunz.2022.2.037.
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The article is devoted to the approximation problems of functional dependencies during conversions performed in intelligent measurement devices. Non-linearities are essential parts of most control processes and systems. When using a nonlinear transmitter with a conversion function in measurement information systems used in various fields, it is necessary to perform nonlinear functional conversion operations on numbers in microprocessors/microcontrollers during direct and indirect measurements. For this purpose, various approximation methods are used. The purpose of the approximation is to describe nonlinear functions in a simpler, more convenient way for utilization and calculations, with an insignificantly small loss of accuracy. Existent methods for linearization, although some of them are effective, can be burdensome for implementation in microprocessor-based systems. Here, one of the proposed methods for the approximation of nonlinear functional dependencies by line segments is proposed. In this method, the range of the argument changes in the function is divided into line segments, and the parts of the coordinate system bisector, remaining within the line segments of the function, is swapped to perform approximation. Having involved few simple mathematical operations, the proposed method can be implemented efficiently in microprocessors/microcontrollers to perform approximations in measurement systems.
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Li, Siwen. "Influence of Embedded Microprocessor Wireless Communication in the Ankle Joint Proprioception Training on the Prevention of Football Sports Injuries." Mobile Information Systems 2022 (May 17, 2022): 1–13. http://dx.doi.org/10.1155/2022/8996453.
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This study synthesizes the relevant publications on the therapy of horizontal joint destabilization of the functional ankle and investigates the effect of anterior motion ankle drills on the inability to cause ankle injuries in soccer teams. We chose university soccer teams as the study population and divided them into five men’s and five women’s squads and five control groups. Embedded microcontrollers are also called microcontrollers. Generally, we focus on a specific type of microprocessor center, integrating ROM/EPROM, RAM, Bus Logic, Timer/Counter, Watchdog, I/O, Serial Port, Pulse Width Modulation Output, A/D, D/A, and more. Functions and Devices. Representative embedded microcontrollers include PSIXA, 8051, MCS-251, MCS96/196/296, and C166/167. With the continuous improvement of the processor’s computing power and chip integration, the differences between embedded microprocessors and embedded microprocessors have further increased. Blurred. The test subjects experienced force testing and the trial subjects involved in ankle native sensory drilling. The experimental results show that the average direction has a statistically significant effect on the front, back, left, and right running ability, which increases significantly after 0.017, 0.032, and 0.043 P, respectively, providing a more scientific basis for preventing football injuries.
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Roska, T., and A. Rodriguez-Vazquez. "Toward visual microprocessors." Proceedings of the IEEE 90, no. 7 (July 2002): 1244–57. http://dx.doi.org/10.1109/jproc.2002.801453.
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Rajulu, R. Govinda. "32-Bit Microprocessors." IETE Journal of Education 27, no. 1 (January 1986): 18–34. http://dx.doi.org/10.1080/09747338.1986.11436094.
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Jamil, T. "Fifth-generation microprocessors." IEEE Potentials 15, no. 5 (1997): 33–35. http://dx.doi.org/10.1109/45.544039.
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Stanley, Robert C. "Microprocessors in brief." IBM Journal of Research and Development 29, no. 2 (March 1985): 110–31. http://dx.doi.org/10.1147/rd.292.0110.
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Standeven, J. "32 Bit Microprocessors." Electronics and Power 33, no. 10 (1987): 657. http://dx.doi.org/10.1049/ep.1987.0393.
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Seals, R. "16-Bit microprocessors." Microelectronics Journal 20, no. 3 (May 1989): 54. http://dx.doi.org/10.1016/0026-2692(89)90031-1.
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Rajaraman, V. "Multi-core microprocessors." Resonance 22, no. 12 (December 2017): 1175–92. http://dx.doi.org/10.1007/s12045-017-0580-0.
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Mateosian, R. "Microprocessors at 25." IEEE Micro 16, no. 2 (April 1996): 75. http://dx.doi.org/10.1109/mm.1996.491465.
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Gelsinger, P. P., P. A. Gargini, G. H. Parker, and A. Y. C. Yu. "Microprocessors circa 2000." IEEE Spectrum 26, no. 10 (October 1989): 43–47. http://dx.doi.org/10.1109/6.40684.
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