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Journal articles on the topic 'Multigate transistor'

Author: Grafiati

Published: 25 May 2024

Last updated: 19 July 2025

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1

Lee, Chi-Woo, Aryan Afzalian, Nima Dehdashti Akhavan, Ran Yan, Isabelle Ferain, and Jean-Pierre Colinge. "Junctionless multigate field-effect transistor." Applied Physics Letters 94, no. 5 (2009): 053511. http://dx.doi.org/10.1063/1.3079411.

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2

Martins, Rodrigo, Diana Gaspar, Manuel J. Mendes, et al. "Papertronics: Multigate paper transistor for multifunction applications." Applied Materials Today 12 (September 2018): 402–14. http://dx.doi.org/10.1016/j.apmt.2018.07.002.

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3

Jayachandran, Remya, Dhanaraj Jagalchandran, and Perinkolam Chidambaram Subramaniam. "Planar CMOS and multigate transistors based wide-band OTA buffer amplifiers for heavy resistance load." Facta universitatis - series: Electronics and Energetics 35, no. 1 (2022): 13–28. http://dx.doi.org/10.2298/fuee2201013j.

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Analog buffer amplifier configurations capable of driving heavy resistive load using different operational transconductance amplifier (OTA) are presented in this paper. The OTA CMOS buffer configurations are designed using 0.18 ?m SCL technology library in Cadence Virtuoso tool and multigate transistor OTA buffer in TCAD Sentaurus tool. CMOS OTA buffer configuration using simple OTA outperform the OTA buffer circuits using other OTAs in terms of power dissipation and stability. Measured results show that the OTA buffer circuit works well for resistive load below 100 ?. The gain tuning of up to

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4

Selvi, K. Kalai, K. S. Dhanalakshmi, and Kalaivani Kanagarajan. "Performance Estimation of Recessed Modified Junctionless Multigate Transistor." Journal of Nano- and Electronic Physics 14, no. 1 (2022): 01008–1. http://dx.doi.org/10.21272/jnep.14(1).01008.

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5

Kohda, S., K. Masuda, K. Matsuzawa, and Y. Kitano. "A giant chip multigate transistor ROM circuit design." IEEE Journal of Solid-State Circuits 21, no. 5 (1986): 713–19. http://dx.doi.org/10.1109/jssc.1986.1052599.

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6

Delgado-Notario, Juan A., Wojciech Knap, Vito Clericò, et al. "Enhanced terahertz detection of multigate graphene nanostructures." Nanophotonics 11, no. 3 (2022): 519–29. http://dx.doi.org/10.1515/nanoph-2021-0573.

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Abstract Terahertz (THz) waves have revealed a great potential for use in various fields and for a wide range of challenging applications. High-performance detectors are, however, vital for exploitation of THz technology. Graphene plasmonic THz detectors have proven to be promising optoelectronic devices, but improving their performance is still necessary. In this work, an asymmetric-dual-grating-gate graphene-terahertz-field-effect-transistor with a graphite back-gate was fabricated and characterized under illumination of 0.3 THz radiation in the temperature range from 4.5 K up to the room te

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7

Ono, Y., H. Inokawa, and Y. Takahashi. "Binary adders of multigate single-electron transistors: specific design using pass-transistor logic." IEEE Transactions on Nanotechnology 1, no. 2 (2002): 93–99. http://dx.doi.org/10.1109/tnano.2002.804743.

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8

Wahid, Syamsudin Nur. "SIMULASI KUANTUM TRANSISTOR EFEK MEDAN MULTI GERBANG (NWFET)." Jurnal Qua Teknika 7, no. 1 (2017): 53–64. http://dx.doi.org/10.35457/quateknika.v7i1.218.

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Makalah ini membahas metode numerik untuk simulasi kuantum satu dan dua dimensi dari nanowire multigate transistor efek medan. Perangkat dimodelkan berdasarkan teori massa efektif dan formalisme fungsi Green non-ekuilibrium. Simulasi terdiri dari solusi Poisson persamaan tiga dimensi, persamaan Schrodinger dua dimensi pada penampang lintang dan persamaan transport satu dimensi. Dijelaskan detail teknik numerik untuk setiap langkah-langkah simulasi.

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9

Wahid, Syamsudin Nur. "SIMULASI KUANTUM TRANSISTOR EFEK MEDAN MULTI GERBANG (NWFET)." JURNAL QUA TEKNIKA 7, no. 1 (2017): 53–64. http://dx.doi.org/10.30957/quateknika.v7i1.218.

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Makalah ini membahas metode numerik untuk simulasi kuantum satu dan dua dimensi dari nanowire multigate transistor efek medan. Perangkat dimodelkan berdasarkan teori massa efektif dan formalisme fungsi Green non-ekuilibrium. Simulasi terdiri dari solusi Poisson persamaan tiga dimensi, persamaan Schrodinger dua dimensi pada penampang lintang dan persamaan transport satu dimensi. Dijelaskan detail teknik numerik untuk setiap langkah-langkah simulasi.

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10

Н.А., Агафонов, Масальский Н.В., Осипов В.В. та Родителев А.В. "Проблемы моделирования переноса в квазипланарных КНИ КМОП нанотранзисторах". Труды НИИСИ РАН 8, № 5 (2018): 139–47. http://dx.doi.org/10.25682/niisi.2018.5.0021.

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Обсуждается возможность эффективного моделирования переноса носителей в квазипланарных КНИ МОП транзисторах. Выполнен анализ разнообразных конструкций транзисторов - от классической планарной схемы до трехмерных мультизатворных структур (двух-, трех- и четырех затворные) с учетом возможной асимметрии затвора и канала транзистора. По результатам исследования сформулированы требования к модели для реализации методики численного расчета переноса носителей в таких устройствах The possibility of effective simulation of transfer of carriers in quasiplanar SOI CMOS transistors is discussed. The analy

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11

Cheng, Hui-Wen, and Yiming Li. "Comparative Study of Multigate and Multifin Metal–Oxide–Semiconductor Field-Effect Transistor." Japanese Journal of Applied Physics 49, no. 4 (2010): 04DC09. http://dx.doi.org/10.1143/jjap.49.04dc09.

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12

Pandian, M. Karthigai, N. B. Balamurugan, and A. Pricilla. "Potential and Quantum Threshold Voltage Modeling of Gate-All-Around Nanowire MOSFETs." Active and Passive Electronic Components 2013 (2013): 1–9. http://dx.doi.org/10.1155/2013/153157.

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An improved physics-based compact model for a symmetrically biased gate-all-around (GAA) silicon nanowire transistor is proposed. Short channel effects and quantum mechanical effects caused by the ultrathin silicon devices are considered in modelling the threshold voltage. Device geometrics play a very important role in multigate devices, and hence their impact on the threshold voltage is also analyzed by varying the height and width of silicon channel. The inversion charge and electrical potential distribution along the channel are expressed in their closed forms. The proposed model shows exc

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13

Park, Jae-Hong, and Chul-Ju Kim. "A Study on the Fabrication of a Multigate/Multichannel Polysilicon Thin Film Transistor." Japanese Journal of Applied Physics 36, Part 1, No. 3B (1997): 1428–32. http://dx.doi.org/10.1143/jjap.36.1428.

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14

Othman, Noraini, Mohd Khairuddin Md Arshad, Syarifah Norfaezah Sabki, and U. Hashim. "Ultra-Thin Body and Buried Oxide (UTBB) SOI MOSFETs on Suppression of Short-Channel Effects (SCEs): A Review." Advanced Materials Research 1109 (June 2015): 257–61. http://dx.doi.org/10.4028/www.scientific.net/amr.1109.257.

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This paper reviews the different UTBB SOI MOSFET structures and their superiority in suppressing short-channel effects (SCEs). As the gate length (Lg), buried oxide thickness (TBOX) and silicon thickness (Tsi) are scaled down, the severity of SCEs becomes significant. The different UTBB SOI MOSFET device structures introduced to suppress these SCEs are discussed. The effectiveness of these structures in managing the associated SCEs such as drain-induced barrier lowering (DIBL), subthreshold swing (SS) and off-state leakage current (Ioff) is also presented. Further evaluations are made on other

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15

Bonnaud, Olivier, Peng Zhang, Emmanuel Jacques, and Régis Rogel. "(Invited) Vertical Channel Thin Film Transistor: Improvement Approach Similar to Multigate Monolithic CMOS Technology." ECS Transactions 37, no. 1 (2019): 29–37. http://dx.doi.org/10.1149/1.3600721.

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16

Jana, Biswabandhu, Anindya Jana, Jamuna Kanta Sing, and Subir Kumar Sarkar. "Performance of Multigate Single Electron Transistor in Wide Temperature Range and 22 nm Hybrid Technology." Journal of Nanoelectronics and Optoelectronics 9, no. 3 (2014): 357–62. http://dx.doi.org/10.1166/jno.2014.1595.

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17

Parkula, Vitaliy, Marcello Berto, Chiara Diacci, et al. "Harnessing Selectivity and Sensitivity in Electronic Biosensing: A Novel Lab-on-Chip Multigate Organic Transistor." Analytical Chemistry 92, no. 13 (2020): 9330–37. http://dx.doi.org/10.1021/acs.analchem.0c01655.

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18

Shao, Feng, Ping Feng, Changjin Wan, et al. "Multifunctional Logic Demonstrated in a Flexible Multigate Oxide-Based Electric-Double-Layer Transistor on Paper Substrate." Advanced Electronic Materials 3, no. 3 (2017): 1600509. http://dx.doi.org/10.1002/aelm.201600509.

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19

Kumar, Ravi, E. Sathish Kumar, S. Vijayalakshmi, et al. "Design and Analysis of Nanosheet Field-Effect Transistor for High-Speed Switching Applications." Journal of Nanomaterials 2023 (July 24, 2023): 1–7. http://dx.doi.org/10.1155/2023/6460617.

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Self-heating effects and short channel effects are unappealing side effects of multigate devices like gate-all-around nanowire-field-effect transistors (FETs) and fin FETs, limiting their performance and posing reliability difficulties. This paper proposes the use of the novel nanosheet FET (NsFET) for complementary metal-oxide semiconductor technology nodes that are changing. Design guidelines and basic measurements for the sub-nm node are displayed alongside a brief introduction to the roadmap to the sub-nm regime and electronic market. The device had an ION/IOFF ratio of more than 105, acco

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20

Yedukondalu, Udara, Vinod Arunachalam, Vasudha Vijayasri Bolisetty, and Ravikumar Guru Samy. "Fully synthesizable multi-gate dynamic voltage comparator for leakage reduction and low power application." Indonesian Journal of Electrical Engineering and Computer Science 28, no. 2 (2022): 716. http://dx.doi.org/10.11591/ijeecs.v28.i2.pp716-723.

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The paper presents the implementation of a standard cell multigate fully synthesizable rail-to-rail dynamic voltage comparator. The dynamic voltage comparator works on deep sub-threshold supply voltage VDD =0.3 V with common mode inputs. The common-mode input range is VDD/2 with minimum input offset voltage ranging between 8mV to 28mV. Thus the circuit is simulated at 180nm Complementary Metal-Oxide Semiconductor (CMOS) process. Hence the dynamic voltage comparator has measured and tabulated by corresponding output voltage, power dissipation. But the performance of CMOS device is not good when

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21

Yedukondalu, Udara, Vinod Arunachalam, Vasudha Vijayasri Bolisetty, and Ravikumar Guru Samy. "Fully synthesizable multi-gate dynamic voltage comparator for leakage reduction and low power application." Indonesian Journal of Electrical Engineering and Computer Science 28, no. 2 (2022): 716–23. https://doi.org/10.11591/ijeecs.v28.i2.pp716-723.

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The paper presents the implementation of a standard cell multigate fully synthesizable rail-to-rail dynamic voltage comparator. The dynamic voltage comparator works on deep sub-threshold supply voltage VDD =0.3 V with common mode inputs. The common-mode input range is VDD/2 with minimum input offset voltage ranging between 8mV to 28mV. Thus the circuit is simulated at 180nm complementary metal-oxide semiconductor (CMOS) process. Hence the dynamic voltage comparator has measured and tabulated by corresponding output voltage, power dissipation. But the performance of CMOS device is not good when

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22

Harirajkumar, J., and R. Shivakumar. "Enhancing Analog Performance in Nanometer FinFET Technology: Bridging the Device-Circuit Co-Design Gap for Low-Power Applications." Journal of Nanoelectronics and Optoelectronics 19, no. 12 (2024): 1277–87. https://doi.org/10.1166/jno.2024.3692.

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In modern electronics and communication systems, the major driving force have been primarily based on down-scaling the minimum transistor size according to Moore0 s law. Furthermore, the efforts to overcome limitations of planar technology have led to development of non-traditional architecture such as Fin shaped Field Effect Transistor (FinFET) and other Multigate devices to achieve compactness. A FinFET, self-aligned process is more resilient to short channel effects in nanometer technology node. In addition to the non-planar nature of multi-gate devices, several technology integration chall

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23

N., M. Shehu G. Babaji M. H. Ali. "Exploring the Influence of Channel Doping Concentration on Short Channel Effects in Nanoscale Double-Gate FinFETs: A Comparative Study." Journal of Science and Technology Research 6, no. 1 (2024): 182–89. https://doi.org/10.5281/zenodo.10969362.

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<em>This work investigates the impact of channel doping concentration on short channel effects (SCEs) in different semiconductor materials using FinFETs. The work examines Gallium Arsenide (GaAs), Gallium Antimonide (GaSb), Gallium Nitride (GaN), and Silicon (Si) FinFETs in the PADRE simulator environment which is a powerful component from Multigate Field Effect Transistor (MUGFET) tool readily available at nanoHUB.org, analyzing performance metrics such as Drain Induced Barrier Lowering (DIBL), Subthreshold Swing (SS), Threshold Voltage roll-off, transconductance as well as on-current. It is

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24

Saha, Priyanka, Rudra Sankar Dhar, Swagat Nanda, Kuleen Kumar, and Moath Alathbah. "The Optimization and Analysis of a Triple-Fin Heterostructure-on-Insulator Fin Field-Effect Transistor with a Stacked High-k Configuration and 10 nm Channel Length." Nanomaterials 13, no. 23 (2023): 3008. http://dx.doi.org/10.3390/nano13233008.

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The recent developments in the replacement of bulk MOSFETs with high-performance semiconductor devices create new opportunities in attaining the best device configuration with drive current, leakage current, subthreshold swing, Drain-Induced Barrier Lowering (DIBL), and other short-channel effect (SCE) parameters. Now, multigate FETs (FinFET and tri-gate (TG)) are advanced methodologies to continue the scaling of devices. Also, strain technology is used to gain a higher current drive, which raises the device performance, and high-k dielectric material is used to minimize the subthreshold curre

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25

A.H Afifah Maheran, M. Pritigavane, N.H.N.M. Nizam, F. Salehuddin, and N. Sabani. "Taguchi Method Statistical Analysis on Characterization and Optimization of 18-nm Double Gate MOSFETs." International Journal of Nanoelectronics and Materials (IJNeaM) 17, no. 4 (2024): 549–55. http://dx.doi.org/10.58915/ijneam.v17i4.1282.

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A bi-layer graphene with a multigate structure was intensified and analysed on an 18-nm Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) device to obtain an optimal performance parameter. The device has a gate structure made of Titanium Dioxide (TiO2) that serves as a high-k material and a metal gate made of Tungsten Silicide (WSix). The Silvaco TCAD Software which are ATHENA and ATLAS modules were used to enhance the fabrication process of virtual devices and to verify the electrical properties of a specific device. According to the International Technology Roadmap Semiconductor (IT

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26

Łukasiak, Lidia, and Andrzej Jakubowski. "History of Semiconductors." Journal of Telecommunications and Information Technology, no. 1 (June 26, 2023): 3–9. http://dx.doi.org/10.26636/jtit.2010.1.1015.

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The history of semiconductors is presented beginning with the first documented observation of a semiconductor effect (Faraday), through the development of the first devices (point-contact rectifiers and transistors, early field-effect transistors) and the theory of semiconductors up to the contemporary devices (SOI and multigate devices).

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27

Lee, Chi-Woo, Isabelle Ferain, Aryan Afzalian, et al. "Performance estimation of junctionless multigate transistors." Solid-State Electronics 54, no. 2 (2010): 97–103. http://dx.doi.org/10.1016/j.sse.2009.12.003.

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28

Lee, Chi-Woo, Alexei N. Nazarov, Isabelle Ferain, et al. "Low subthreshold slope in junctionless multigate transistors." Applied Physics Letters 96, no. 10 (2010): 102106. http://dx.doi.org/10.1063/1.3358131.

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29

Jang, Doyoung, Jae Woo Lee, Chi-Woo Lee, et al. "Low-frequency noise in junctionless multigate transistors." Applied Physics Letters 98, no. 13 (2011): 133502. http://dx.doi.org/10.1063/1.3569724.

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30

Ferain, Isabelle, Cynthia A. Colinge, and Jean-Pierre Colinge. "Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors." Nature 479, no. 7373 (2011): 310–16. http://dx.doi.org/10.1038/nature10676.

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31

Song, Yi, and Xiuling Li. "Scaling junctionless multigate field-effect transistors by step-doping." Applied Physics Letters 105, no. 22 (2014): 223506. http://dx.doi.org/10.1063/1.4902864.

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32

Pan, Andrew, Songtao Chen, and Chi On Chui. "Electrostatic Modeling and Insights Regarding Multigate Lateral Tunneling Transistors." IEEE Transactions on Electron Devices 60, no. 9 (2013): 2712–20. http://dx.doi.org/10.1109/ted.2013.2272040.

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33

Prasad, Divya, Ahmet Ceyhan, Chenyun Pan, and Azad Naeemi. "Adapting Interconnect Technology to Multigate Transistors for Optimum Performance." IEEE Transactions on Electron Devices 62, no. 12 (2015): 3938–44. http://dx.doi.org/10.1109/ted.2015.2487888.

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34

Hofheinz, M., X. Jehl, M. Sanquer, et al. "Measurement of Capacitances in Multigate Transistors by Coulomb Blockade Spectroscopy." IEEE Transactions on Nanotechnology 7, no. 1 (2008): 74–78. http://dx.doi.org/10.1109/tnano.2007.908683.

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35

Aldegunde, Manuel, Antonio Jesus Garcia-Loureiro, and Karol Kalna. "3D Finite Element Monte Carlo Simulations of Multigate Nanoscale Transistors." IEEE Transactions on Electron Devices 60, no. 5 (2013): 1561–67. http://dx.doi.org/10.1109/ted.2013.2253465.

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36

Shin, Mincheol. "Three-dimensional quantum simulation of multigate nanowire field effect transistors." Mathematics and Computers in Simulation 79, no. 4 (2008): 1060–70. http://dx.doi.org/10.1016/j.matcom.2007.10.007.

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37

Xie, Dingdong, Jie Jiang, Wennan Hu, et al. "Coplanar Multigate MoS2 Electric-Double-Layer Transistors for Neuromorphic Visual Recognition." ACS Applied Materials & Interfaces 10, no. 31 (2018): 25943–48. http://dx.doi.org/10.1021/acsami.8b07234.

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38

Bradford, T., and S. P. McAlister. "The use of multiple-gated MOSFETs in a simple application." Canadian Journal of Physics 74, S1 (1996): 182–85. http://dx.doi.org/10.1139/p96-855.

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We describe the design and simulation of the use of neuron MOSFETs in a simple application — that of a parallel-carry adder circuit. The neuron MOSFETs are multigated MOSFETs where the multiple coupling to a MOSFET's gate is made capacitatively. By using such devices a multilevel logic is achieved that allows functions in a circuit to be achieved with fewer transistors than in a conventional CMOS design.

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39

Jung, Doohwan, Huan Zhao, and Hua Wang. "A CMOS Highly Linear Doherty Power Amplifier With Multigated Transistors." IEEE Transactions on Microwave Theory and Techniques 67, no. 5 (2019): 1883–91. http://dx.doi.org/10.1109/tmtt.2019.2899596.

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40

Lou, Haijun, Dan Li, Yan Dong, et al. "Effects of Fin Sidewall Angle on Subthreshold Characteristics of Junctionless Multigate Transistors." Japanese Journal of Applied Physics 52, no. 10R (2013): 104302. http://dx.doi.org/10.7567/jjap.52.104302.

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41

Zhang, Dongli, Mingxiang Wang, Huaisheng Wang, and Yilin Yang. "Enhanced Negative Bias Stress Degradation in Multigate Polycrystalline Silicon Thin-Film Transistors." IEEE Transactions on Electron Devices 64, no. 10 (2017): 4363–67. http://dx.doi.org/10.1109/ted.2017.2737489.

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42

Takahashi, Yasuo, Akira Fujiwara, Kenji Yamazaki, Hideo Namatsu, Kenji Kurihara, and Katsumi Murase. "Multigate single-electron transistors and their application to an exclusive-OR gate." Applied Physics Letters 76, no. 5 (2000): 637–39. http://dx.doi.org/10.1063/1.125843.

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43

Lou, Haijun, Baili Zhang, Dan Li, Xinnan Lin, Jin He, and Mansun Chan. "Suppression of subthreshold characteristics variation for junctionless multigate transistors using high-k spacers." Semiconductor Science and Technology 30, no. 1 (2014): 015008. http://dx.doi.org/10.1088/0268-1242/30/1/015008.

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44

Ranjan, Akhil, Ravikiran Lingaparthi, Nethaji Dharmarasu, and K. Radhakrishnan. "Enhanced NO2 Gas Sensing Performance of Multigate Pt/AlGaN/GaN High Electron Mobility Transistors." Journal of The Electrochemical Society 168, no. 4 (2021): 047502. http://dx.doi.org/10.1149/1945-7111/abed42.

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45

Colinge, Jean-Pierre, Aryan Afzalian, Chi-Woo Lee, Ran Yan, and Nima Dehdashti Akhavan. "Influence of carrier confinement on the subthreshold swing of multigate silicon-on-insulator transistors." Applied Physics Letters 92, no. 13 (2008): 133511. http://dx.doi.org/10.1063/1.2907330.

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46

Chen, Lun-Chun, Yu-Ru Lin, Yu-Shuo Chang, and Yung-Chun Wu. "High-Performance Stacked Double-Layer N-Channel Poly-Si Nanosheet Multigate Thin-Film Transistors." IEEE Electron Device Letters 38, no. 9 (2017): 1256–58. http://dx.doi.org/10.1109/led.2017.2725325.

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47

Tae Park, Jong, Jin Young Kim, and Jean Pierre Colinge. "Negative-bias-temperature-instability and hot carrier effects in nanowire junctionless p-channel multigate transistors." Applied Physics Letters 100, no. 8 (2012): 083504. http://dx.doi.org/10.1063/1.3688245.

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48

Garcia-Loureiro, Antonio J., Natalia Seoane, Manuel Aldegunde, et al. "Implementation of the Density Gradient Quantum Corrections for 3-D Simulations of Multigate Nanoscaled Transistors." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30, no. 6 (2011): 841–51. http://dx.doi.org/10.1109/tcad.2011.2107990.

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49

Elmessary, Muhammad A., Daniel Nagy, Manuel Aldegunde, et al. "Anisotropic Quantum Corrections for 3-D Finite-Element Monte Carlo Simulations of Nanoscale Multigate Transistors." IEEE Transactions on Electron Devices 63, no. 3 (2016): 933–39. http://dx.doi.org/10.1109/ted.2016.2519822.

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50

Chao Lu, A. V. H. Pham, M. Shaw, and C. Saint. "Linearization of CMOS Broadband Power Amplifiers Through Combined Multigated Transistors and Capacitance Compensation." IEEE Transactions on Microwave Theory and Techniques 55, no. 11 (2007): 2320–28. http://dx.doi.org/10.1109/tmtt.2007.907734.

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