Relevant bibliographies by topics / Nonbinary low-density parity check (LDPC) decoder

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Academic literature on the topic 'Nonbinary low-density parity check (LDPC) decoder'

Author: Grafiati
Published: 14 March 2023
Last updated: 31 July 2025

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Journal articles on the topic "Nonbinary low-density parity check (LDPC) decoder"

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Ramachandran, Varatharajan. "An Efficient VLSI Architecture for Nonbinary LDPC Decoder with Adaptive Message Control." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 1 (2015): 6. http://dx.doi.org/10.11591/ijres.v4.i1.pp6-12.

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<p>A new decoder architecture for nonbinary low-density parity check (LDPC) codes is presented in this paper to reduce the hardware operational complexity and power consumption. Adaptive message control (AMC) is to achieve the low decoding complexity, that dynamically trims the message length of belief information to reduce the amount of memory accesses and arithmetic operations. A new horizontal nonbinary LDPC decoder architecture is developed to implement AMC. Key components in the architecture have been designed with the consideration of variable message lengths to leverage the benefi
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Dinh, The Cuong, Huyen Pham Thi, Hung Dao Tuan, and Nghia Pham Xuan. "ONE-MINIUM-ONLY BASIC-SET TRELLIS MIN-MAX DECODER ARCHITECTURE FOR NONBINARY LDPC CODE." Journal of Computer Science and Cybernetics 37, no. 2 (2021): 91–106. http://dx.doi.org/10.15625/1813-9663/37/2/15917.

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Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error-correcting performance and error-floor property when the code length is moderate. However, the drawback of NB-LDPC decoders is high complexity and the complexity increases considerably when increasing the Galois-field order. In this paper, an One-Minimum-Only basic-set trellis min-max (OMO-BS-TMM) algorithm and the corresponding decoder architecture are proposed for NBLDPC codes to greatly reduce the complexity of the check node unit (CNU) as well as the whole decoder. In the proposed OMO-B
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Pham, Huyen Thi, Hung Tuan Dao, and Nghia Xuan Pham. "Simplified Variable Node Unit Architecture for Nonbinary LDPC Decoder." Journal of Science and Technology on Information security 9, no. 01 (2020): 12–19. http://dx.doi.org/10.54654/isj.v9i01.36.

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Abstract— Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error correcting performance and error-floor property when the code length is moderate. However, the drawback of NB-LDPC decoders is high complexity and the complexity increases considerably when increasing the Galois-field order. In this paper, a simplified basic-set trellis min-max (sBS-TMM) algorithm that is especially efficient for high-order Galois Fields, is proposed for the variable node processing to reduce the complexity of the variable node unit (VNU) as well as the whole deco
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Revathy, M., and R. Saravanan. "A Low-Complexity Euclidean Orthogonal LDPC Architecture for Low Power Applications." Scientific World Journal 2015 (2015): 1–8. http://dx.doi.org/10.1155/2015/327357.

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Low-density parity-check (LDPC) codes have been implemented in latest digital video broadcasting, broadband wireless access (WiMax), and fourth generation of wireless standards. In this paper, we have proposed a high efficient low-density parity-check code (LDPC) decoder architecture for low power applications. This study also considers the design and analysis of check node and variable node units and Euclidean orthogonal generator in LDPC decoder architecture. The Euclidean orthogonal generator is used to reduce the error rate of the proposed LDPC architecture, which can be incorporated betwe
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Sułek, W. "Pipeline processing in low-density parity-check codes hardware decoder." Bulletin of the Polish Academy of Sciences: Technical Sciences 59, no. 2 (2011): 149–55. http://dx.doi.org/10.2478/v10175-011-0019-9.

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Pipeline processing in low-density parity-check codes hardware decoderLow-Density Parity-Check (LDPC) codes are one of the best known error correcting coding methods. This article concerns the hardware iterative decoder for a subclass of LDPC codes that are implementation oriented, known also as Architecture Aware LDPC. The decoder has been implemented in a form of synthesizable VHDL description. To achieve high clock frequency of the decoder hardware implementation - and in consequence high data-throughput, a large number of pipeline registers has been used in the processing chain. However, t
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M.Sakthivel, Raja M.Karthick, KR.Ragupathy, and Kumar K.Sathis. "PERFORMANCE COMPARISON OF EG-LDPC CODES WITH MAXIMUM LIKELIHOOD ALGORITHM OVER NON-BINARY LDPC CODES." International Journal of Computational Science and Information Technology (IJCSITY) 2, May (2014): 1–11. https://doi.org/10.5281/zenodo.3517939.

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<strong>ABSTRACT </strong> Error correcting coding has become one essential part in nearly all the modern data transmission and storage systems. Low density parity check (LDPC) codes are a class of linear block code has the superior performance closer to the Shannon&rsquo;s limit. In this paper two error correcting codes from the family of LDPC codes specifically Euclidean Geometry Low Density Parity Check (EG-LDPC) codes and Nonbinary low density parity check (NB-LDPC) codes are compared in terms of power consumption, number of iterations and other parameters. For better performance of EG-LDP
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Swapnil, B. Dheple. "ANALYSIS OF REDUCED DECODING COMPLEXITY OF LOW DENSITY PARITY CHECK DECODER." International Journal of Advances in Engineering & Scientific Research 5, no. 1 (2018): 16–21. https://doi.org/10.5281/zenodo.10776884.

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<strong>ABSTRACT</strong> &nbsp; <em>The approach of this paper to reduce decoding complexity of Low density parity check decoder(LDPC). For that technique uses high precision soft messages at the variable node and put down the message length, due to this number of interconnection between check node and variable node will reduce. For the designing and simulation purposes LDPC uses min-sum algorithm. In min-sum algorithm quite increment in complexity so modified min-sum&nbsp; algorithm is use to reduce decoding complexity. A design model of this decoder uses for long distance communication appl
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Yashika Gaidhani, Tejaswini Panse, Monica Kalbande,. "A Quasi-Cyclic LDPC Based Low Complexity and Area-Efficient Communication System for IEEE 802.11n." Journal of Electrical Systems 20, no. 2s (2024): 950–58. http://dx.doi.org/10.52783/jes.1742.

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Low-density parity-check (LDPC) code, which has an excellent error-correcting performance that is close to the Shannon limit, is the most often used error correction code (ECC) for reliable and effective communication. Despite higher performance and lower decoding complexity, the main disadvantage of LDPC codes is their high encoding complexity. A significant problem is the VLSI implementation of the LDPC encoder and decoder. In this paper, structured LDPC codes—also known as quasi-cyclic low-density parity check codes—have been used since it is good bit error ratio (BER) performance and adapt
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Kuc, Mateusz, Wojciech Sułek, and Dariusz Kania. "Low Power QC-LDPC Decoder Based on Token Ring Architecture." Energies 13, no. 23 (2020): 6310. http://dx.doi.org/10.3390/en13236310.

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The article presents an implementation of a low power Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder in a Field Programmable Gate Array (FPGA) device. The proposed solution is oriented to a reduction in dynamic energy consumption. The key research concepts present an effective technology mapping of a QC-LDPC decoder to an LUT-based FPGA with many limitations. The proposed decoder architecture uses a distributed control system and a Token Ring processing scheme. This idea helps limit the clock skew problem and is oriented to clock gating, a well-established concept for power optimizati
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Hao, Ning, Yang An Zhang, Jin Nan Zhang, Ming Lun Zhang, and Xue Guang Yuan. "An Application of LDPC Code for Wireless Coherent-Light Commutation in Atmospheric Channel." Applied Mechanics and Materials 347-350 (August 2013): 1864–67. http://dx.doi.org/10.4028/www.scientific.net/amm.347-350.1864.

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Low Density Parity Check code is more and more taken seriously in high-speed transmission. In this article we represent a LDPC coder and decoder which based on IEEE802.16e and realize the coder and decoder with Virtex-5 FPGA. By using Matlab to make an off-line system simulation, we analyzed and compared the LDPC performance under the different length of code for LDPC coder then analyzed the influence of different iteration to the LDPC BER performance of decoder.
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Dissertations / Theses on the topic "Nonbinary low-density parity check (LDPC) decoder"

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XIAO, GUOPING. "VLSI architectures design for encoders of High Efficiency Video Coding (HEVC) standard." Doctoral thesis, Politecnico di Torino, 2016. http://hdl.handle.net/11583/2644058.

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The growing popularity of high resolution video and the continuously increasing demands for high quality video on mobile devices are producing stronger needs for more efficient video encoder. Concerning these desires, HEVC, a newest video coding standard, has been developed by a joint team formed by ISO/IEO MPEG and ITU/T VCEG. Its design goal is to achieve a 50% compression gain over its predecessor H.264 with an equal or even higher perceptual video quality. Motion Estimation (ME) being as one of the most critical module in video coding contributes almost 50%-70% of computational complexity
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Liu, Yue Electrical Engineering &amp Telecommunications Faculty of Engineering UNSW. "Design of structured nonbinary quasi-cyclic low-density parity-check codes." Publisher:University of New South Wales. Electrical Engineering & Telecommunications, 2009. http://handle.unsw.edu.au/1959.4/43616.

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Since the rediscovery, LDPC codes attract a large amount of research efforts. In 1998, nonbinary LDPC codes were firstly investigated and the results shown that they are better than their binary counterparts in performance. Recently, there is always a requirement from the industry to design applied nonbinary LDPC codes. In this dissertation, we firstly propose a novel class of quasi-cyclic (QC) LDPC codes. This class of QC-LDPC codes embraces both linear encoding complexity and excellent compatibility in various degree distributions and nonbinary expansions. We show by simulation results that
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Kopparthi, Sunitha. "Flexible encoder and decoder designs for low-density parity-check codes." Diss., Manhattan, Kan. : Kansas State University, 2010. http://hdl.handle.net/2097/4190.

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Zhang, Kai. "High-Performance Decoder Architectures For Low-Density Parity-Check Codes." Digital WPI, 2012. https://digitalcommons.wpi.edu/etd-dissertations/17.

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The Low-Density Parity-Check (LDPC) codes, which were invented by Gallager back in 1960s, have attracted considerable attentions recently. Compared with other error correction codes, LDPC codes are well suited for wireless, optical, and magnetic recording systems due to their near- Shannon-limit error-correcting capacity, high intrinsic parallelism and high-throughput potentials. With these remarkable characteristics, LDPC codes have been adopted in several recent communication standards such as 802.11n (Wi-Fi), 802.16e (WiMax), 802.15.3c (WPAN), DVB-S2 and CMMB. This dissertation is devoted
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Selvarathinam, Anand Manivannan. "High throughput low power decoder architectures for low density parity check codes." Texas A&M University, 2005. http://hdl.handle.net/1969.1/2529.

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A high throughput scalable decoder architecture, a tiling approach to reduce the complexity of the scalable architecture, and two low power decoding schemes have been proposed in this research. The proposed scalable design is generated from a serial architecture by scaling the combinational logic; memory partitioning and constructing a novel H matrix to make parallelization possible. The scalable architecture achieves a high throughput for higher values of the parallelization factor M. The switch logic used to route the bit nodes to the appropriate checks is an important constituent of the sca
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Shadab, Rakin Muhammad. "Statistical Analysis of a Channel Emulator for Noisy Gradient Descent Low Density Parity Check Decoder." DigitalCommons@USU, 2019. https://digitalcommons.usu.edu/etd/7582.

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The purpose of a channel emulator is to emulate a communication channel in real-life use case scenario. These emulators are often used in the domains of research in digital and wireless communication. One such area is error correction coding, where transmitted data bits over a channel are decoded and corrected to prevent data loss. A channel emulator that does not follow the properties of the channel it is intended to replicate can lead to mistakes while analyzing the performance of an error-correcting decoder. Hence, it is crucial to validate an emulator for a particular communication channel
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Yang, Lan. "An Area-Efficient Architecture for the Implementation of LDPC Decoder." Case Western Reserve University School of Graduate Studies / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=case1300337576.

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Von, Leipzig Mirko. "Code generation and simulation of an automatic, flexible QC-LDPC hardware decoder." Thesis, Stellenbosch : Stellenbosch University, 2015. http://hdl.handle.net/10019.1/96835.

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Thesis (MEng)--Stellenbosch University, 2015.<br>ENGLISH ABSTRACT: Iterative error correcting codes such as LDPC codes have become prominent in modern forward error correction systems. A particular subclass of LDPC codes known as quasicyclic LDPC codes has been incorporated in numerous high speed wireless communication and video broadcasting standards. These standards feature multiple codes with varying codeword lengths and code rates and require a high throughput. Flexible hardware that is capable of decoding multiple quasi-cyclic LDPC codes is therefore desirable. This thesis investiga
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Gunnam, Kiran Kumar. "Area and energy efficient VLSI architectures for low-density parity-check decoders using an on-the-fly computation." [College Station, Tex. : Texas A&M University, 2006. http://hdl.handle.net/1969.1/ETD-TAMU-1049.

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Matcha, Chaitanya Kumar, Mohsen Bahrami, Shounak Roy, Shayan Garani Srinivasa, and Bane Vasic. "Generalized belief propagation based TDMR detector and decoder." IEEE, 2016. http://hdl.handle.net/10150/622831.

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Two dimensional magnetic recording (TDMR) achieves high areal densities by reducing the size of a bit comparable to the size of the magnetic grains resulting in two dimensional (2D) inter symbol interference (ISI) and very high media noise. Therefore, it is critical to handle the media noise along with the 2D ISI detection. In this paper, we tune the generalized belief propagation (GBP) algorithm to handle the media noise seen in TDMR. We also provide an intuition into the nature of hard decisions provided by the GBP algorithm. The performance of the GBP algorithm is evaluated over a Voronoi b
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Book chapters on the topic "Nonbinary low-density parity check (LDPC) decoder"

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Shankar Prasad, Mani, and Shivani Verma. "Irreducible Polynomials: Non-Binary Fields." In Recent Advances in Polynomials [Working Title]. IntechOpen, 2022. http://dx.doi.org/10.5772/intechopen.101897.

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Irreducible polynomials play an important role in design of Forward Error Correction (FEC) codes for data transmission with integrity and automatic correction of data, as for example, Low-Density Parity Check codes. The usage of irreducible polynomials enables construction of non-prime-order finite fields. Most of the irreducible polynomials belong to binary Galois field. The important analytical concept is optimisation of irreducible polynomials for use in FECs in nonbinary Galois (NBG) field, leading to the development of an algorithm for LDPC that can work with nonbinary Galois fields. Acco
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Conference papers on the topic "Nonbinary low-density parity check (LDPC) decoder"

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Zarubica, Radivoje, Stephen G. Wilson, and Eric Hall. "Multi-Gbps FPGA-Based Low Density Parity Check (LDPC) Decoder Design." In IEEE GLOBECOM 2007-2007 IEEE Global Telecommunications Conference. IEEE, 2007. http://dx.doi.org/10.1109/glocom.2007.108.

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Zhu, Yuming, Yanni Chen, Dale Hocevar, and Manish Goel. "A Reduced-Complexity, Scalable Implementation of Low Density Parity Check (LDPC) Decoder." In 2006 IEEE Workshop on Signal Processing Systems Design and Implementation. IEEE, 2006. http://dx.doi.org/10.1109/sips.2006.352560.

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Shoup, Ryan. "Hardware implementation and characterization of a low density parity check (LDPC) decoder." In SPIE Optics + Photonics, edited by Roger W. Heymann, Charles C. Wang, and Timothy J. Schmit. SPIE, 2006. http://dx.doi.org/10.1117/12.682607.

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Duangthong, Chatuporn, and Watid Phakphisut. "Design of Lookup-Table (LUT) Decoder for Protograph-Based Low-Density Parity-Check (LDPC) codes." In 2022 37th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC). IEEE, 2022. http://dx.doi.org/10.1109/itc-cscc55581.2022.9895041.

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Maheshwari, Abhishek, Usana Tuntoolavest, and Kazuhiko Fukawa. "Implementation of the Nonbinary Encoder and Decoder for Systematic Low Density Parity Check Codes on Raspberry-pi boards." In 2020 11th IEEE Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON). IEEE, 2020. http://dx.doi.org/10.1109/iemcon51383.2020.9284943.

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Jemima, A., and G. Manoj. "Post and pre-layout analysis of Low Density Parity Check (LDPC) decoder using 120nm technology Cadence Encounter Tool." In 2015 2nd International Conference on Electronics and Communication Systems (ICECS). IEEE, 2015. http://dx.doi.org/10.1109/ecs.2015.7124921.

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