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Relevant bibliographies by topics / Radix-4 Booth Multiplier

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Academic literature on the topic 'Radix-4 Booth Multiplier'

Author: Grafiati

Published: 2 June 2025

Last updated: 13 July 2025

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Journal articles on the topic "Radix-4 Booth Multiplier"

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Sadaf, Sumaya, and V. Radha Krishna. "Design and Implementation of Area Efficient Low Latency Radix-8 Multiplier on FPGA." International Journal for Research in Applied Science and Engineering Technology 11, no. 10 (2023): 667–78. http://dx.doi.org/10.22214/ijraset.2023.56018.

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Abstract: Electronic systems are widely used by humans nowadays in all aspects of daily life. Today, there is no living for humans on Earth without any electronic products. High Speed, Low Power, and Low Area Electronic Systems are what the current generation needs. In digital systems, a variety of arithmetic circuits are employed. Adder, multiplier, divider, and other arithmetic circuits are some examples. To acquire Products from Multiplier and Multiplicand, there are various multipliers with various methods. One of the multipliers is Radix-4 Multiplier. The Radix-4 Multiplier produces n/2 partial products, where n is the multiplier's bit count. This multiplier has a high operating speed, power dissipation, and surface area. Area, power dissipation, and propagation delay can all be reduced by reducing the number of partial products of the n-bit multiplier. Radix-8 uses n-bit multiplier integers that are n/3 for partial products. The Area, Delay, and Power Dissipation are reduced as a result. 8- bit booth multipliers for Radix-4 and Radix-8 are designed and implemented using FPGA. For both multipliers, delay, power dissipation, and area are compared. According to the comparison, Radix8 Booth Multiplier performs better than Radix-4 Booth Multiplier in terms of delay, power dissipation, and area. Therefore, the Radix-4 Booth Multiplier can be swapped out for the Radix-8 Booth Multiplier.

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Nandha Kumar, P. "Design of Accuracy Based Fixed-Width Booth Multipliers Using Data Scaling Technology." Asian Journal of Electrical Sciences 11, no. 2 (2022): 24–30. http://dx.doi.org/10.51983/ajes-2022.11.2.3524.

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Multipliers are the basic building blocks in various digital signal processing applications such as convolution, correlation, and filters. However, conventional array multipliers, vedic multipliers were resulted in higher area, power, delay consumptions. Therefore, this work is focused on design and implementation of variable width Radix-4 booth multiplier using Data Scaling Technology (DST). The radix-4 modified booth encoding was used in the production of these incomplete items. In accumulation, the bits of the fractional products are added in a parallel manner with decreased stages using a multi-stage carry propagation adder (MSCPA). The simulation demonstrated that the suggested DST-Radix-4 booth multiplier (DST-R4BM) resulted in higher performance in comparison to traditional multiplies in terms of area, delay, and power.

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Mokhtar, Anis Shahida, Chew Sue Ping, Muhamad Faiz Md Din, Nazrul Fariq Makmor, and Muhammad Asyraf Che Mahadi. "Implementation of Booth Multiplier Algorithm using Radix-4 in FPGA." Jurnal Kejuruteraan si4, no. 1 (2021): 161–65. http://dx.doi.org/10.17576/jkukm-2021-si4(1)-20.

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This paper presentsthe performance of Radix-4 Modified Booth Algorithm. Booth algorithm is a multiplication algorithm that multiplies two signed binary numbers in two's complement notation. Multiplier is a fundamental component in general-purpose microprocessors and in digital signal processors. With advances in technology, researchers design multipliers which offer high speed, low power, and less area implementation. Booth multiplier algorithm is designed to reduce number of partial products as compared to conventional multiplier. The proposed design is simulated by using Verilog HDL in Quartus II and implemented in Cyclone II FPGA. The result shows that the average output delay is 20.78 ns. The whole design has been verified by gate level simulation.

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Bhusare, Saroja S., and V. S. Kanchana Bhaaskaran. "Low-Power High-Accuracy Fixed-Width Radix-8 Booth Multiplier Using Probabilistic Estimation Technique." Journal of Circuits, Systems and Computers 26, no. 05 (2017): 1750079. http://dx.doi.org/10.1142/s0218126617500797.

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In many Multimedia and DSP applications, the fixed-width multipliers are used to avoid infinite growth in the word size. Fixed-width multiplier produces an [Formula: see text]-bit product with two [Formula: see text]-bit inputs. This paper presents probabilistic estimation technique applied for the fixed-width radix-8 Booth multiplier for the generation of the compensation bias circuit. The probabilistic estimation circuit for the fixed-width radix-8 Booth multiplier is derived systematically from theoretical computation in preference to time-consuming exhaustive simulations. Results show that the radix-8 direct truncated multiplier reduces the maximum absolute error by 33%, the average error by 22% and the mean square error by 39% for a 12-bit multiplier compared with the radix-4 direct truncated multiplier. Results also demonstrate that, with the probabilistic estimation technique applied to the fixed-width radix-8 Booth multiplier, there is a reduction of 25% in the maximum absolute error, 13.4% reduction in the average error, and 25.13% reduction in the mean square error have been realized compared with the existing fixed-width radix-4 Booth multiplier with probabilistic estimation technique. Standard EDA design tools are used for simulations.

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Suvarna, S., K. Rajesh, and T. Radhu. "A Modified Architecture for Radix-4 Booth Multiplier with Adaptive Hold Logic." International Journal of Students' Research in Technology & Management 4, no. 1 (2016): 01–05. http://dx.doi.org/10.18510/ijsrtm.2016.411.

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High speed digital multipliers are most efficiently used in many applications such as Fourier transform, discrete cosine transforms, and digital filtering. The throughput of the multipliers is based on speed of the multiplier, and then the entire performance of the circuit depends on it. The pMOS transistor in negative bias cause negative bias temperature instability (NBTI), which increases the threshold voltage of the transistor and reduces the multiplier speed. Similarly, the nMOS transistor in positive bias cause positive bias temperature instability (PBTI).These effects reduce the transistor speed and the system may fail due to timing violations. So here a new multiplier was designed with novel adaptive hold logic (AHL) using Radix-4 Modified Booth Multiplier. By using Radix-4 Modified Booth Encoding (MBE), we can reduce the number of partial products by half. Modified booth multiplier helps to provide higher throughput with low power consumption. This can adjust the AHL circuit to reduce the performance degradation. The expected result will be reduce threshold voltage, increase throughput and speed and also reduce power. This modified multiplier design is coded by Verilog and simulated using Xilinx ISE 12.1 and implemented in Spartan 3E FPGA kit.

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Sivajyothi, Gogula, and Suman Mishra. "Efficient Compressor and Encoder Strategies for Cost-Effective Radix-4 Approximate Booth Multipliers." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 008 (2024): 1–16. http://dx.doi.org/10.55041/ijsrem37197.

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Multiplication operations are essential in digital systems, and the design of efficient and cost- effective multipliers holds significant importance across various applications. This paper presents a novel methodology aimed at improving the affordability of approximate radix-4 Booth multipliers by proposing simplified designs for compressors and encoders. The primary objective is to achieve a balance between computational accuracy and hardware cost, rendering the multiplier suitable for deployment in low-cost embedded systems and applications where a certain degree of approximation is permissible. The proposed approach involves utilization of simplified compressors, meticulously optimized for resource efficiency and seamless integration into the approximate radix-4 Booth multiplier architecture. Furthermore, an innovative encoder design is introduced to further streamline the hardware complexity associated with encoding partial products. These encoder designs are strategically crafted to maintain an acceptable level of accuracy while minimizing resource utilization. Keywords:Approximate Booth multipliers, Booth encoders, Compressors, Xilinx ISE 14.7 tool

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Fu, Chengjie, Xiaolei Zhu, Kejie Huang, and Zheng Gu. "An 8-bit Radix-4 Non-Volatile Parallel Multiplier." Electronics 10, no. 19 (2021): 2358. http://dx.doi.org/10.3390/electronics10192358.

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The data movement between the processing and storage units has been one of the most critical issues in modern computer systems. The emerging Resistive Random Access Memory (RRAM) technology has drawn tremendous attention due to its non-volatile ability and the potential in computation application. These properties make them a perfect choice for application in modern computing systems. In this paper, an 8-bit radix-4 non-volatile parallel multiplier is proposed, with improved computational capabilities. The corresponding booth encoding scheme, read-out circuit, simplified Wallace tree, and Manchester carry chain are presented, which help to short the delay of the proposed multiplier. While the presence of RRAM save computational time and overall power as multiplicand is stored beforehand. The area of the proposed non-volatile multiplier is reduced with improved computing speed. The proposed multiplier has an area of 785.2 μm2 with Generic Processing Design Kit 45 nm process. The simulation results show that the proposed multiplier structure has a low computing power at 161.19 μW and a short delay of 0.83 ns with 1.2 V supply voltage. Comparative analyses are performed to demonstrate the effectiveness of the proposed multiplier design. Compared with conventional booth multipliers, the proposed multiplier structure reduces the energy and delay by more than 70% and 19%, respectively.

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Wani, Towseef Ul Haq, and Ravinder Pal Singh. "Implementation of ALU Using Modified Radix-4 Modified Booth Multiplier." International Journal for Research in Applied Science and Engineering Technology 11, no. 2 (2023): 188–200. http://dx.doi.org/10.22214/ijraset.2023.48914.

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Abstract: In this project, we propose a novel multiplier hardware design based on a radix - 4 modified booth encoder. The standard modified Booth encoding (MBE) provides an uneven partial product array due to the extra partial product bit at the least significant bit position of each partial product row. In this brief, a simple technique for constructing a regular partial product array with fewer partial product rows and low overhead is provided, reducing the complexity of partial product reduction as well as the space, time, and power of MBE multipliers. A SPST-based adder is examined and designed for the reduction of power in partial product reduction

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Kuo, Chao-Tsung, and Yao-Cheng Wu. "FPGA Implementation of a Novel Multifunction Modulo (2n ± 1) Multiplier Using Radix-4 Booth Encoding Scheme." Applied Sciences 13, no. 18 (2023): 10407. http://dx.doi.org/10.3390/app131810407.

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The residue number system is widely used in applications such as communication systems, cryptography, digital filters, digital signal processors, fault-tolerant detection, and so on. This paper proposes a multifunction modulo (2n ± 1) multiplier based on the radix-4 Booth encoding scheme that can operate both modulo (2n − 1) and modulo (2n + 1) multipliers using the same hardware structure with only one control signal. A novel modulo (2n ± 1) multiplier based on radix-4 Booth encoding is proposed that can achieve superior performance, with low power, fast operation, high area efficiency, and low area-delay product (ADP) and power-delay product (PDP) compared with similar modified Booth-encoding methods. In addition, by integrating the separate modulo functions of the modulo (2n − 1) multiplier and modulo (2n + 1) multiplier into a single multifunction modulo (2n ± 1) multiplier, the proposed method can save up to 52.59% (n = 16) of hardware area, up to 5.45% (n = 32) of delay time, up to 49.05% (n = 16) of dynamic power, up to 50.92% (n = 32) of ADP, and up to 50.02% (n = 32) of PDP compared with the original separate circuits merged together. Furthermore, the operation ranges of the multiplicand and multiplier of the proposed modulo (2n + 1) multiplier and modulo (2n − 1) multiplier are {0, 2n + 1} and {0, 2n}, respectively, which are wider than for other reported hardware structures. The hardware area, power consumption, and delay time are simulated and verified using Verilog HDL and Xilinx FPGA (Field Programmable Gate Array) Vivado tools. The Xilinx Artix-7 XC7A35T-CSG324-1 FPGA chipset is adopted in the proposed work.

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Liu, Chenghao, Jingyu Sun, and Ruihong Tang. "A design of multiplier based on Radix_4 Booth algorithm and 4-2 Wallace compression tree." Applied and Computational Engineering 37, no. 1 (2024): 166–76. http://dx.doi.org/10.54254/2755-2721/37/20230498.

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In a multitude of computational and signal processing scenarios, the multiplier functions as a fundamental arithmetic component. Given the complex hardware arrangement of multipliers and their usual positioning within the crucial pathway of digital systems, their significance is substantial. Therefore, approximations of multipliers can greatly optimize system performance. This essay examines the fundamental ideas behind the Wallace tree, the Carry ahead adder, and the Radix-4 Booth algorithm. Additionally, instead of the more common 3-2 compressors, a Wallace tree structure with 4-2 compressors is used to compact these products for the manufacture of partial products. This reduction in compression stages to three significantly curtails delays along critical paths, thereby substantially improving overall performance. The compressed outcomes from the Wallace tree undergo processing via a 64 bit carry ahead adder, effectively addressing delays stemming from mutual carry propagation among sequentially connected regular full adders. Leveraging these principles and processes, a 32-bit signed multiplier is designed. Building upon this foundation, an approximate Booth multiplier is developed, enhancing both computational speed and reducing critical path delays. The functionality of the multiplier was validated using Vivado simulation, demonstrating its correctness. Additionally, the RTL-level circuitry of different segments of the multiplier was showcased.

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Dissertations / Theses on the topic "Radix-4 Booth Multiplier"

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Patel, Rishit Navinbhai. "Implementation of High Speed and Low Power Radix-4 8*8 Booth Multiplier in CMOS 32nm Technology." Wright State University / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=wright1495371138748713.

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Liao, Shao-Chi, and 廖少祺. "Pre-encoded Radix-4 Booth Multiplier." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/wghqr4.

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碩士<br>國立中興大學<br>資訊科學與工程學系<br>103<br>Multiplication is widely used in many applications, thus, the power consumption of the multiplier is important issue. In this paper, we propose a new modified Booth encoding (MBE) scheme with a pre-encoder to improve the power consumption of the multiplier. This pre-encoder will disable the booth decoders which are unnecessary to be active in the 0X case, and set the outputs of decoders to 0. Compared with the previous approach, our design reduces 25% dynamic power consumption and 10% the transistor count of booth encoder and decoder for an 8-bit multiplication. For a 16-bit multiplication, our design reduces 34% dynamic power consumption and 12% transistor count. The performace and static power consumption are also better than previous studies.

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Liu, Hsin-Chun, and 劉信均. "A Low Power Radix-4 Booth Multiplier Design." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/26398031568419386105.

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碩士<br>國立中興大學<br>資訊科學與工程學系所<br>99<br>In this paper, we present a low power Booth multiplier with a conditionally gated decoder. Using the features of Booth decoding, our design can reduce the unnecessary node switching in Booth decoder. Based on UMC 90-nm CMOS technology, simulation results show that our decoder can achieve 11.05% improvement in dynamic power consumption and 10.05% in static power consumption. In addition, the power improvement of the 32 × 32 Booth multiplier can reach 6.07% in dynamic and 6.48% in static after implementing with our decoder.

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Wang, Yen-Yuan, and 王彥淵. "A Low-Power Radix-4 Booth Multiplier Design Using Precise Operand Exchange." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/63516007279939452155.

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碩士<br>國立中興大學<br>資訊科學與工程學系<br>102<br>In this paper, we present a low power 16 × 16 Radix-4 Booth multiplier design using precise operand exchange. In the Booth algorithm the partial product is zero when the multiplier input is sequential 0/1. Our design can choose and set the preferable multiplier input between two operands to reduce the switching activity in the partial product generation. Moreover, we increase the chance of operand exchange by separating a 16 × 16 multiplier into four 8 × 8 multipliers with one-level recursion design. Based on TSMC 90-nm CMOS technology, simulation results show that our design can achieve 28.81% improvement in dynamic power.

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Book chapters on the topic "Radix-4 Booth Multiplier"

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Kumari, Priyanka, and Gaurav Verma. "Area and Energy Efficient Booth Radix-4 Signed Multiplier Using Verilog." In Mobile Radio Communications and 5G Networks. Springer Nature Singapore, 2024. http://dx.doi.org/10.1007/978-981-97-0700-3_20.

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Kanoujia, Sandhya, Rishav Kumar, and P. Karuppanan. "Low Power Radix-4 Booth Multiplier Design Using Pass Transistor Logic." In VLSI, Communication and Signal Processing. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-0973-5_26.

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Dalal, Anshul, Manoj Choudhary, and S. Balamurugan. "Design Framework of 4-Bit Radix-4 Booth Multiplier Using Perpendicular Nanomagnetic Logic in MagCAD." In Communications in Computer and Information Science. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-5048-2_31.

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Xia, Chao, Hang Yang, and Bo Gao. "Implementation of a 64 Bit Vector Multiplier for RISC-V." In Advances in Transdisciplinary Engineering. IOS Press, 2024. https://doi.org/10.3233/atde241307.

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The article presents a novel 64-bit vector integer/fixed-point multiplier design. This multiplier is in accordance with the RISC-V Vector Extension, which is designated as “RVV 1.0.” The proposed approach for 64-bit signed or unsigned multiplication employs an advanced Radix-4 Booth encoder variant in conjunction with a Wallace tree configuration. This refined Radix-4 Booth encoding method markedly reduces the partial product count and simplifies the multiplication process. Moreover, incorporating the Wallace tree facilitates rapid compression and summation of partial products, significantly enhancing multiplication efficiency. The vector multiplier exhibits low latency and full pipelining, achieving the compression of 35 partial products within just two cycles. The multiplier introduced in this paper is particularly well-suited for demanding computational tasks, including multimedia and digital signal processing applications.

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Sivasaravanababu, S., T. R. Dineshkumar, and G. Saravana Kumar. "Assertion Driven Modified Booth Encoding and Post Computation Model for Speed MAC Applications." In Recent Trends in Intensive Computing. IOS Press, 2021. http://dx.doi.org/10.3233/apc210289.

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The Multiply-Accumulate Unit (MAC) is the core computational block in many DSP and wireless application but comes with more complicated architectures. Moreover the MAC block also decides the energy consumption and the performance of the overall design; due to its lies in the maximal path delay critical propagation. Developing high performance and energy optimized MAC core is essential to optimized DSP core. In this work, a high speed and low power signed booth radix enabled MAC Unit is proposed with highly configurable assertion driven modified booth algorithm (AD-MBE). The proposed booth core is based on core optimized booth radix-4 with hierarchical partial product accumulation design and associated path delay optimization and computational complexity reduction. Here all booth generated partial products are added as post summation adder network which consists of carry select adder (CSA) & carry look ahead (CLA) sequentially which narrow down the energy and computational complexity. Here increasing the operating frequency is achieved by accumulating encoding bits of each of the input operand into assertion unit before generating end results instead of going through the entire partial product accumulation. The FPGA implementation of the proposed signed asserted booth radix-4 based MAC shows significant complexity reduction with improved system performance as compared to the conventional booth unit and conventional array multiplier.

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Chopde, Abhay, Sharvari Bodas, Varada Deshmukh, and Shamish Bramhekar. "Fast Inverse Square Root using FPGA." In Advancements in Communication and Systems. Soft Computing Research Society, 2024. http://dx.doi.org/10.56155/978-81-955020-7-3-21.

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The Fast Inverse Square Root (FISR) algorithm, originally introduced in the Quake III source code, accomplishes the vector normalization task required in graphics application through basic multiplication and bit-shifting operations. The core of this algorithm relies on the use of approximation techniques to enhance an initial estimation, which is primarily based on a designated “magic” constant. The implemented Verilog code utilizes the Newton-Raphson iterations, modified booth’s multiplier, and the inverse square root, featuring a core “Inverse Square Root” module with 32-bit input and output. This paper makes use of two magic constants “0x5f3e34bc” and “0x5f3759df” aiming to improve the accuracy. It selects a magic constant based on the exponent bit. The approximation occurs through two Newton-Raphson iterations. A Booth Multiplier is used, that is using a Radix-4 encoding scheme to reduce partial product generation, making it faster.

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Wang, Ju, and Jonathan C. L. Liu. "Advances of Radio Interface in WCDMA Systems." In Encyclopedia of Multimedia Technology and Networking, Second Edition. IGI Global, 2009. http://dx.doi.org/10.4018/978-1-60566-014-1.ch002.

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Recent years have witnessed the rapid progress in handheld devices. This has resulted in a growing number of mobile phones or PDAs that have a built-in camera to record still pictures or live videos. Encouraged by the success of second generation cellular wireless networks, researchers are now pushing the 3G standard to support a seamless integration of multimedia data services. One of the main products is WCDMA (Holma & Toskala, 2001), short for wideband code division multiple access. WCDMA networks have 80 million subscribers in 46 countries at the time of this writing. WCDMA can be viewed as a successor of the 2G CDMA system. In fact, many WCDMA technologies can be traced back to the 2G CDMA system. However, WCDMA air interface is specifically designed with envision to support real time multimedia services. To name some highlights, WCDMA: • Supports both packet-switched and circuitswitched data services. Mobile best-effort data services, such as Web surfing and file downloads, are available through packet service. • Has more bandwidth allocated for downlink and uplink than the 2G systems. It uses a 5 MHz wide radio signal and a chip rate of 3.84 mcps, which is about three times higher than CDMA2000. • Support a downlink data rate of 384 kbps for wide area coverage and up to 2 Mbps for hot-spot areas, which is sufficient for most existing packet-data applications. WCDMA Release 5 (Erricson, 2004) adopts HSDPA (High-speed downlink packet access), which increases peak data rates to 14 Mbps in the downlink. To achieve high data rate, WCDMA uses several new radio interface technologies, including (1) shared channel transmission, (2) higher-order modulation, (3) fast link adaptation, (4) fast scheduling, and (5) hybrid automatic-repeat-request (HARQ). These technologies have been successfully used in the downlink HSDPA, and will be used in upcoming improved uplink radio interface in the future. The rest of this article will explain the key components of the radio interface in WCDMA.

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Pal, Soumayadeep, Parthib Banerjee, Avrajeet Ghosh, et al. "ADVANCED ROBOTICS IN DEFENCE AND MEDICAL APPLICATIONS." In Futuristic Trends in Robotics & Automation Volume 3, Book 1. Iterative International Publisher, Selfypage Developers Pvt Ltd, 2024. http://dx.doi.org/10.58532/v3bbra1p3ch1.

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Development of Swarm Bot for Defence and Medical Application Design of Swarm bot is an initiative towards the synchronized performance of multiple bots as a total system consisting huge numbers of plain real-time bots. It is observed that an expected groupwise behavior is expressed from the interactions between the bots and the master device. The head posture movement is used to send the signal from the master device to communicate the slave devices. This methodology has come out in the field of artificial swarm intelligence, as well as the bio-inspired researches of insects and other fields in nature with the occurrence of swarm behavior. This process depends on the master-slave concept to operate the whole system. The wireless communication utilizes the SPI (Serial Peripheral Interface) protocol with radio waves in the range of 2.4-2.5 GHz. The ISM (Industrial Scientific Medical) band is used for the communication purpose. Development of Verticle Climbing Camouflage Surveillance Bot Scientists are trying to make vehicles that can move through both vertical and horizontal planes simultaneously for a long time. Moving against gravity makes it very difficult because of wheel spin in a steeply inclined surface plane. In this paper, we are dealing with the design and development of a WI-FI controlled bot that can move on both horizontal and vertical surfaces. The air suction technique is used to hold the bot on a vertically inclined surface. This paper presents the design and development of a wall climbing bot using an ESP32 CAM microcontroller. The wall climbing feature is achieved by using a 2200kv BLDC motor and 600 mm propeller. When the propeller is rotated using the BLDC motor, the propeller sucks the air underneath the robot, creating a vacuum. As a result, outside air pressure works on the robot and makes it stick to the horizontal surface. The robot`s movement is done by using 4 100 RPM dc motors. The motors are connected to the ESP32 microcontroller via motor driver L298N and can be manually controlled using any ESP32 Android/IOS mobile application. We have used the TCS3200 colour sensor and RGB LED lights to change the colour of the body as per the surroundings. The robot can be used for any surveillance purposes from general surveillance purposes to surveillance of hostile areas.

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Conference papers on the topic "Radix-4 Booth Multiplier"

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Zhu, Xinyu, Hongge Li, Yinjie Song, Yuhao Chen, and Xiaoyu Guo. "High Energy Efficiency Radix-4 Booth Multiplier with Zero Encoding Skipping Mechanism." In 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 2024. http://dx.doi.org/10.1109/isvlsi61997.2024.00050.

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S, Hariprasad, Maria Dominic Savio M, Akriti D, Rithvidas R, and Naveen M. "Image Processing Acceleration Using Radix-8 Booth Multiplier with Custom Designed 4:2 Compressors." In 2024 5th International Conference on Data Intelligence and Cognitive Informatics (ICDICI). IEEE, 2024. https://doi.org/10.1109/icdici62993.2024.10810991.

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Adinarayana, T. V. S., G. Rajesh, Yashasvi Linga Reddy, Vishwass R. Yadav, and Srinivas Abhinay Gandla. "Design of a 16-Bit Power-Efficient Posit Multiplier with Selective Activation and Modified Radix-4 Booth Multiplier." In 2025 6th International Conference on Mobile Computing and Sustainable Informatics (ICMCSI). IEEE, 2025. https://doi.org/10.1109/icmcsi64620.2025.10883248.

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Rooban, S., M. Nagesh, M. V. S. L. Prasanna, K. Rayudu, and G. Dheeraj Sai. "Implementation of 128-bit Radix-4 Booth Multiplier." In 2021 International Conference on Computer Communication and Informatics (ICCCI). IEEE, 2021. http://dx.doi.org/10.1109/iccci50826.2021.9457004.

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Nagamani, A. N., R. Nikhil, Manish Nagaraj, and Vinod Kumar Agrawal. "Reversible Radix-4 booth multiplier for DSP applications." In 2016 International Conference on Signal Processing and Communications (SPCOM). IEEE, 2016. http://dx.doi.org/10.1109/spcom.2016.7746687.

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Varghese, Nivya Rose, and Swaminadhan Rajula. "High Speed Low Power Radix 4 Approximate Booth Multiplier." In 2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech). IEEE, 2019. http://dx.doi.org/10.1109/iementech48150.2019.8981022.

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Kumre, Laxmi, Ajay Somkuwar, and Ganga Agnihotri. "Implementation of radix 4 booth multiplier using MGDI technique." In 2013 Annual International Conference on Emerging Research Areas (AICERA) - 2013 International Conference on Microelectronics, Communications and Renewable Energy (ICMiCR). IEEE, 2013. http://dx.doi.org/10.1109/aicera-icmicr.2013.6575945.

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Gaurav, Tanya, Krutarthkumar Patel, and Rutu Parekh. "RTL to GDSII Implementation of RADIX-4 Booth Multiplier." In 2022 IEEE International Conference on Nanoelectronics, Nanophotonics, Nanomaterials, Nanobioscience & Nanotechnology (5NANO). IEEE, 2022. http://dx.doi.org/10.1109/5nano53044.2022.9828885.

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Agarwal, Riya, Sanjana Jayakrishna, and N. Sivaselvan. "Design of an Accurate, Cost-effective Radix-4 Booth Multiplier." In 2021 IEEE International IOT, Electronics and Mechatronics Conference (IEMTRONICS). IEEE, 2021. http://dx.doi.org/10.1109/iemtronics52119.2021.9422509.

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Cho, Ki-seon, Jong-on Park, Jin-seok Hong, and Goang-seog Choi. "54x54-bit radix-4 multiplier based on modified booth algorithm." In the 13th ACM Great Lakes Symposium. ACM Press, 2003. http://dx.doi.org/10.1145/764808.764869.

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