Relevant bibliographies by topics / REVERSE CARRY PROPAGATE ADDER

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'REVERSE CARRY PROPAGATE ADDER'

Author: Grafiati
Published: 11 September 2023
Last updated: 31 July 2025

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Journal articles on the topic "REVERSE CARRY PROPAGATE ADDER"

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Pashaeifar, Masoud, Mehdi Kamal, Ali Afzali-Kusha, and Massoud Pedram. "Approximate Reverse Carry Propagate Adder for Energy-Efficient DSP Applications." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26, no. 11 (2018): 2530–41. http://dx.doi.org/10.1109/tvlsi.2018.2859939.

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Arulkarthick, V. J., and Abinaya Rathinaswamy. "Delay and area efficient approximate multiplier using reverse carry propagate full adder." Microprocessors and Microsystems 74 (April 2020): 103009. http://dx.doi.org/10.1016/j.micpro.2020.103009.

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Laxmi, Kumre1 Ajay Somkuwar2 and Ganga Agnihotri3. "POWER EFFICIENT CARRY PROPAGATE ADDER." International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013 4, no. 3 (2019): 01–10. https://doi.org/10.5281/zenodo.3364247.

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Here we describe the design details and performance of proposed Carry Propagate Adder based on GDI technique. GDI technique is power efficient technique for designing digital circuit that consumes less power as compare to most commonly used CMOS technique. GDI also has an advantage of minimum propagation delay, minimum area required and less complexity for designing any digital circuit. We designed Carry Propagate Adder using GDI technique and compared its performance with CMOS technique in terms of area, delay and power dissipation. Circuit designed using CADENCE EDA tool and simulated using
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Kumre, Laxmi, Ajay Somkuwar, and Ganga Agnihotri. "Power Efficient Carry Propagate Adder." International Journal of VLSI Design & Communication Systems 4, no. 3 (2013): 125–34. http://dx.doi.org/10.5121/vlsic.2013.4312.

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Lin, Yu Shen, and Damu Radhakrishnan. "Delay Efficient 32-Bit Carry-Skip Adder." VLSI Design 2008 (April 2, 2008): 1–8. http://dx.doi.org/10.1155/2008/218565.

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The design of a 32-bit carry-skip adder to achieve minimum delay is presented in this paper. A fast carry look-ahead logic using group generate and group propagate functions is used to speed up the performance of multiple stages of ripple carry adders. The group generate and group propagate functions are generated in parallel with the carry generation for each block. The optimum block sizes are decided by considering the critical path into account. The new architecture delivers the sum and carry outputs in lesser unit delays than existing carry-skip adders. The adder is implemented in 0.25 m C
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Sanduri, Akshitha, P. Navitha Mrs., and D. Mamatha Mrs. "Fast Modular Multiplication using Parallel Prefix Adder." International Journal of Trend in Scientific Research and Development 2, no. 5 (2018): 1770–74. https://doi.org/10.31142/ijtsrd18170.

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Public key cryptography applications involve use of large integer arithmetic operations which are compute intensive in term of power, delay and area. Modular multiplication, which is frequently, used most resource hungry block. Generally, last stage of modular multiplication is implemented by using carry propagate adder whose long carry chain takes more time. In this paper, modulo multiplication architectures using Carry Save and Kogge Stone parallel prefix adder are presented to reduce this problem. Proposed implementations are faster as compared to conventional carry save adder and carry pro
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Escribá, J., and J. A. Carrasco. "Self-timed Manchester chain carry propagate adder." Electronics Letters 32, no. 8 (1996): 708. http://dx.doi.org/10.1049/el:19960512.

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8

Keerthan, Chilagani, and Bathini Trinay. "High-Speed Area-Efficient VLSI Architecture of Three Operand Binary Adder." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 09, no. 04 (2025): 1–9. https://doi.org/10.55041/ijsrem44578.

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This paper proposes a novel high-speed three-operand binary adder architecture, namely the Han-Carlson adder, which mitigates the inherent limitations of traditional Carry Save Adders (CSAs). The CSA's drawbacks, including slow carry propagation and increased power consumption, are alleviated by the Han-Carlson adder's innovative prefix computation and carry lookahead architecture.The Han-Carlson adder's design exploits the benefits of prefix computation to generate the carry signals in parallel, thereby reducing the critical path delay. Furthermore, the carry lookahead mechanism enables the a
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Sandi, Anuradha. "VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH." International Journal of Engineering Technologies and Management Research 6, no. 6 (2020): 40–50. http://dx.doi.org/10.29121/ijetmr.v6.i6.2019.392.

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In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The performance depends on power consumption and delay. Adders are not only used for arithmetic operations, but also for calculating addresses and indices. In digital design we have half adder and full adder, by using these adders we can implement ripple carry adder (RCA). RCA is used to perform any number of additions. In this RCA is serial adder and it has propagation delay problem. With increas
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Dr., Anuradha M. Sandi. "VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH." International Journal of Engineering Technologies and Management Research 6, no. 6 (2019): 40–50. https://doi.org/10.5281/zenodo.3245207.

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In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The performance depends on power consumption and delay. Adders are not only used for arithmetic operations, but also for calculating addresses and indices. In digital design we have half adder and full adder, by using these adders we can implement ripple carry adder (RCA). RCA is used to perform any number of additions. In this RCA is serial adder and it has propagation delay problem. With increas
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Dissertations / Theses on the topic "REVERSE CARRY PROPAGATE ADDER"

1

CHOUDHARY, DIVYA. "NEW REVERSE CARRY PROPAGATE ADDER USING MODIFIED GDI TECHNIQUE." Thesis, 2019. http://dspace.dtu.ac.in:8080/jspui/handle/repository/16711.

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Addition is the most important function in arithmetic and logical operations. Approximate Computing can be used to reduce the number of transistors, delay and power constraints in VLSI design, which makes the use of approximate adders possible in error-tolerant applications. Existing Approximate Reverse Carry Propagate Adder designs [1] have proved to be advantageous in improving these constraints. A new design of Reverse Carry Propagate Adder has been proposed using Modified-Gate Diffusion Input (GDI) technique [7]. A 4-bit Multiplier has also been designed using this RCPFA and results verifi
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Book chapters on the topic "REVERSE CARRY PROPAGATE ADDER"

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Naresh, B., K. Aruna Manjusha, and U. Somanaidu. "Design of Low-Power Reverse Carry Propagate Adder Using FinFET." In Algorithms for Intelligent Systems. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-1669-4_42.

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Conference papers on the topic "REVERSE CARRY PROPAGATE ADDER"

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Bhavani, N. S. V. S. Ganga, and M. Vinodhini. "High Performance Accurate Multiplier using Hybrid Reverse Carry Propagate Adder." In 2022 6th International Conference on Electronics, Communication and Aerospace Technology (ICECA). IEEE, 2022. http://dx.doi.org/10.1109/iceca55336.2022.10009577.

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Baskar, P., V. Prabhu, S. Ashok, D. Ruban Thomas, Vishnu Vardhan Rao, and A. Mohamed Abbas. "High and low power modified reverse carry propagate adder for DSP application." In INTERNATIONAL CONFERENCE ON MODELLING STRATEGIES IN MATHEMATICS: ICMSM 2024. AIP Publishing, 2025. https://doi.org/10.1063/5.0276644.

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V. S, Muralikrishna, and oselin Kavitha M. J. "A High-Speed, Area-Efficient Transfer Method Using a Reverse Carry Propagate Adder." In The International Conference on scientific innovations in Science, Technology, and Management. International Journal of Advanced Trends in Engineering and Management, 2023. http://dx.doi.org/10.59544/jjjn7780/ngcesi23p115.

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The most important component of any electronic device has historically been the arithmetic and logic unit. An efficient algorithmic function, such as addition and multiplication, which is required for an arithmetic as well as logic unit to be significant in the current improvement. For performing modular arithmetic in several cryptography and pseudorandom bit generator (PRBG) algorithms, the three-operand binary adder is the fundamental functional unit. In this paper, this study purposes a reverse carry propagate adder A carry input signal is more important than the carry output signal because
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V. S, Muralikrishna, and Joselin Kavitha M. "A High-Speed, Area-Efficient Transfer Method Using a Reverse Carry Propagate Adder." In The International Conference on scientific innovations in Science, Technology, and Management. International Journal of Advanced Trends in Engineering and Management, 2023. http://dx.doi.org/10.59544/ueyi4889/ngcesi23p117.

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Abstract:
The most important component of any electronic device has historically been the arithmetic and logic unit. An efficient algorithmic function, such as addition and multiplication, which is required for an arithmetic as well as logic unit to be significant in the current improvement. For performing modular arithmetic in several cryptography and pseudorandom bit generator (PRBG) algorithms, the three-operand binary adder is the fundamental functional unit. In this paper, this study purposes a reverse carry propagate adder A carry input signal is more important than the carry output signal because
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Garg, Bharat, and Yashoda Bisht. "A Novel High Performance Reverse Carry Propagate Adder for Energy Efficient Multimedia Applications." In 2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS). IEEE, 2019. http://dx.doi.org/10.1109/ises47678.2019.00073.

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Naidu, S. Harshavardhan, T. Kathiravan, K. S. Rani, V. Charan Sai, Y. Venkata Karthik Reddy, and Moddu Vamsi. "Design of an Efficient Reverse Carry Propagate Adder for Area Consumption on VLSI." In 2024 International Conference on Recent Advances in Electrical, Electronics, Ubiquitous Communication, and Computational Intelligence (RAEEUCCI). IEEE, 2024. http://dx.doi.org/10.1109/raeeucci61380.2024.10547835.

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Sedhumadhavan, A., S. Sabariesh, V. Shanmathi, K. Ramya, R. Venukumar, and J. Ajayan. "Study of Performance Comparison of Static and Dynamic Approximate Reverse Carry Propagate Adder Using 22 nm CMOS Technology." In 2020 6th International Conference on Advanced Computing and Communication Systems (ICACCS). IEEE, 2020. http://dx.doi.org/10.1109/icaccs48705.2020.9074311.

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Singh, Shalini, Pavan Kumar Pothula, and Madhav Rao. "Design and Evaluation of On-chip DCT accelerators based on Novel Approximate Reverse Carry Propagate Adders." In 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 2022. http://dx.doi.org/10.1109/isvlsi54635.2022.00015.

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Singh, Varun Pratap, and Manish Rai. "Reversible adder-subtractor circuit with carry and borrow propagate facility." In 2017 3rd International Conference on Advances in Computing, Communication & Automation (ICACCA) (Fall). IEEE, 2017. http://dx.doi.org/10.1109/icaccaf.2017.8344704.

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Akbar, Muhammad Ali, Bo Wang, and Amine Bermak. "Evaluating the Optimal Self-Checking Carry Propagate Adder for Cryptographic Processor." In 2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC). IEEE, 2022. http://dx.doi.org/10.1109/mcsoc57363.2022.00011.

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