Relevant bibliographies by topics / Ripple carry adder (RCA)

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Ripple carry adder (RCA)'

Author: Grafiati
Published: 2 June 2025
Last updated: 31 July 2025

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Journal articles on the topic "Ripple carry adder (RCA)"

1

Alkurwy, Salah Hasan, and Isam Salah Hameed. "A novel pipelined carry adder design based on half adder." Indonesian Journal of Electrical Engineering and Computer Science 25, no. 2 (2022): 763–70. https://doi.org/10.11591/ijeecs.v25.i2.pp763-770.

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A new design of binary parallel adder circuit is presented in this paper. The pipeline technique is applied to implement a group of a half adder (HA) blocks to architect the proposed adder. The pipelined carry adder (PCA) method is suitable for carrying out the desired adder by using the HA circuits of XOR and AND gates. The applied technique reduces the critical path delay by 27% compared with the ripple carry adder (RCA) and relatively lowers logic gates by 55% compared with the carry look-ahead adder (CLA). The coded design of the proposed circuit is implemented and simulated on the Cyclone
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Dr., Anuradha M. Sandi. "VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH." International Journal of Engineering Technologies and Management Research 6, no. 6 (2019): 40–50. https://doi.org/10.5281/zenodo.3245207.

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In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The performance depends on power consumption and delay. Adders are not only used for arithmetic operations, but also for calculating addresses and indices. In digital design we have half adder and full adder, by using these adders we can implement ripple carry adder (RCA). RCA is used to perform any number of additions. In this RCA is serial adder and it has propagation delay problem. With increas
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3

Joseph, Neenu, Ashker Assis, Arjun Bibin, Aromal A., and Thanzeel A R. "FPGA Based 32-Bit Hybrid Ripple Ling Carry Adder." Journal of Electronics and Informatics 7, no. 2 (2025): 177–90. https://doi.org/10.36548/jei.2025.2.008.

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The 32-bit Hybrid Ripple Ling carry adder uses a Ling-based parallel prefix adder for the upper 16 bits and a ripple-carry adder (RCA) for the lower 16 bits to optimize performance, power, and area efficiency for VLSI designs. While the Ling adder speeds up carry propagation for larger bits, the RCA minimizes area and power for smaller bit-widths. This hybrid structure offers high-speed, low-power operation while saving 12% power, 30%–40% area, and a worst-case delay of 0.182 ns in a 28 nm process. The adder employs a Ling-based parallel prefix topology for the higher-order bits. A re-expressi
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Kamaraju, M., P. Ashok Babu, P. Himasri, and S. Akshitha. "Power and Area Efficient Four-Bit Vedic Multiplier Implemented Using a Modified Five-Bit Adder with CMOS and TG Configuration." Journal of Controller and Converters 9, no. 1 (2024): 27–36. http://dx.doi.org/10.46610/jcc.2024.v090i01.005.

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Vedic multipliers are incredibly fast, efficient, and flexible, perfect for efficiently handling tasks like signal processing. Vedic multipliers are the go-to choice for maximizing performance and efficiency in digital designs, as the existing method adders like Carry Look-Ahead Adder (CLA), a Carry Skip Adder (CSA), or a Ripple Carry Adder (RCA) have more delay, area and power. The project proposal presents a novel 4-bit Vedic multiplier essential to system functionality. Optimizing the balancing area and delay is necessary for improving the system as a whole. This project aims to strike this
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Maroju, SaiKumar, and P. Samundiswary Dr. "Design and Performance Analysis of Various Adders using Verilog." International Journal of Computer Science and Mobile Computing 2, no. 9 (2013): 128–38. https://doi.org/10.5281/zenodo.32564.

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Adders are one of the most widely digital components in the digital integrated circuit design and are the necessary part of Digital Signal Processing (DSP) applications. With the advances in technology, researchers have tried and are trying to design adders which offer either high speed, low power consumption, less area or the combination of them. In this paper, the design of various adders such as Ripple Carry Adder (RCA), Carry Skip Adder (CSkA), Carry Increment Adder (CIA), Carry Look Ahead Adder (CLaA), Carry Save Adder (CSA), Carry Select Adder (CSlA), Carry Bypass Add
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Sandi, Anuradha. "VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH." International Journal of Engineering Technologies and Management Research 6, no. 6 (2020): 40–50. http://dx.doi.org/10.29121/ijetmr.v6.i6.2019.392.

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In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The performance depends on power consumption and delay. Adders are not only used for arithmetic operations, but also for calculating addresses and indices. In digital design we have half adder and full adder, by using these adders we can implement ripple carry adder (RCA). RCA is used to perform any number of additions. In this RCA is serial adder and it has propagation delay problem. With increas
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7

Ali, Mohamed Syed. "Cascaded Ripple Carry Adder Based SRCSA for Efficient FIR Filter." Indonesian Journal of Electrical Engineering and Computer Science 9, no. 2 (2018): 253. http://dx.doi.org/10.11591/ijeecs.v9.i2.pp253-256.

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<p>Filter is one of the key components of all signals processing elements. Both the FIR and IIR filter are used to reduce the unwanted signal in the original signal. Here discussing the FIR filter and design the efficient FIR filter using Dual Ripple Carry Adder (RCA) based SQRT-carry select adder (CSLA). Many components present in the FIR filter, one of the main component is Adder. Adder is used to combine the signal for avoid the noise occurring in the output. Proposed a Dual RCA based SQRT-CSLA for speed up the filtering process. The filter performance can be analyzed by Xilinx simula
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Mohamed, Syed Ali. "Cascaded Ripple Carry Adder based SRCSA for Efficient FIR Filter." Indonesian Journal of Electrical Engineering and Computer Science 9, no. 2 (2018): 253–56. https://doi.org/10.11591/ijeecs.v9.i2.pp253-256.

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Filter is one of the key components of all signals processing elements. Both the FIR and IIR filter are used to reduce the unwanted signal in the original signal. Here discussing the FIR filter and design the efficient FIR filter using Dual Ripple Carry Adder (RCA) based SQRT-carry select adder (CSLA). Many components present in the FIR filter, one of the main component is Adder. Adder is used to combine the signal for avoid the noise occurring in the output. Proposed a Dual RCA based SQRT-CSLA for speed up the filtering process. The filter performance can be analyzed by Xilinx simulation envi
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Hoe, David H. K., L. P. Deepthi Bollepalli, and Chris D. Martinez. "FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders." VLSI Design 2013 (November 7, 2013): 1–10. http://dx.doi.org/10.1155/2013/382682.

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This paper examines fault tolerant adder designs implemented on FPGAs which are inspired by the methods of modular redundancy, roving, and gradual degradation. A parallel-prefix adder based upon the Kogge-Stone configuration is compared with the simple ripple carry adder (RCA) design. The Kogge-Stone design utilizes a sparse carry tree complemented by several smaller RCAs. Additional RCAs are inserted into the design to allow fault tolerance to be achieved using the established methods of roving and gradual degradation. A triple modular redundant ripple carry adder (TMR-RCA) is used as a point
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10

Alkurwy, Salah Hasan, and Isam Salah Hameed. "A novel pipelined carry adder design based on half adder." Indonesian Journal of Electrical Engineering and Computer Science 25, no. 2 (2022): 763. http://dx.doi.org/10.11591/ijeecs.v25.i2.pp763-770.

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<span lang="EN-US">A new design of binary parallel adder circuit is presented in this paper. The pipeline technique is applied to implement a group of a half adder (HA) blocks to architect the proposed adder. The pipelined carry adder (PCA) method is suitable for carrying out the desired adder by using the HA circuits of XOR and AND gates. The applied technique reduces the critical path delay by 27% compared with the ripple carry adder (RCA) and relatively lowers logic gates by 55% compared with the carry look-ahead adder (CLA). The coded design of the proposed circuit is implemented and
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Dissertations / Theses on the topic "Ripple carry adder (RCA)"

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Wei, Lan. "Implementation of Pipelined Bit-parallel Adders." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1943.

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<p>Bit-parallel addition can be performed using a number of adder structures with different area and latency. However, the power consumption of different adder structures is not well studied. Further, the effect of pipelining adders to increase the throughput is not well studied. In this thesis four different adders are described, implemented in VHDL and compared after synthesis. The results give a general idea of the time-delay-power tradeoffs between the adder structures. Pipelining is shown to be a good technique for increasing the circuit speed.</p>
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Åslund, Anders. "Power Estimation of High Speed Bit-Parallel Adders." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2390.

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<p>Fast addition is essential in many DSP algorithms. Various structures have been introduced to speed up the time critical carry propagation. For high throughput applications, however, it may be necessary to introduce pipelining. In this report the power consumption of four different adder structures, with varying word length and different number of pipeline cuts, is compared. </p><p>Out of the four adder structures compared, the Kogge-Stone parallel prefix adder proves to be the best choice most of the time. The Brent-Kung parallel prefix adder is also a good choice, but the maximal throughp
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Fang, Chih-Jen, and 方智仁. "Fast and Compact Dynamic Ripple Carry Adder Design." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/30444709334677092076.

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碩士<br>國立中正大學<br>電機工程研究所<br>90<br>Adders are fundamental building blocks and often constitute part of the critical path. The maximum operating speed of a Ripple Carry Adder (RCA) is limited by the carry propagation delay, and the penalty of the propagation delay depends on the number of primary input bits. In this paper, we propose four high-speed and compact ripple carry adder designs. The key techniques of these novel designs are race-free dynamic CMOS logic technique for high-speed and compact designs. We demonstrate these designs approach using a 32-bit ripple carry adder built
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Behera, Chinmay Kumar, and S. K. Barman. "Design of booth multiplier using ripple carry adder." Thesis, 2014. http://ethesis.nitrkl.ac.in/6012/1/110EI0235-10.pdf.

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Modern IC Technology focuses on the planning of ICs considering additional space improvement and low power techniques. Multiplication may be a heavily used operation that figures conspicuously in signal process and scientific applications. Multiplication may be a terribly hardware intensive subject and thus we as users area unit largely involved with obtaining low-power, smaller space and better speed. The foremost necessary concern in classic multiplication largely accomplished by K-cycles of shifting and adding, is to hurry up underlying multi-operand addition of partial product. During this
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Book chapters on the topic "Ripple carry adder (RCA)"

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Arunakumari, S., K. Rajasekahr, S. Sunithamani, and D. Suresh Kumar. "Carry Select Adder Using Binary Excess-1 Converter and Ripple Carry Adder." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-2308-1_30.

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Mohan, Shoba, and Nakkeeran Rangaswamy. "Design of Ripple Carry Adder Using GDI Logic." In Proceedings of the International Conference on Soft Computing Systems. Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2671-0_51.

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Kishore, Pinninti, P. V. Sridevi, and K. Babulu. "Low Power and Optimized Ripple Carry Adder and Carry Select Adder Using MOD-GDI Technique." In Lecture Notes in Electrical Engineering. Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2728-1_15.

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Nagaraj, S., K. Sai Khyathi, and K. Pavansai. "Design of Energy Efficient Reversible Full Adder and Ripple Carry Adder for Digital Computing Applications." In Intelligent Manufacturing and Energy Sustainability. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-6774-2_18.

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Mewada, Manan, Mazad Zaveri, and Anurag Lakhlani. "Estimating the Maximum Propagation Delay of 4-bit Ripple Carry Adder Using Reduced Input Transitions." In Communications in Computer and Information Science. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-7470-7_2.

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Datta, Kakali, Debarka Mukhopadhyay, and Paramartha Dutta. "Design of Ripple Carry Adder Using 2-Dimensional 2-Dot 1-Electron Quantum-Dot Cellular Automata." In Advances in Intelligent Systems and Computing. Springer India, 2016. http://dx.doi.org/10.1007/978-81-322-2755-7_27.

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Roy, Rupsa, Swarup Sarkar, and Sourav Dhar. "Physical Design and Implementation of Multibit Multilayer 3D Reversible Ripple Carry Adder Using “QCA-ES” Nanotechnique." In Advances in Communication, Devices and Networking. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-2911-2_5.

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Kadam, Kanchan, and Swati S. Shetkar. "Design and Implementation of Power Efficient 4 Bit Ripple Carry Adder Using 14 nm FinFET Technology." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-7985-8_68.

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Saxena, Naman, Shruti Dutta, Neeta Pandey, and Kirti Gupta. "Implementation and Performance Comparison of a Four-Bit Ripple-Carry Adder Using Different MOS Current Mode Logic Topologies." In Computational Science and Its Applications – ICCSA 2017. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-62407-5_21.

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Srividhya, G., T. Sivasakthi, R. Srivarshini, P. Varshaa, and S. Vijayalakshmi. "Enhanced and Efficient Carry Select Adder with Minimal Delay." In Advances in Parallel Computing. IOS Press, 2021. http://dx.doi.org/10.3233/apc210102.

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In today’s digital world, Arithmetic computations have been evolved as a core factor in digital signal processors, micro-controllers, and systems using arithmetic and logical operations such as adders, multipliers, image processors, and signal processors. One of the elements that play an important role in performing arithmetic calculations is an adder. Among many adders, the Carry Select Adder produces less propagation delay. However, there may be an increased delay, power consumption, and area required in the case of a normal Carry Select Adder. To overcome the mentioned drawbacks, an improve
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Conference papers on the topic "Ripple carry adder (RCA)"

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Akter, Jesmin, and Rahimul I. Mazumdar. "Efficient Design and Implementation of a 4-Tap FIR Filter Using Braun Multiplier and Ripple Carry Adder (RCA)." In 2025 3rd International Conference on Intelligent Systems, Advanced Computing and Communication (ISACC). IEEE, 2025. https://doi.org/10.1109/isacc65211.2025.10969293.

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Kumaar A, Deepan, P. R. Ajithkumar, T. K. Giriprasath, and Senthamizh Selvi R. "An Efficient Ripple Carry Adder Using Pipelining." In 2024 International Conference on Innovation and Novelty in Engineering and Technology (INNOVA). IEEE, 2024. https://doi.org/10.1109/innova63080.2024.10847016.

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K, Dharsan, Dineshkumar G, and Ramesh S. R. "Area-Optimized and Low Power Ripple Carry Adder." In 2024 IEEE Silchar Subsection Conference (SILCON). IEEE, 2024. https://doi.org/10.1109/silcon63976.2024.10910664.

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C, Trupthi M., and D. Savitha. "Design of Ripple Carry Adder Using Cadence Virtuoso 180Nm Technology." In 2025 3rd International Conference on Smart Systems for applications in Electrical Sciences (ICSSES). IEEE, 2025. https://doi.org/10.1109/icsses64899.2025.11009717.

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V, Senbagaseelan, Ragul T, Subbulakshmi A, and R. Rajesh Kanna. "Design and Implementation of a 4-Bit Carry Select Adder using MTCMOS-Based Ripple Carry Adder with 10T Full Adders in 90nm Technology." In 2025 International Conference in Advances in Power, Signal, and Information Technology (APSIT). IEEE, 2025. https://doi.org/10.1109/apsit63993.2025.11086236.

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Kumar, Aruru Sai, P. Santhosh, N. Neelima, Barama Veda Harshitha, D. Suvarna Aishwarya Lakshmi, and Katkam Shashi Vardhan. "A Novel ASK Reversible Gate and its Implementation in Ripple Carry Adder Design." In 2024 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON). IEEE, 2024. https://doi.org/10.1109/edkcon62339.2024.10870774.

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Lakshmi Naga Chetana, B., C. Purna Sai Sandeep, K. Vasamth, S. Radha, C. V. Narasimhulu, and K. Sai Krishna. "An Efficient Selection Gate Logic Based Ripple Carry Adder for Deep Learning Networks." In 2024 2nd International Conference on Recent Trends in Microelectronics, Automation, Computing and Communications Systems (ICMACC). IEEE, 2024. https://doi.org/10.1109/icmacc62921.2024.10894497.

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Dharani, M., Dudekonda Upendra, Bathula Surendra Babu, Bingi Sathwika, and Chinnepalli Harika. "Efficient Clocking Strategies for Adiabatic Quantum-Flux-Parametron 8-bit Ripple Carry Adder Implementation." In 2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS). IEEE, 2024. http://dx.doi.org/10.1109/iciteics61368.2024.10625097.

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Juneja, Sagar, Deepika Bansal, and Kulbhushan Sharma. "Low-power and High-speed CNTFET based Four-bit Static Approximate Modified Mirror Ripple Carry Adder for Image Processing." In 2025 Devices for Integrated Circuit (DevIC). IEEE, 2025. https://doi.org/10.1109/devic63749.2025.11012517.

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Balatero, Phoebe Nicole L., Jhanine J. Galang, Trisha Mae M. Gonzales, and Arcel Salem-Diaz. "Design of a Low-Power 4x4 Wallace Tree Multiplier Using Ripple Carry Adder at 10 MHz in 180nm CMOS Techology." In 2024 23rd International Symposium on Communications and Information Technologies (ISCIT). IEEE, 2024. https://doi.org/10.1109/iscit63075.2024.10793598.

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