Dissertations / Theses on the topic 'Self-test and reliability'

Si on veut assurer de facon efficace les tests de conception, de fabrication, de maintenance et le test accompli au cours de l'application pour les systemes electroniques, on est amene a integrer le test hors-ligne et le test en-ligne dans des circuits. Ensuite, pour que les systemes complexes tirent profit des deux types de tests, une telle unification doit etre etendue du niveau circuit aux niveaux carte et module. D'autre part, bien que l'integration des techniques de test hors-ligne et en-ligne fait qu'il est possible de concevoir des systemes pour toute application securitaire, le materiel ajoute pour assurer une haute surete de fonctionnement fait que la fiabilite de ces systemes est reduite, car la probabilite d'occurrence de fautes augmente. Confrontee a ces deux aspects antagoniques, cette these se fixe l'objectif de trouver un compromis entre la securite et la fiabilite de systemes electroniques complexes. Ainsi, dans un premier temps, on propose une solution aux problemes de test hors-ligne et de diagnostic qui se posent dans les etapes intermediaires de l'evolution vers les cartes 100% compatibles avec le standard IEEE 1149. 1 pour le test "boundary scan". Une approche pour le BIST ("Built-In Self-Test") des circuits et connexions "boundary scan" illustre ensuite l'etape ultime du test hors-ligne de cartes. Puis, le schema UBIST ("Unified BIST") - integrant les techniques BIST et "self-checking" pour le test en-ligne de circuits, est combine au standard IEEE 1149. 1, afin d'obtenir une strategie de conception en vue du test unifie de connexions et circuits montes sur des cartes et modules. Enfin, on propose un schema tolerant les fautes et base sur la duplication de ces modules securitaires qui assure la competitivite du systeme resultant du point de vue de la fiabilite, tout en gardant sa sureté inherente<br>On one hand, if the goal is to ensure that the design validation, the manufacturing and the maintenance testing, along with the concurrent error detection are efficiently performed in electronic systems, one is led to integrate the off-line and the on-line testing into circuits. Then, for complex systems to make profit of these two types of tests, such unification must be extended from the circuit to the board and module levels. On the other hand, although the unification of off-line and on-line testing techniques makes possible the design of systems suiting any safety application, the hardware added for increasing the application safety also decreases the system availability and reliability, since the probability of occurrence of faults increases. Faced to these two antagonist aspects, this thesis aims at finding a compromise between the safety and the reliability of complex electronic systems. Thus, firstly we propose a solution to the off-line test and diagnosis problems found in the intermediate steps in the evolution towards boards which are 100% compliant with the IEEE standard for boundary scan testing. An approach for the BIST (Built-In Self-Test) of boundary scan circuits and interconnects then illustrates the ultimate step in the board off-line testing. Next, the UBIST (Unified BIST) scheme - merging BIST and self-checking capabilities for circuit on-line testing, is combined with the IEEE standard for boundary scan testing, in order to obtain a design strategy for unifying the tests of interconnects and circuits populating boards and modules. Finally, we propose a fault-tolerant scheme based on the duplication of these kind of modules which ensures the competitivity of the resulting system in terms of reliability at the same time as preserving the inherent module safety

Este trabalho tem como objetivo realizar um estudo do problema de teste de circuitos analógicos e mistos, propondo uma metodologia de teste e apresentando uma ferramenta para geração automática de vetores de teste (ATPG). A necessidade deste tipo de pesquisa torna-se clara no momento em que um número cada vez maior de aplicações requer algum tipo de interação entre dispositivos analógicos e digitais, não só em se tratando de placas de circuito impresso, mas também em um mesmo circuito integrado. A metodologia prevê a detecção de falhas paramétricas, de grandes desvios e catastróficas em circuitos lineares e não-lineares. Além disso. a ocorrência de falhas de interação é considerada, assim como a definição de vetores para diagnóstico que garantam máxima cobertura de falhas. Inicialmente são apresentados alguns aspectos teóricos relacionados ao teste deste tipo de circuitos (complexidade do teste, abordagens existentes e trabalhos correlatos). A seguir, são apresentados o modelo de falhas utilizado e a metodologia proposta, bem como a ferramenta de ATPG. A técnica é aplicada, então, a dois circuitos. O processo de geração dos vetores de teste é explicado e exemplos de vetores gerados são apresentados. Posteriormente, uma proposta de automatização do método é feita, acompanhada da descrição de algumas ferramentas comerciais utilizadas. Por fim, os resultados e conclusões são apresentados.<br>This work aims at studying the testing problems related to analog and mixedsignal circuits. This kind of research is very useful nowadays, since there is a great demand for circuits that need some kind of interaction between analog and digital blocks. This document presents a method and an automatic test pattern generation tool aplicable to the detection of soft, large and hard fault in linear and non-linear circuits. This method considers, also, interaction faults and computes diagnose vectors that garantee maximal fault coverage. At first. a brief review of methods. approaches and related works is presented. Then. the fault model used and the test methodology are defined. and an ATPG tool is proposed. Next, the ATPG algorithm is applied to a linear and to a non-linear circuit. The test vector generation process and the test vectors computed are then shown. After that a way to automatize the ATPG tool is discussed under the light of those commercial tools that were used in this work. Finally. the conclusions and results are presented.

Background: Patient empowerment is viewed as a priority by policy makers, patients and practitioners worldwide. Although there are a number of measures available, none have been developed specifically for patients in the UK with long-term conditions. It is the aim of this study to report the development and preliminary validation of an empowerment instrument for patients with long-term conditions in primary care.Methods: The study involved three methods. Firstly, a systematic review was conducted to identify existing empowerment instruments, and to describe, compare and appraise their content and quality. The results supported the need for a new instrument. Item content of existing instruments helped support development of the new instrument. Secondly, empowerment was explored in patients with long-term conditions and primary care practitioners using qualitative methods, to explore its meaning and the factors that support or hinder empowerment. This led to the development of a conceptual model to support instrument development. Thirdly, a new instrument for measuring empowerment in patients with long-term conditions in primary care was developed. A cross-sectional survey of patients was conducted to collect preliminary data on acceptability, reliability and validity, using pre-specified hypotheses based on existing theoretical and empirical work. Results: Nine instruments meeting review inclusion criteria were identified. Only one instrument was developed to measure empowerment in long-term conditions in the context of primary care, and that was judged to be insufficient in terms of content and purpose. Five dimensions (‘identity’, ‘knowledge and understanding’, ‘personal control’, personal decision-making’, and ‘enabling other patients’) of empowerment were identified through published literature and the qualitative work and incorporated into a preliminary version of the new instrument. A postal survey achieved 197 responses (response rate 33%). Almost half of the sample reported circulatory, diabetic or musculoskeletal conditions. Exploratory factor analysis suggested a three factor solution (‘identity’, ‘knowledge and understanding’ and ‘enabling’). Two dimensions of empowerment (‘identity’ and ‘enabling’) and total empowerment showed acceptable levels of internal consistency. The measure showed relationships with external measures (including quality of chronic illness care, self-efficacy and educational qualifications) that were generally supportive of its construct validity.Conclusion: Initial analyses suggest that the new measure meets basic psychometric criteria and has potential for the measurement of patient empowerment in long-term conditions in primary care. The scale may have a role in research on quality of care for long-term conditions, and could function as a patient-reported outcome measure. However, further validation is required before more extensive use of the measure.

Introduction: People who have disabilities are often deprived of opportunities to be involved in daily life situations. While research attempts to explore the participation patterns of individuals with disabilities, there is a paucity of studies that have obtained the personal opinions of participation from children with intellectual disabilities, and none that have obtained personal opinions (self-reports) from children living in low- to middle-income (LAMI) countries. Reasons for this are thought to be the lack of measures and methods available for obtaining self-reports from children with intellectual disabilities. The Picture my Participation (PMP) instrument has been developed for use in LAMI countries and when used with the Talking MatsTM framework, ensures that the views of children with intellectual disabilities can be obtained. This study aimed to assess the test-retest reliability of the PMP instrument. Methods: Sixteen children aged 12 to 17 years with intellectual disabilities and their primary caregivers took part in this study. Each participant pair was required to complete the Picture My Participation survey twice in a space of two weeks. Cronbach’s alpha coefficient and Spearman’s rank order were used to measure internal consistency and test-retest reliability. Results and conclusions: While the questionnaire yielded high alpha values, indicating high internal consistency, the values for test-retest reliability were incomparable due to a small sample size and limited data. Further study is required with a larger and more diverse data sample.<br>Mini Dissertation (MAAC)--University of Pretoria, 2018.<br>This research forms part of an international project jointly funded by the National Research Foundation (NRF)/ STINT. Opinions expressed and conclusions arrived at are those of the author and are not necessarily to be attributed to the NRF/ STINT.<br>Centre for Augmentative and Alternative Communication (CAAC)<br>MAAC<br>Unrestricted

L'intelligence artificielle et les algorithmes d'apprentissage automatique sont au sommet du marché de la technologie de nos jours. Dans ce contexte, les accélérateurs matériels d'IA devraient jouer un rôle de plus en plus primordial pour de nombreuses applications, surtout ceux ayant une mission critique et un haut niveau de sécurité. Cela nécessite d'évaluer leur fiabilité et de développer des techniques peu coûteuses de tolérance aux fautes; un problème qui reste largement inexploré pour les puces neuromorphiques et les réseaux de neurones impulsionnels. Il est souvent présumé que la fiabilité et la résilience aux erreurs dans les Réseaux de Neurones Artificiels sont intrinsèquement obtenues grâce au parallélisme, à la redondance structurelle et à la ressemblance avec les réseaux de neurones biologiques. Cependant, des travaux antérieurs dans la littérature ont révélé le non-fondement de cette hypothèse et ont exposé la vulnérabilité des ANN aux fautes. Dans cette thèse, nous abordons le sujet de test et de la tolérance aux fautes pour les SNNs matériels. Nous abordons tout d’abord la question du test de post-fabrication des réseaux de neurones matériels et de leur autotest orienté sur le comportement. Puis, nous nous dirigeons vers une solution globale pour l'accélération des tests et l'analyse de la résilience des SNN contre les défauts au niveau matériel. Après ça, nous proposons une stratégie de tolérance aux fautes des neurones pour les SNNs qui a été optimisée afin de minimiser les surcoûts en surface et puissance du circuit. Enfin, nous présentons une étude de cas matériel qui serait utilisée comme plateforme pour démontrer les expériences d'injection de fautes<br>Artificial Intelligence (AI) and machine learning algorithms are taking up the lion's share of the technology market nowadays, and hardware AI accelerators are foreseen to play an increasing role in numerous applications, many of which are mission-critical and safety-critical. This requires assessing their reliability and developing cost-effective fault tolerance techniques; an issue that remains largely unexplored for neuromorphic chips and Spiking Neural Networks (SNNs). A tacit assumption is often made that reliability and error-resiliency in Artificial Neural Networks (ANNs) are inherently achieved thanks to the high parallelism, structural redundancy, and the resemblance to their biological counterparts. However, prior work in the literature unraveled the falsity of this assumption and exposed the vulnerability of ANNs to faults. This requires assessing their reliability and developing cost-effective fault tolerance techniques; an issue that remains largely unexplored for neuromorphic chips and Spiking Neural Networks (SNNs). In this thesis, we tackle the subject of testing and fault tolerance in hardware SNNs. We start by addressing the issue of post-manufacturing test and behavior-oriented self-test of hardware neurons. Then we move on towards a global solution for the acceleration of testing and resiliency analysis of SNNs against hardware-level faults. We also propose a neuron fault tolerance strategy for SNNs, optimized for low area and power overhead. Finally, we present a hardware case-study which would be used as a platform for demonstrating fault-injection experiments and fault-tolerance capabilities

De nos jours, les circuits FPGAs à base de mémoire SRAM sont omniprésents dans les applications électroniques embarquées. Ainsi, ces circuits sont devenus un acteur principal dans l’amélioration du rendement de l’ensemble du spectre des systèmes-sur-puce (SoC). Néanmoins, les pannes se sont accentuées dans ces technologies émergentes, qu’il s’agisse de pannes permanentes provenant d’une forte densité d’intégration, associée à une complexité élevée des procédés de fabrication, ou de pannes transitoires découlant des particules chargées qui heurtent les FPGAs dans leurs environnements d’exploitation. La tolérance aux pannes des circuits FPGAs à base de mémoire SRAM est donc un paramètre essentiel pour assurer la sûreté de fonctionnement des applications implémentées. Dans le cadre de cette thèse, nous proposons une stratégie de tolérance aux pannes qui s’accommode des contraintes de fiabilité pour un système implémenté dans un FPGA à base de mémoire SRAM. Cette stratégie présente une grande flexibilité et un coût faible comparé à la technique de la redondance modulaire triple (TMR), et permet la gestion en temps d’exécution qui est une caractéristique importante pour les applications critiques. Dans cette thèse, nous proposons également des tests spécifiques, appelés algorithmes March, qui permettent de détecter les pannes intra-mots dans la mémoire de configuration d’un circuit FPGA- SRAM. Ces tests présentent l’avantage de bénéficier d’une implémentation rapide et d’obtenir un taux de couverture élevé<br>Nowadays, SRAM-based FPGAs are omnipresent for embedded electronic applications. Consequently, these circuits became the key player of the overall System-On-Chip (SoC) yield enhancement. However, faults are increasingly pronounced in these emergent technologies, from permanent faults arising from circuit processing at nanometer scales to transient soft errors arising from high-energy particle hits. So fault-tolerance of SRAM-based FPGA is an important system metric to ensure the dependability of embedded applications. The first part of this thesis exposes a comprehensive technique to cope with multiple faults in applications implemented in SRAM-based FPGA without incurring substantial area, power, or performance penalties. This approach has three main benefits compared to redundancy-based fault-tolerance: it’s very low overhead, the option for runtime management, and its complete flexibility. Run-time management can be a very valuable feature of a system, particularly for mission-critical applications. This fault-tolerance approach handles runtime problems on-line, minimizing the amount of system downtime and eliminating the need for outside intervention. The last part of this thesis is oriented toward configuration memory array of SRAM-based FPGA test and diagnostic. New fault models in configuration frames and March algorithms are proposed. These tests have the advantage to benefit from a fast implementation and achieving high fault coverage

Si on veut assurer de fawn efficace les tests de conception, de fabrication, de maintenance et le test accompli au cours de l'application pour les systemes electroniques, on est amend a integrer le test hors-ligne et le test en-ligne dans des circuits. Ensuite, pour que les systemes complexes tirent profit des deux types de tests, une telle unification doit etre &endue du niveau circuit aux niveaux carte et module. D'autre part, bien que rintegration des techniques de test hors-ligne et en-ligne fait qu'il est possible de concevoir des systemes pour toute application securitaire, le materiel ajoute pour assurer une haute siirete de fonctionnement fait que la fiabilite de ces systemes est reduite, car la probabilite d'occurrence de fautes augmente. Confront& a ces deux aspects antagoniques, cette these se fixe l'objectif de trouver un compromis entre la securite et la fiabilite de systemes electroniques complexes. Ainsi, dans un premier temps, on propose une solution aux problemes de test hors-ligne et de diagnostic qui se posent dans les &apes intermediaires de revolution vers les cartes 100% compatibles avec le standard IEEE 1149.1 pour le test "boundary scan". Une approche pour le BIST ("Built-In Self-Test") des circuits et connexions "boundary scan" illustre ensuite retape ultime du test hors-ligne de cartes. Puis, le schema UBIST ("Unified BIST") - integrant les techniques BIST et "self-checking" pour le test en-ligne de circuits, est combine au standard IEEE 1149.1, afin d'obtenir une strategie de conception en vue du test unifie de connexions et circuits montes sur des cartes et modules. Enfin, on propose un schema tolerant les fautes et base sur la duplication de ces modules securitaires qui assure la competitivite du systeme resultant du point de vue de la fiabilite, tout en gardant sa silrete inherente.<br>On one hand, if the goal is to ensure that the design validation, the manufacturing and the maintenance testing, along with the concurrent error detection are efficiently performed in electronic systems, one is led to integrate the off-line and the on-line testing into circuits. Then, for complex systems to make profit of these two types of tests, such unification must be extended from the circuit to the board and module levels. On the other hand, although the unification of off-line and on-line testing techniques makes possible the design of systems suiting any safety application, the hardware added for increasing the application safety also decreases the system reliability, since the probability of occurrence of faults increases. Faced to these two antagonist aspects, this thesis aims at finding a compromise between the safety and the reliability of complex electronic systems. Thus, firstly we propose a solution to the off-line test and diagnosis problems found in the intermediate steps in the evolution towards boards which are 100% compliant with the IEEE standard 1149.1 for boundary scan testing. An approach for the BIST (Built-In Self-Test) of boundary scan circuits and interconnects then illustrates the ultimate step in the board off-line testing. Next, the UBIST (Unified BIST) scheme - merging BIST and self-checking capabilities for circuit on-line testing, is combined with the IEEE standard 1149.1, in order to obtain a design strategy for unifying the tests of interconnects and circuits populating boards and modules. Finally, we propose a fault-tolerant scheme based on the duplication of these kind of modules which ensures the competitivity of the resulting system in terms of reliability at the same time as preserving the inherent module safety.

碩士<br>國立陽明大學<br>腦科學研究所<br>103<br>Background: Sleep disorders have become a common disease in recent years and we pay more attention on sleep detecting gradually. Polysomnography (PSG) is the gold standard for assessing sleep quality, but it needs high cost and long set-up time which is not suitable for public. Actigraphy, is low cost, small size, set up fast, and long-term recording, can be used to distinguish sleep and detect activities. As we known, detecting sleep/wake pattern by using actigraphy is more convenient and less-cost than traditional sleep detecting tool, also can long-term recording. However, because of low accuracy, using actigraphy on sleep scoring and physical activity detecting is still not well-estimated. Aim: To raise the accuracy of actigraphy in distinguishing sleep/wake patterns and application for long-distance health care, we develop sleep/wake discrimination algorithm by laboratory actigraphy, and the comparison with polysomnography (PSG) by using sleep scoring and commercial actiwatch to confirm sleep/wake analysis function. Methods: Each participant carried a laboratory actigraphy with the function of sleep/wake pattern analysis (KY9, K&;Y lab, Taiwan, size: 3.5 x 3.5 x 0.6 cm3, weight: 16 g), a commercial actigraphy (Actiwatch, Actigraph, wActiSleep-BT Monitor, Pensacola) as well as a miniature PSG (TD1, Taiwan Telemedicine Device Company, Taiwan) for 24 hours recording. We compared the results which from the laboratory sleep/wake patterns analysis, standard sleep/wake scoring system and commercial actiwatch. Results: The correlation between TD1 and KY9 by the Pearson linear regression was higher than the correlation between TD1 and commercial actiwatch in total sleep time (r = 0.98, p < 0.001). The Bland-Altman plot used to calculate the variation of KY9 and Actiwatch between TD1 showed that KY9 was better than commercial actiwatch in stability (p = 0.02). Moreover, the similarity between KY9 and TD1 of the sleep parameters, including sleep efficiency (SE) and wakening time after sleep onset (WASO) was higher than commercial actiwatch (p < 0.01). Conclusion: The laboratory-made actigraphy with our developed sleep/wake discrimination analysis have higher accuracy for sleep/wake scoring than the commercial actiwatch, especially in total sleep time. This can provide low power and more convenient sleep monitoring technique with great stability and consistency; even combine cloud computing technique to raise the life quality for general population.

Emotional intelligence has attracted a considerable amount of attention over the past few years specifically with regard to the nature of the underlying construct and the reliability and validity of the psychometric tools used to measure the construct. The present study explored the reliability and validity of a trait measure of EI in relation to an ability measure in order to determine whether the tools can be considered as measuring conceptually valid constructs within an occupational environment. The study also examined the overlap with a trait measure of cognitive thinking styles to determine the potential for separating the trait and ability EI into two unique and distinguishable constructs. Participants included 308 employees from four different workforces within a diverse South African consulting firm. The results of the study identified a number of psychometric concerns regarding the structural fidelity of the instruments as well as concerns about the cultural bias evident in both measurement instruments. Evidence for the discriminant and incremental validity of the two instruments was, however, provided and recommendations are made for the reconceptualisation of trait EI as an emotional competence and ability EI as an emotional intelligence.<br>Psychology<br>D. Litt. et Phil. (Psychology)