Relevant bibliographies by topics / Semiconductor chip protection

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Semiconductor chip protection'

Author: Grafiati
Published: 2 June 2025
Last updated: 31 July 2025

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Journal articles on the topic "Semiconductor chip protection"

1

Greguras, Fred M., and Neal M. Williams. "US semiconductor chip protection act." Computer Fraud & Security Bulletin 7, no. 7 (1985): 4–12. http://dx.doi.org/10.1016/0142-0496(85)90027-x.

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Chesser, James. "Semiconductor Chip Protection: Changing Roles for Copyright and Competition." Virginia Law Review 71, no. 2 (1985): 249. http://dx.doi.org/10.2307/1073018.

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3

SAMUELS, LINDA B., and JEFFREY M. SAMUELS. "SEMICONDUCTOR CHIP PROTECTION ACT OF 1984: AN ANALYTICAL COMMENTARY." American Business Law Journal 23, no. 4 (1985): 601–16. http://dx.doi.org/10.1111/j.1744-1714.1985.tb01584.x.

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4

Rose, Simone A. "Semiconductor Chips, Genes, and Stem Cells: New Wine for New Bottles?" American Journal of Law & Medicine 38, no. 1 (2012): 113–57. http://dx.doi.org/10.1177/009885881203800102.

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This Article analogizes early semiconductor technology and its surrounding economics with isolated genes, stem cells, and related bioproducts, and their surrounding economics, to make the case for sui generis (of its own class) intellectual property protection for isolated bioproducts. Just as early semiconductors failed to meet the patent social bargain requiring novelty and non-obviousness in the 1980s, isolated genes and stem cells currently fail to meet the patent bargain requirements of non-obviousness and eligible subject matter that entitle them to traditional intellectual property prot
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Yuan, Qi Ping, Tian Mei Zheng, Zheng Rong Tong, Xiu Feng Yang, and Ye Cao. "A Method of Stabilizing Semiconductor Laser Power." Applied Mechanics and Materials 130-134 (October 2011): 1370–73. http://dx.doi.org/10.4028/www.scientific.net/amm.130-134.1370.

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For the influence of the temperature and current, the power of semiconductor laser fluctuates constantly. So this paper comes up with a new method to solve this problem. The design of peripheral circuit contains two parts: temperature control and power control. The system of temperature control uses special laser temperature control chip, which realizes the accuracy of 0.01°C. The system of power control adopts hardware PI control, over-current protection, over-voltage protection, and temperature protection. Temperature compensation is added to the circuit, which realizes the accuracy of 0.01m
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Zhao, Qixin, Xiangyi Liu, Hanbing Wang, et al. "Research Progress in Corrosion Protection Technology for Electronic Components." Metals 13, no. 9 (2023): 1508. http://dx.doi.org/10.3390/met13091508.

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As a necessary part of all electronic devices, equipment and systems, electronic components play a vital role in the global economy. Since the corrosion of a single electronic component may directly affect the normal operation of the entire electronic system, the failure of electronic components has now become the most important cause of electrical system failure and has become a major obstacle to China’s transformation into a scientific and technological power. Therefore, it is urgent to study the corrosion failure process of electronic components and the means of effective protection. In thi
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7

Liang, Hailian, Jianfeng Li, Jun Sun, et al. "High-Voltage Electrostatic Discharge/Electrical Overstress Co-Protection Implementing Gradual-Triggered SCR and MOS-Stacked Configuration." Electronics 14, no. 6 (2025): 1076. https://doi.org/10.3390/electronics14061076.

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This paper proposes a monolithic electrostatic discharge/electrical overstress (ESD/EOS) co-protection device featuring gradual triggering by silicon-controlled rectifier (SCR) and metal–oxide semiconductor (MOS) structures, demonstrating enhanced voltage clamping and current-conducting capabilities. Compared with conventional PMOS-triggered SCR (PMOS-SCR) for ESD protection, the proposed dual-PMOS-triggered SCR (DPMOS-SCR) architecture within a compact area achieves monolithic ESD/EOS protection performance due to the strategic semiconductor structures integration. ESD measurement results sho
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8

Sung, Guo-Ming, Shih-Hao Chen, Venkatesh Choppa, and Chih-Ping Yu. "Hybrid Radio-Frequency-Energy- and Solar-Energy-Harvesting-Integrated Circuit for Internet of Things and Low-Power Applications." Electronics 14, no. 11 (2025): 2192. https://doi.org/10.3390/electronics14112192.

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This paper proposes a hybrid energy-harvesting chip that utilizes both radio-frequency (RF) energy and solar energy for low-power applications and extended service life. The key contributions include a wide input power range, a compact chip area, and a high maximum power conversion efficiency (PCE). Solar energy is a clean and readily available source. The hybrid energy harvesting system has gained popularity by combining RF and solar energy to improve overall energy availability and efficiency. The proposed chip comprises a matching network, rectifier, charge pump, DC combiner, overvoltage pr
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Sidiki, Tamim. "Polyamide 4T: A New Lead-Free Solderable Polymer Enabling Packaging Technology Through Micro Molding and LDS." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, DPC (2010): 001563–84. http://dx.doi.org/10.4071/2010dpc-wa43.

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The continuous trend towards convergence and miniaturization is recently generating significant interest in new technologies for Electronics. This requires the integration of Semiconductors and Magnetics, two entirely different industries with different players in the value chain. In this paper, we demonstrate, a packaging technology which allows three dimensional stacking of Magnets and Semiconductors. We realized the integration of a Semiconductor chip - which provides protection against electro static discharge (ESD) – and a common mode filter (CMF) into one thermoplastic package. For the f
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Xu, Yan Hui, and Dan Tong Zhang. "Research on One Kind of Intellectualization High Accuracy Digital Adjustment Direct Source." Applied Mechanics and Materials 599-601 (August 2014): 608–11. http://dx.doi.org/10.4028/www.scientific.net/amm.599-601.608.

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The power source uses the digital adjustment, the closed loop real-time monitoring.The output precision is vary high. It also has both the dual over-load protection and alarm, which is suitable especially in each kind situation of the high accuracy request.This design intellectualization direct-current power supply uses the self-restraint keyboard entry. The system of intellectualization high accuracy digital adjustmen direct source contains D/A module and A/D module . D/A module adopts low-priced 8 bits DA chip. DAC0832 is a electric current exports type 8 bits D/A converter , adopting to rev
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Dissertations / Theses on the topic "Semiconductor chip protection"

1

Joe, Raymond K. (Raymond Kim). "Reconfiguring intellectual property for cyberspace : a lok at the Semiconductor Chip Protection Act of 1984." Thesis, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/36631.

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Books on the topic "Semiconductor chip protection"

1

Hertz, Allen Zangwil. Semiconductor chip protection in Canada: Proposals for legislation. Consumer and Corporate Affairs Canada, 1987.

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2

E, Leibowitz David, and Joseph Bruce G, eds. Protection for semiconductor chip masks in the United States: Analysis of the Semiconductor Chip Protection Act of 1984. Max Planck Institute for Foreign and International Patent, Copyright, and Competition Law, 1986.

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3

D, Reams Bernard, ed. The Semiconductor chip and the law: A legislative history of the Semiconductor Chip Protection Act of 1984. W.S. Hein, 1986.

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4

United States. Congress. Senate. Committee on the Judiciary. The Semiconductor Chip Protection Act Extension of 1987: Report (to accompany S. 442). U.S. G.P.O., 1987.

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5

Frank, Gotzen, Université catholique de Louvain--Katholieke Universiteit te Leuven., Universitaire Faculteiten Sint-Aloysius (Brussels, Belgium), and Centrum voor Intellectuele Rechten, eds. Chip protection: A new form of intellectual property = La protection des circuits intégrés : un nouveau droit intellectuel. E. Study-Scienta, 1990.

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6

J, Mergens Markus P. On-chip ESD protection in integrated circuits: Device physics, modeling, circuit simulation. Hartung-Gorre, 2001.

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7

United States. Congress. House. Committee on the Judiciary. Protective orders for semiconductor chip products: Report (to accompany H.R. 1951) (including cost estimate of the Congressional Budget Office). U.S. G.P.O., 1987.

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United States. Congress. House. Committee on the Judiciary. Protective orders for semiconductor chip products: Report (to accompany H.R. 1951) (including cost estimate of the Congressional Budget Office). U.S. G.P.O., 1987.

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United States. Congress. House. Committee on the Judiciary. Protective orders for semiconductor chip products: Report (to accompany H.R. 1951) (including cost estimate of the Congressional Budget Office). U.S. G.P.O., 1987.

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10

Semiconductor chip protection. Law & Business, 1986.

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Book chapters on the topic "Semiconductor chip protection"

1

Amernick, Burton A. "Copyrights and Semiconductor Chip Protection." In Patent Law for the Nonlawyer. Springer US, 1991. http://dx.doi.org/10.1007/978-1-4684-7829-7_13.

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2

Torremans, Paul. "30. Computer technology and intellectual property." In Holyoak and Torremans Intellectual Property Law. Oxford University Press, 2019. http://dx.doi.org/10.1093/he/9780198836452.003.0030.

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This chapter discusses five issues: the availability of patent protection for computer hardware and for computer software (computer programs); copyright in computer software; databases and the sui generis right; the Internet; and semiconductor chip protection.
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3

Bently, L., B. Sherman, D. Gangjee, and P. Johnson. "30. Uk unregistered design right." In Intellectual Property Law. Oxford University Press, 2018. http://dx.doi.org/10.1093/he/9780198769958.003.0030.

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This chapter focuses on unregistered design right as a means to protect designs in the UK under Part III of the Copyright, Designs and Patents Act 1988. It begins by considering the subsistence of the UK unregistered design right, with emphasis on the requirement that there be a ‘design’ and exclusions to design protection by the unregistered design right. It then discusses issues of ownership, duration, and infringement as well as the defences available in cases of infringement of unregistered designs. The chapter concludes with a brief explanation of sui generis right involving semiconductor
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Conference papers on the topic "Semiconductor chip protection"

1

"The 1984 Semiconductor chip protection act." In 1985 IEEE International Solid-State Circuits Conference. IEEE, 1985. http://dx.doi.org/10.1109/isscc.1985.1156751.

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2

Szermer, Michal, Marcin Janicki, Piotr Pietrzak, Zbigniew Kulesza, and Andrzej Napieralski. "PTAT sensor for chip overheat protection." In 2010 IEEE/CPMT 26th Semiconductor Thermal Measurement, Modeling & Management Symposium (SEMI-THERM). IEEE, 2010. http://dx.doi.org/10.1109/stherm.2010.5444294.

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3

Wang, Li, Rui Ma, Chen Zhang, Zongyu Dong, Fei Lu, and Albert Wang. "Behavior modeling for whole-chip HV ESD protection circuits." In 2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD). IEEE, 2014. http://dx.doi.org/10.1109/ispsd.2014.6856006.

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4

Lifang Lou and Juin J. Liou. "A novel low-trigger and high-holding voltage SCR without externally- assisted circuitry for area-efficient on-chip ESD protection." In 2007 International Semiconductor Device Research Symposium. IEEE, 2007. http://dx.doi.org/10.1109/isdrs.2007.4422547.

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5

Zhihong, Mai, Ng Tsu Hau, Dawood M. Khalid, Tan Pik Kee, and Jeffrey Lam. "A Silicon Debugging Methodology on Customer Prototype for Wafer Foundries." In ISTFA 2012. ASM International, 2012. http://dx.doi.org/10.31399/asm.cp.istfa2012p0411.

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Abstract IP protection is of major importance for a semiconductor company and only limited information is made available for device debugging for the product outsourced to a foundry. In order to position ourselves better in the ever competitive semiconductor industry, with the consideration of IP protection, we have to provide the customers with the Si debugging capability and device/chip verification services in foundry. This paper explores the Si debugging methodology and technique in a foundry. Two case studies are presented and discussed. The first case illustrates the isolation of the fai
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Monden, Kenji. "Reliability Improvement of Solder Joints Between Ceramic Chip Resistors and Insulated Metal Substrates With Thick Copper Pads." In ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference. ASMEDC, 2005. http://dx.doi.org/10.1115/ipack2005-73176.

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An insulated metal substrate (IMS) is a circuit board comprised of an insulating layer on a metal base plate. The insulating layer is made from epoxy resin incorporating dense inorganic fillers with high thermal conductivity. Because the substrates have high thermal conductivity, they have been used in electrical products that generate intense heat, such as inverters, amplifiers, motor drivers and so on. For using a high power semiconductor, thick copper pads are used on IMSs. In many times, aluminum plates are used for metal base plates in IMSs. The substrates are repeated heating and cooling
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