Relevant bibliographies by topics / Set of instructions

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Set of instructions'

Author: Grafiati
Published: 28 May 2022

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Journal articles on the topic "Set of instructions"

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Forsyth, Katherine L., Bethany R. Lowndes, Erik Prytz, Carl-Oscar Jonson, Matthew D. Sztajnkrycer, Stephanie F. Heller, M. Susan Hallbeck, and Renaldo C. Blocker. "Improving Instructions to Stop the Bleed." Proceedings of the Human Factors and Ergonomics Society Annual Meeting 61, no. 1 (September 2017): 588–92. http://dx.doi.org/10.1177/1541931213601631.

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The Stop The Bleed initiative was developed by the Department of Homeland Security to educate lay providers in bleeding reduction strategies. The current study evaluated: (1)three tourniquet instructions using a simulated tourniquet task and (2)participant confidence levels in tourniquet use and lay provider training. Thirty participants with limited clinical experience applied a tourniquet to a simulated limb using one of three instruction sets. Twelve of these participants (40%) participated in a tourniquet training session and focus group to discuss each instruction set. Participants preferred the most simple and pictoral instruction set, and identified opportunities for improvement in each set. Participant confidence in tourniquet use increased significantly following the task and the focus group. After the focus group, participant confidence in instructing lay providers on proper tourniquet use significantly increased. Adding key steps, contextual pictures, and indicators of success to instructions could support lay providers stop the bleed in life-threatening situations.
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Nishiwaki, Yuji, Toru Takebayashi, Azusa Imai, Masahiko Yamamoto, and Kazuyuki Omae. "Difference by instructional set in stabilometry." Journal of Vestibular Research 10, no. 3 (June 1, 2000): 157–61. http://dx.doi.org/10.3233/ves-2000-10305.

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There is no standard for the awareness of standing posture in stabilometry, yet little research addressing the matter has been carried out. In the present study, we evaluated the influence of different instructional sets during a test on stabilometry. Stabilometry was performed on 349 male subjects. Two different instructions were prepared for the subjects regarding the awareness of their standing posture. These instructions were a) “Please relax when you stand” (R-standing), and b) “Please make an effort to minimize your body sway” (E-standing). Subjects were classified into four groups according to the combination of these instructions they received. For the five body sway parameters, a comparison between R-standing and E-standing was performed, controlling for possible confounders such as age, height, body weight, educational history, alcohol consumption, and smoking status. The sway length in E-standing was larger than that in R-standing, even after the adjustment for possible confounders. Our results indicate that the difference in the instructional set caused a significant measurement bias. Thorough-going unification of instructions for the stabilometry should be recommended when stabilometry is performed in an epidemiological investigation.
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Shen, Zheng, Hu He, Yanjun Zhang, and Yihe Sun. "A Video Specific Instruction Set Architecture for ASIP design." VLSI Design 2007 (November 15, 2007): 1–7. http://dx.doi.org/10.1155/2007/58431.

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This paper describes a novel video specific instruction set architecture for ASIP design. With single instruction multiple data (SIMD) instructions, two destination modes, and video specific instructions, an instruction set architecture is introduced to enhance the performance for video applications. Furthermore, we quantify the improvement on H.263 encoding. In this paper, we evaluate and compare the performance of VS-ISA, other DSPs (digital signal processors), and conventional SIMD media extensions in the context of video coding. Our evaluation results show that VS-ISA improves the processor's performance by approximately 5x on H.263 encoding, and VS-ISA outperforms other architectures by 1.6x to 8.57x in computing IDCT.
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Et.al, Maria Shu Hong Bee Abdullah. "Effective Instructions by Novice Teacher to Improve Teaching Repertoire in School." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (April 10, 2021): 181–84. http://dx.doi.org/10.17762/turcomat.v12i3.654.

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This paper highlights a review on the importance of giving clear instructions and strategies to improve oral instruction by novice teachers as they improve their teaching repertoires in schools. Essentially, this will help teachers to develop a clear oral instruction for good class management. It is an agreeable fact that giving instruction is a skill that takes many years of experience to master and meets the ideal set of practice that teachers set for themselves. Novice teachers face a lot of challenges to master the skill of giving instruction effectively and that is a mark of great quality of a teacher. An effective instructional strategy will deliver the lesson clearly and help learners to understand the focus, engage actively and take ownership of their learning.
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Kim, Dae-Hwan. "Addressing Mode and Bit Extensions to the Thumb-2 Instruction Set Architecture." European Journal of Electrical Engineering and Computer Science 5, no. 2 (March 22, 2021): 13–17. http://dx.doi.org/10.24018/ejece.2021.5.2.308.

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Thumb-2 is the most recent instruction set architecture for ARM processors which are one of the most widely used embedded processors. In this paper, two extensions are proposed to improve the performance of the Thumb-2 instruction set architecture, which are addressing mode extensions and sign/zero extensions combined with data processing instructions. To speed up access to an element of an aggregated data, the proposed approach first introduces three new addressing modes for load and store instructions. They are register-plus-immediate offset addressing mode, negative register offset addressing mode, and post-increment register offset addressing mode. Register-plus-immediate offset addressing mode permits two offsets and negative register offset allows offset to be a negative value of a register content. Post-increment register offset mode automatically modifies the offset address after the memory operation. The second is the sign/zero extension combined with a data processing instruction which allows the result of a data processing operation to be sign/zero extended to accelerate a type conversion. Several least frequently used instructions are reduced to provide the encoding space for the new extensions. Experiments show that the proposed approach improves performance by an average of 8.6% when compared to the Thumb-2 instruction set architecture.
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El Hadj Youssef, Wajih, Ali Abdelli, Fethi Dridi, Rim Brahim, and Mohsen Machhout. "An Efficient Lightweight Cryptographic Instructions Set Extension for IoT Device Security." Security and Communication Networks 2022 (February 5, 2022): 1–17. http://dx.doi.org/10.1155/2022/9709601.

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The Internet of Things is changing all sectors such as manufacturing, agriculture, city infrastructure, and the automotive industry. All these applications ask for secure processors that can be embedded in the IoT devices. Furthermore, these devices are restricted in terms of computing capabilities, memory, and power consumption. A major challenge is how to meet the need for security in such resource-constrained devices. This paper presents a customized version of LEON3, the ReonV RISCV (Reduced Instruction Set Computer-five) processor, dedicated for IoT applications that has strong effective security mechanisms built in at the design stage. Firstly, efficient lightweight cipher designs are elaborated and validated. Then, the proposed cryptographic instructions (PRESENT and PRINCE) are integrated into the default instruction set architecture of the ReonV processor core. The instruction set extensions (ISE) of lightweight cipher modules can be instantiated in software routines exactly as the instructions of the base architecture. A single instruction is needed to implement a full lightweight cryptographic instruction. The customized ReonV RISCV processor is implemented on a Xilinx FPGA platform and is evaluated for Slice LUTs plus FF-pairs, frequency, and throughput. Obtained results show that our proposed concepts not only can achieve good encryption results with high performance and reduced cost but also are secure enough to resist against the most common attacks.
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Lowndes, Bethany, Katherine Law, Amro Abdelrahman, Erik Prytz, Carl-Oscar Jonson, Matthew Sztajnkrycer, Hunter Hawthorne, Walter Franz, Renaldo Blocker, and M. Susan Hallbeck. "Preliminary Investigation of Civilian Clinician Perspectives & Just-in-Time Guidance for Tourniquet Use to “Stop the Bleed”." Military Medicine 184, Supplement_1 (March 1, 2019): 28–36. http://dx.doi.org/10.1093/milmed/usy331.

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Abstract Objective The American College of Surgeons (ACS) encourages clinicians to provide training to laypeople on tourniquet application. It is unclear whether clinicians are confident in their abilities and equipped with adequate knowledge, skills, and resources. This study aimed to determine surgical trainee knowledge and attitudes regarding tourniquet application and compare the effectiveness of instructions. Methods Thirty surgical trainees performed a tourniquet application simulation using a Combat Application Tourniquet and one of the three instructions sets developed by ACS, Department of Homeland Security, and the tourniquet manufacturer. Participants reported tourniquet knowledge, attitudes, and confidence and discussed the instructions. One instruction set was updated and compared to the original set with 20 new trainees. Results Participants with ACS instructions passed the greatest number of steps (p < 0.01) and completed the task significantly faster compared to those with manufacturer instructions (p < 0.01). Participants (80%) reported favorable views toward tourniquets but 30–60% did not align with to ACS tourniquet guidelines. Focus group participants suggested revisions to the ACS instructions. Comparing the original and revised version of these instructions resulted in no significant improvements. Conclusions ACS instructions provide guidance; however, improvements to tourniquet instruction are needed for success in controlling exsanguinating hemorrhage.
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Ryabokin, N. O., and Y. M. Shatkovsky. "The concept of instruction, its communicative tasks." Bulletin of Luhansk Taras Shevchenko National University, no. 4 (335) (2020): 27–37. http://dx.doi.org/10.12958/2227-2844-2020-4(335)-27-37.

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This article deals with the concept of instructions, its types and communication tasks. It was found that the instruction can be characterized as an official business document of technical content and its design at all levels has a high degree of standardization, which ensures the economy in writing and perception of this text. The instructional discourse is investigated and its features are determined: the presence of different speech genres, in particular, the operation manual, the memo, the user manual, the prescription, the service directive; certain speech tactics, namely, informing, shifting responsibility, prompted to action; minimal change in communicative roles. Analyzed four standard types of instructions: 1) instructions for goods (household appliances, food, vehicles, etc.); 2) annotation to medicines; 3) departmental instructions (rules for filling out documents, customer behavior: customs declaration, fire instructions, etc.) 4) job description (rules of behavior for employees in a certain position) and six new types were added: audio / video instructions, interactive instructions, pop-up hints, hypertext knowledge base, hypertext online resource, electronic document. It was also found that the communicative tasks of the instructions are the message of information and the prescription of actions and for the design of the texts of the instructions of the product the optimal system of language means. It was determined that the compositional structure of the text of a typical instruction contains, as a rule, the following sections: introduction, general information, technical data, delivery set, safety requirements, the procedure for installing and preparing the product for work, the procedure for operating the product, product care, maintenance, rules storage and transportation, possible malfunctions and methods of their elimination, warranty obligations.
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Zhang, Huizhen, and Yonghong Chen. "Code mapping algorithm for custom instructions on reconfigurable instruction set processors." International Journal of Electronics 102, no. 1 (September 17, 2014): 18–31. http://dx.doi.org/10.1080/00207217.2014.938308.

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Tan, Vivian Z., Meredith Q. Lee, Daryl L. Wong, Katherin S. Huang, Melissa Y. Chan, Clement C. Yan, and Meredith T. Yeung. "The Chinese (Mandarin) instructions of the 6-minute walk test: A validation study." Hong Kong Physiotherapy Journal 41, no. 01 (January 13, 2021): 45–53. http://dx.doi.org/10.1142/s1013702521500049.

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Background/Objective: To date, a validated Chinese (Mandarin) six-minute walk test (6MWT) translated instruction is not available. Translation of the Chinese 6MWT instruction is done in an ad hoc manner within the Chinese-speaking populations. This study aimed to develop a set of valid and reliable Chinese (Mandarin) instructions of the 6MWT. Methods: Translation was performed from the original English instruction via the recommended “Process of translation and adaptation of instruments” by the World Health Organization to generate the Chinese instructions. The Chinese instructions were tested with 52 healthy adult participants for its validity. Each participant underwent three 6MWTs and a cardiopulmonary exercise test. Randomization allowed participants to undergo the walk test in both the original English and the new Chinese instructions. Face and content validity, intra-rater and inter-rater reliability of the Chinese instructions of the 6MWT were established through the translation process. Criterion validity was established by analyzing the results of the 6MWT and cardiopulmonary exercise test. Results: Intraclass correlation coefficient for inter-rater reliability was excellent ([Formula: see text], 95% confidence [Formula: see text]–1.000). Similarly, the intra-rater reliability across the three raters was high (R1: [Formula: see text], 95% confidence interval [Formula: see text]–1.000; R2: [Formula: see text], 95% [Formula: see text]–1.000; R3: [Formula: see text], 95% [Formula: see text]–1.000). The 6-min walk distances collected from the Chinese and English instructed trials correlated positively with the maximal oxygen consumption ([Formula: see text], [Formula: see text]; [Formula: see text], [Formula: see text]). Conclusion: This is the first study to develop and validate the Chinese (Mandarin) instructions of the 6MWT, and the translation is as reliable and valid as the original English instructions.
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Dissertations / Theses on the topic "Set of instructions"

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Necsulescu, Philip I. "Automatic Generation of Hardware for Custom Instructions." Thèse, Université d'Ottawa / University of Ottawa, 2011. http://hdl.handle.net/10393/20153.

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The Software/Hardware Implementation and Research Architecture (SHIRA) is a C to hardware toolchain developed by the Computer Architecture Research Group (CARG) of the University of Ottawa. The framework and algorithms to generate the hardware from an Intermediate Representation (IR) of the C code is needed. This dissertation presents the conceiving, design, and development of a module that generates the hardware for custom instructions identified by specialized SHIRA components without the need for any user interaction. The module is programmed in Java and takes a Data Flow Graph (DFG) as an IR for input. It then generates VHDL code that targets the Altera FPGAs. It is possible to use separate components for each operation or to set a maximum number for each component which leads to component reuse and reduces chip area use. The performance improvement of the generated code is compared to using only the processor’s standard instruction set.
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Nagpal, Radhika. "Store Buffers : implementing single cycle store instructions in write-through, write-back and set associative caches." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/36678.

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Thesis (B.S. and M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.
Includes bibliographical references (p. 87).
This thesis proposes a new mechanism, called Store Buffers, for implementing single cycle store instructions in a pipelined processor. Single cycle store instructions are difficult to implement because in most cases the tag check must be performed before the data can be written into the data cache. Store buffers allow a store instruction to read the cache tag as it. passes through the pipe while keeping the store instruction data buffered in a backup register until the data cache is free. This strategy guarantees single cycle store execution without increasing the hit access time or degrading the performance of the data cache for simple direct-mapped caches, as well as for more complex set associative and write-back caches. As larger caches are incorporated on-chip, the speed of store instructions becomes an increasingly important part of the overall performance. The first part of the thesis describes the design and implementation of store buffers in write through, write-back, direct-mapped and set associative caches. The second part describes the implementation and simulation of store buffers in a 6-stage pipeline with a direct mapped write-through pipelined cache. The performance of this method is compared to other cache write techniques. Preliminary results show that store buffers perform better than other store strategies under high IO latencies and cache thrashing. With as few as three buffers, they significantly reduce the number of cycles per instruction.
by Radhika Nagpal.
B.S.and M.S.
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Schneider, Nicole. "Parameters: Suites of unique abstract prints generated through the use of a limited set of form-making instructions." Kent State University / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=kent1334282036.

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Zmily, Ahmad Darweesh. "Block-aware instruction set architecture /." May be available electronically:, 2007. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.

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Schoepke, Olaf S. "Dense instruction set computer architecture." Thesis, University of Bath, 1992. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.332540.

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Shi, Xiaomu. "Certification of an Instruction Set Simulator." Phd thesis, Université de Grenoble, 2013. http://tel.archives-ouvertes.fr/tel-00937524.

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Cette thèse expose nos travaux de certification d'une partie d'un programme C/C++ nommé SimSoC (Simulation of System on Chip), qui simule le comportement d'archi- tectures basées sur des processeurs tels que ARM, PowerPC, MIPS ou SH4. Un simulateur de System on Chip peut être utilisé pour developper le logiciel d'un système embarqué spécifique, afin de raccourcir les phases des développement et de test, en particulier quand la vitesse de simulation est réaliste (environ 100 millions d'instructions par seconde par cœur dans le cas de SimSoC). Les réductions de temps et de coût de développement obtenues se traduisent par des cycles de conception interactifs et rapides, en évitant la lourdeur d'un système de développement matériel. SimSoC est un logiciel complexe, comprenant environ 60 000 de C++, intégrant des parties écrites en SystemC et des optimisations non triviales pour atteindre une grande vitesse de simulation. La partie de SimSoC dédiée au processeur ARM, l'un des plus répandus dans le domaine des SoC, transcrit les informations contenues dans un manuel épais de plus de 1000 pages. Les erreurs sont inévitables à ce niveau de complexité, et certaines sont passées au travers des tests intensifs effectués sur la version précédente de SimSoC pour l'ARMv5, qui réussissait tout de même à simuler l'amorçage complet de linux. Un problème critique se pose alors : le simulateur simule-t-il effectivement le matériel réel ? Pour apporter des éléments de réponse positifs à cette question, notre travail vise à prouver la correction d'une partie significative de SimSoC, de sorte à augmenter la confiance de l'utilisateur en ce similateur notamment pour des systèmes critiques. Nous avons concentré nos efforts sur un composant particulièrement sensible de SimSoC : le simulateur du jeu d'instructions de l'ARMv6, faisant partie de la version actuelle de SimSoC. Les approches basées sur une sémantique axiomatique (logique de Hoare par exemple) sont les plus répandues en preuve de programmes impératifs. Cependant, nous avons préféré essayer une approche moins classique mais plus directe, basée sur la sémantique opérationnelle de C : cela était rendu possible en théorie depuis la formalisation en Coq d'une telle sémantique au sein du projet CompCert et mettait à notre disposition toute la puissance de Coq pour gérer la complexitité de la spécification. À notre connaissance, au delà de la certification d'un simulateur, il s'agit de la première expérience de preuve de correction de programmes C à cette échelle basée sur la sémantique opérationnelle. Nous définissons une représentation du jeu d'instruction ARM et de ses modes d'adressage formalisée en Coq, grâce à un générateur automatique prenant en entrée le pseudo-code des instructions issu du manuel de référence ARM. Nous générons égale- ment l'arbre syntaxique abstrait CompCert du code C simulant les mêmes instructions au sein de Simlight, une version allégée de SimSoC. À partir de ces deux représentations Coq, nous pouvons énoncer et démontrer la correction de Simlight, en nous appuyant sur la sémantique opérationnelle définie dans CompCert. Cette méthodologie a été appliquée à au moins une instruction de chaque catégorie du jeu d'instruction de l'ARM. Au passage, nous avons amélioré la technologie disponible en Coq pour effectuer des inversions, une forme de raisonnement utilisée intensivement dans ce type de situation.
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Wright, Stephen. "Formal construction of Instruction Set Architectures." Thesis, University of Bristol, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.508307.

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Bennett, Richard Vincent. "Increasing the efficacy of automated instruction set extension." Thesis, University of Edinburgh, 2011. http://hdl.handle.net/1842/5789.

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The use of Instruction Set Extension (ISE) in customising embedded processors for a specific application has been studied extensively in recent years. The addition of a set of complex arithmetic instructions to a baseline core has proven to be a cost-effective means of meeting design performance requirements. This thesis proposes and evaluates a reconfigurable ISE implementation called “Configurable Flow Accelerators” (CFAs), a number of refinements to an existing Automated ISE (AISE) algorithm called “ISEGEN”, and the effects of source form on AISE. The CFA is demonstrated repeatedly to be a cost-effective design for ISE implementation. A temporal partitioning algorithm called “staggering” is proposed and demonstrated on average to reduce the area of CFA implementation by 37% for only an 8% reduction in acceleration. This thesis then turns to concerns within the ISEGEN AISE algorithm. A methodology for finding a good static heuristic weighting vector for ISEGEN is proposed and demonstrated. Up to 100% of merit is shown to be lost or gained through the choice of vector. ISEGEN early-termination is introduced and shown to improve the runtime of the algorithm by up to 7.26x, and 5.82x on average. An extension to the ISEGEN heuristic to account for pipelining is proposed and evaluated, increasing acceleration by up to an additional 1.5x. An energyaware heuristic is added to ISEGEN, which reduces the energy used by a CFA implementation of a set of ISEs by an average of 1.6x, up to 3.6x. This result directly contradicts the frequently espoused notion that “bigger is better” in ISE. The last stretch of work in this thesis is concerned with source-level transformation: the effect of changing the representation of the application on the quality of the combined hardwaresoftware solution. A methodology for combined exploration of source transformation and ISE is presented, and demonstrated to improve the acceleration of the result by an average of 35% versus ISE alone. Floating point is demonstrated to perform worse than fixed point, for all design concerns and applications studied here, regardless of ISEs employed.
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Lee, Vinson 1978. "Instruction set and simulation framework for transactional memory." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/87369.

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Moreira, João Carlos Peralta. "An instruction set simulator for VLIW DSP architectures." Master's thesis, Universidade de Aveiro, 2015. http://hdl.handle.net/10773/18675.

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Engenharia Eletrónica e Telecomunicações
Dissertação apresentada a Universidade de Aveiro para cumprimento dos requisitos necessários a obtenção do grau de Mestre em Engenharia Eletrónica e Telecomunicações, realizada sob a orientação científica do Professor Doutor Manuel Bernardo Salvador Cunha, Professor Auxiliar do Departamento de Eletrónica, Telecomunicações e Informática da Universidade de Aveiro e Doutor Mohamed Bamakhrama, Hardware Tools Engineer na equipa "Processor and Compiler Tools" no grupo "Imaging and Camera Technologies", Intel Eindhoven, Países Baixos.
Dissertation presented to Universidade de Aveiro with the goal of achieving a Master's Degree in Electronics and Telecommunications, made with the scienti c orientation of Professor Manuel Bernardo Salvador Cunha PhD, Professor at the Department of Electronic, Telecommunications and Informatics from Universidade de Aveiro and Mohamed Bamakhrama, Hardware Tools Engineer at Processor and Compiler Tools Team of Intel's Imaging and Camera Technologies Group, Eindhoven.
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Books on the topic "Set of instructions"

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Konsek, Marian B. ISPY: An instruction set analysis tool. Urbana, Ill. (1304 W. Springfield, Urbana 61801): Dept. of Computer Science, University of Illinois at Urbana-Champaign, 1986.

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Reduced instruction set computer--RISC--architecture. Letchworth, Hertfordshire, England: Research Studies Press, 1987.

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Inmos. The T9000 transputer instruction set manual. [Marlow]: Inmos, 1993.

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Sailer, Philip M. The DLX instruction set architecture handbook. San Francisco, Calif: Morgan Kaufmann Publishers, 1996.

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Reduced instruction set computer architectures for VLSI. Cambridge, Mass: MIT Press, 1985.

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Limarenko, Aleksandr Ivanovich. Ceili, country set & 2 hand dance instruction booklet. 2nd ed. Bayside, NY: Westley School of Irish Dance, 1997.

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Catthoor, Francky. Ultra-low energy domain-specific instruction-set processors. Dordrecht: Springer, 2010.

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Westley, Kevin B. Ceili, country set & 2 hand dance instruction booklet. 2nd ed. Bayside, NY: Westley School of Irish Dance, 1997.

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Bennett, J. P. Automated design of an instruction set for BCPL. Cambridge: University of Cambridge,Computer Laboratory, 1986.

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Catthoor, Francky, Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Angeliki Kritikakou, and Javed Absar. Ultra-Low Energy Domain-Specific Instruction-Set Processors. Dordrecht: Springer Netherlands, 2010. http://dx.doi.org/10.1007/978-90-481-9528-2.

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Book chapters on the topic "Set of instructions"

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Benadjila, Ryad, Olivier Billet, Shay Gueron, and Matt J. B. Robshaw. "The Intel AES Instructions Set and the SHA-3 Candidates." In Advances in Cryptology – ASIACRYPT 2009, 162–78. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-10366-7_10.

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Weik, Martin H. "instruction set." In Computer Science and Communications Dictionary, 797. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_9182.

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Mahout, Vincent. "Instruction Set." In Assembly Language Programming, 63–86. Hoboken, NJ USA: John Wiley & Sons, Inc., 2013. http://dx.doi.org/10.1002/9781118562123.ch5.

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Trio, Jean-Michel. "Instruction Set." In 8086–8088 Architecture and Programming, 143–62. London: Macmillan Education UK, 1985. http://dx.doi.org/10.1007/978-1-349-08186-8_6.

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Leupers, Rainer. "Instruction-Set Extraction." In Retargetable Code Generation for Digital Signal Processors, 45–83. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4757-2570-4_3.

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Weik, Martin H. "instruction-set computer." In Computer Science and Communications Dictionary, 797. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_9183.

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Gilreath, William F., and Phillip A. Laplante. "Instruction Set Completeness." In Computer Architecture: A Minimalist Perspective, 55–71. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0237-1_8.

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Katzen, Sid. "The Instruction Set." In The Essential PIC18® Microcontroller, 95–157. London: Springer London, 2010. http://dx.doi.org/10.1007/978-1-84996-229-2_5.

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Jaulent, Patrick. "68000 Instruction Set." In The 68000 Hardware and Software, 82–149. London: Macmillan Education UK, 1985. http://dx.doi.org/10.1007/978-1-349-07763-2_6.

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Weik, Martin H. "machine instruction set." In Computer Science and Communications Dictionary, 950. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_10813.

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Conference papers on the topic "Set of instructions"

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Yu, Pan, and Tulika Mitra. "Scalable custom instructions identification for instruction-set extensible processors." In the 2004 international conference. New York, New York, USA: ACM Press, 2004. http://dx.doi.org/10.1145/1023833.1023844.

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Lam, Siew-kei, Bharathi Krishnan, and Thambipillai Srikanthan. "Efficient management of custom instructions for run-time reconfigurable instruction set processors." In 2006 IEEE International Conference on Field Programmable Technology. IEEE, 2006. http://dx.doi.org/10.1109/fpt.2006.270323.

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Jaime, Francisco J., Javier Hormigo, Julio Villalba, and Emilio L. Zapata. "New SIMD instructions set for image processing applications enhancement." In 2008 15th IEEE International Conference on Image Processing. IEEE, 2008. http://dx.doi.org/10.1109/icip.2008.4712025.

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Kharchenko, Kostyantyn, Oleksandr Beznosyk, and Valeriy Romanov. "A set of instructions for data flow virtual machine." In 2017 IEEE First Ukraine Conference on Electrical and Computer Engineering (UKRCON). IEEE, 2017. http://dx.doi.org/10.1109/ukrcon.2017.8100385.

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Kaipa, Krishnanand, Carlos Morato, Boxuan Zhao, and Satyandra K. Gupta. "Instruction Generation for Assembly Operations Performed by Humans." In ASME 2012 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. American Society of Mechanical Engineers, 2012. http://dx.doi.org/10.1115/detc2012-71266.

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This paper presents the design of an instruction generation system that can be used to automatically generate instructions for complex assembly operations performed by humans on factory shop floors. Multimodal information—text, graphical annotations, and 3D animations—is used to create easy-to-follow instructions. This thereby reduces learning time and eliminates the possibility of assembly errors. An automated motion planning subsystem computes a collision-free path for each part from its initial posture in a crowded scene onto its final posture in the current subassembly. Visualization of this computed motion results in generation of 3D animations. The system also consists of an automated part identification module that enables the human to identify, and pick, the correct part from a set of similar looking parts. The system’s ability to automatically translate assembly plans into instructions enables a significant reduction in the time taken to generate instructions and update them in response to design changes.
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Dubrovin, Egor N., and Aleksey Yu Popov. "Graph Representation Methods for the Discrete Mathematics Instructions Set Computer." In 2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus). IEEE, 2020. http://dx.doi.org/10.1109/eiconrus49466.2020.9039222.

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Han, Shuo, Lei Zou, and Jeffrey Xu Yu. "Speeding Up Set Intersections in Graph Algorithms using SIMD Instructions." In SIGMOD/PODS '18: International Conference on Management of Data. New York, NY, USA: ACM, 2018. http://dx.doi.org/10.1145/3183713.3196924.

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J Kurisinkel, Litton, and Nancy Chen. "Set to Ordered Text: Generating Discharge Instructions from Medical Billing Codes." In Proceedings of the 2019 Conference on Empirical Methods in Natural Language Processing and the 9th International Joint Conference on Natural Language Processing (EMNLP-IJCNLP). Stroudsburg, PA, USA: Association for Computational Linguistics, 2019. http://dx.doi.org/10.18653/v1/d19-1638.

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Dyomin, Victor V., and Igor G. Polovtsev. "Set of instrumentation and methodological instructions for practical work in optics." In SPIE's 1995 International Symposium on Optical Science, Engineering, and Instrumentation. SPIE, 1995. http://dx.doi.org/10.1117/12.224032.

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Santana Cordeiro, Aline, Tiago Rodrigo Kepe, Diego Gomes Tomé, Eduardo Cunha de Almeida, and Marco Antonio Zanata Alves. "Intrinsics-HMC: An Automatic Trace Generator for Simulations of Processing-In-Memory Instructions." In XVIII Simpósio em Sistemas Computacionais de Alto Desempenho. Sociedade Brasileira de Computação, 2017. http://dx.doi.org/10.5753/wscad.2017.253.

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Processor-in-Memory (PIM) architectures, such as the Hybrid Memory Cube (HMC), are emerging nowadays as a solution for processing large amount of data directly inside the memory. In this area, several researchers are proposing and evaluating new instructions and new PIM architectures. For such evaluations, trace-driven simulators, as the Simulator of Non-Uniform Cache Architectures (SiNUCA), are commonly used in order to model these new proposed systems. Such simulators provide fast prototyping of new architectures, while it requires the researcher to write simulation traces manually when evaluating new Instruction Set Architecture (ISA) proposals, which is an time consuming and error prone task. In this work, we propose a methodology for fast generation of simulation traces focused on HMC architecture, which consists on a high-level Intrinsics-HMC library and a modification inside the trace-generator tool from SiNUCA. Our proposal enables the researchers to write high level code in C/C++ languages using our library, which mimics the behavior of HMC instructions. These codes can be compiled and executed in traditional x86 architectures for verification. After ensure the code is correct and working, the user can use our modified version of SiNUCA-Tracer to translate HMC functions into HMC instructions know by the simulator, providing a convenient solution to generate traces and fast simulations of new PIM architectures. Results using the proposed technique applied on database application kernels show the correct translation and simulation of new HMC instructions using SiNUCA.
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Reports on the topic "Set of instructions"

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Kibler, Amanda, René Pyatt, Jason Greenberg Motamedi, and Ozen Guven. Key Competencies in Linguistically and Culturally Sustaining Mentoring and Instruction for Clinically-based Grow-Your-Own Teacher Education Programs. Oregon State University, May 2021. http://dx.doi.org/10.5399/osu/1147.

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Grow-Your-Own (GYO) Teacher Education programs that aim to diversify and strengthen the teacher workforce must provide high-quality learning experiences that support the success and retention of Black, Indigenous, and people of color (BIPOC) teacher candidates and bilingual teacher candidates. Such work requires a holistic and systematic approach to conceptualizing instruction and mentoring that is both linguistically and culturally sustaining. To guide this work in the Master of Arts in Teaching in Clinically Based Elementary program at Oregon State University’s College of Education, we conducted a review of relevant literature and frameworks related to linguistically responsive and/or sustaining teaching or mentoring practices. We developed a set of ten mentoring competencies for school-based cooperating/clinical teachers and university supervisors. They are grouped into the domains of: Facilitating Linguistically and Culturally Sustaining Instruction, Engaging with Mentees, Recognizing and Interrupting Inequitable Practices and Policies, and Advocating for Equity. We also developed a set of twelve instructional competencies for teacher candidates as well as the university instructors who teach them. The instructional competencies are grouped into the domains of: Engaging in Self-reflection and Taking Action, Learning About Students and Re-visioning Instruction, Creating Community, and Facilitating Language and Literacy Development in Context. We are currently operationalizing these competencies to develop and conduct surveys and focus groups with various GYO stakeholders for the purposes of ongoing program evaluation and improvement, as well as further refinement of these competencies.
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Atuhurra, Julius, and Michelle Kaffenberger. System (In)Coherence: Quantifying the Alignment of Primary Education Curriculum Standards, Examinations, and Instruction in Two East African Countries. Research on Improving Systems of Education (RISE), December 2020. http://dx.doi.org/10.35489/bsg-rise-wp_2020/057.

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Improvements in instructional coherence have been shown to have large impacts on student learning, yet analysis of such coherence, especially in developing countries and at a systems level, is rare. We use an established methodology, the Surveys of Enacted Curriculum (SEC), and apply it to a developing country context to systematically analyze and quantify the content and coherence of the primary curriculum standards, national examinations, and actual teaching delivered in the classroom in Uganda and Tanzania. We find high levels of incoherence across all three instructional components. In Uganda, for example, only four of the fourteen topics in the English curriculum standards appear on the primary leaving exam, and two of the highest-priority topics in the standards are completely omitted from the exams. In Tanzania, only three of fourteen English topics are covered on the exam, and all are assessed at the “memorization” level. Rather than aligning with either the curriculum standards or exams, teachers’ classroom instruction is poorly aligned with both. Teachers tend to cover broad swathes of content and levels of cognitive demand, unrelated to the structure of either the curriculum standards or exams. An exception is Uganda mathematics, for which standards, exams, and teacher instruction are all well aligned. By shedding light on alignment deficits in the two countries, these results draw attention to a policy area that has previously attracted little (if any) attention in many developing countries’ education policy reform efforts. In addition to providing empirical results for Uganda and Tanzania, this study provides a proof-of-concept for the use of the SEC methodology as a diagnostic tool in developing countries, helping education systems identify areas of instructional (in)coherence and informing efforts to improve coherence for learning.
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Koga, R., W. A. Kolasinski, W. A. Hanna, J. D. Vantrease, and G. W. Robnett. SEU (Single Event Upset) Tolerance of McDonnell Douglas' CMOS/SOS High Performance 3 Chip Implementation of MIL-STD-1750A Instruction Set. Fort Belvoir, VA: Defense Technical Information Center, September 1986. http://dx.doi.org/10.21236/ada176234.

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Waterman, Andrew, Yunsup Lee, David A. Patterson, and Krste Asanovi. The RISC-V Instruction Set Manual. Volume 1: User-Level ISA, Version 2.0. Fort Belvoir, VA: Defense Technical Information Center, May 2014. http://dx.doi.org/10.21236/ada605735.

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Rojas Smith, Lucia, Megan L. Clayton, Carol Woodell, and Carol Mansfield. The Role of Patient Navigators in Improving Caregiver Management of Childhood Asthma. RTI Press, April 2017. http://dx.doi.org/10.3768/rtipress.2017.rr.0030.1704.

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Childhood asthma is a significant public health problem in the United States. Barriers to effective asthma management in children include the need for caregivers to identify and manage diverse environmental triggers and promote appropriate use of preventive asthma medications. Although health care providers may introduce asthma treatments and care plans, many providers lack the time and capacity to educate caregivers about asthma in an ongoing, sustained manner. To help address these complexities of asthma care, many providers and caregivers rely on patient navigators (defined as persons who provide patients with a particular set of services and who address barriers to care) (Dohan & Schrag, 2005). Despite growing interest in their value for chronic disease management, researchers and providers know little about how or what benefits patient navigators can provide to caregivers in managing asthma in children. To explore this issue, we conducted a mixed-method evaluation involving focus groups and a survey with caregivers of children with moderate-to-severe asthma who were enrolled in the Merck Childhood Asthma Network Initiative (MCAN). Findings suggest that patient navigators may support children’s asthma management by providing individualized treatment plans and hands-on practice, improving caregivers’ understanding of environmental triggers and their mitigation, and giving clear, accessible instructions for proper medication management. Study results may help to clarify and further develop the role of patient navigators for the effective management of asthma in children.
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Holmer, Bruce K. A Detailed Description of the VLSI-PLM Instruction Set: A WAM Based Processor for Prolog. Fort Belvoir, VA: Defense Technical Information Center, March 1989. http://dx.doi.org/10.21236/ada632225.

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Ramsey, Lori J., and Dianne D. Younkman. Development of the Automated Instructional Management System Data Set of the Officer Longitudinal Research Data Base. Fort Belvoir, VA: Defense Technical Information Center, January 1989. http://dx.doi.org/10.21236/ada207213.

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Piper, Benjamin, Yasmin Sitabkhan, Jessica Mejia, and Kellie Betts. Effectiveness of Teachers’ Guides in the Global South: Scripting, Learning Outcomes, and Classroom Utilization. RTI Press, May 2018. http://dx.doi.org/10.3768/rtipress.2018.op.0053.1805.

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This report presents the results of RTI International Education’s study on teachers' guides across 13 countries and 19 projects. Using quantitative and qualitative methods, we examine how teachers’ guides across the projects differ and find substantial variation in the design and structure of the documents. We develop a scripting index so that the scripting levels of the guides can be compared across projects. The impact results of the programs that use teachers’ guides show significant impacts on learning outcomes, associated with approximately an additional half year of learning, showing that structured teachers’ guides contribute to improved learning outcomes. During observations, we find that teachers make a variety of changes in their classroom instruction from how the guides are written, showing that the utilization of structured teachers’ guides do not create robotic teachers unable to use their own professional skills to teach children. Unfortunately, many changes that teachers make reduce the amount of group work and interactivity that was described in the guides, suggesting that programs should encourage teachers to more heavily utilize the instructional routines designed in the guide. The report includes a set of research-based guidelines that material developers can use to develop teachers’ guides that will support effective instructional practices and help improve learning outcomes. The key takeaway from the report is that structured teachers' guides improve learning outcomes, but that overly scripted teachers' guides are somewhat less effective than simplified teachers' guides that give specific guidance to the teacher but are not written word for word for each lesson in the guide.
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McDonald, John F. F-RISC- A 1.0 GOPS Fast Reduced Instruction Set Computer for Super Workstation and Teraops Parallel Processor Applications. Fort Belvoir, VA: Defense Technical Information Center, April 2001. http://dx.doi.org/10.21236/ada394207.

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Hwa, Yue-Yi, Michelle Kaffenberger, and Jason Silberstein. Aligning Levels of Instruction with Goals and the Needs of Students (ALIGNS): Varied Approaches, Common Principles. Research on Improving Systems of Education (RISE), November 2020. http://dx.doi.org/10.35489/bsg-rise-ri_2020/022.

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In this Insight Note, we present a set of principles shared by varied approaches that have all succeeded in improving foundational learning in developing countries. These approaches were not explicitly designed with this list of principles in mind; rather, the principles emerged through analysis and synthesis of successful approaches. We call such efforts ALIGNS approaches, which stands for Aligning Levels of Instruction with Goals and the Needs of Students. ALIGNS approaches take many forms, ranging from large-scale policy and curricular reforms to in-school or after-school remedial programmes. In this note, we describe the principles that ALIGNS approaches have in common (Section I); review interdisciplinary evidence on why aligning instruction with children’s learning levels improves learning (Section II); present three cases from across the spectrum of approaches and illustrate how each embodies the ALIGNS principles (Section III); and provide a longer (though not exhaustive) table of programmes that illustrates the range of possible approaches to implementing ALIGNS principles and describes the design features across which they vary (Table 1).
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