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Forsyth, Katherine L., Bethany R. Lowndes, Erik Prytz, Carl-Oscar Jonson, Matthew D. Sztajnkrycer, Stephanie F. Heller, M. Susan Hallbeck, and Renaldo C. Blocker. "Improving Instructions to Stop the Bleed." Proceedings of the Human Factors and Ergonomics Society Annual Meeting 61, no. 1 (September 2017): 588–92. http://dx.doi.org/10.1177/1541931213601631.
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The Stop The Bleed initiative was developed by the Department of Homeland Security to educate lay providers in bleeding reduction strategies. The current study evaluated: (1)three tourniquet instructions using a simulated tourniquet task and (2)participant confidence levels in tourniquet use and lay provider training. Thirty participants with limited clinical experience applied a tourniquet to a simulated limb using one of three instruction sets. Twelve of these participants (40%) participated in a tourniquet training session and focus group to discuss each instruction set. Participants preferred the most simple and pictoral instruction set, and identified opportunities for improvement in each set. Participant confidence in tourniquet use increased significantly following the task and the focus group. After the focus group, participant confidence in instructing lay providers on proper tourniquet use significantly increased. Adding key steps, contextual pictures, and indicators of success to instructions could support lay providers stop the bleed in life-threatening situations.
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Nishiwaki, Yuji, Toru Takebayashi, Azusa Imai, Masahiko Yamamoto, and Kazuyuki Omae. "Difference by instructional set in stabilometry." Journal of Vestibular Research 10, no. 3 (June 1, 2000): 157–61. http://dx.doi.org/10.3233/ves-2000-10305.
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There is no standard for the awareness of standing posture in stabilometry, yet little research addressing the matter has been carried out. In the present study, we evaluated the influence of different instructional sets during a test on stabilometry. Stabilometry was performed on 349 male subjects. Two different instructions were prepared for the subjects regarding the awareness of their standing posture. These instructions were a) “Please relax when you stand” (R-standing), and b) “Please make an effort to minimize your body sway” (E-standing). Subjects were classified into four groups according to the combination of these instructions they received. For the five body sway parameters, a comparison between R-standing and E-standing was performed, controlling for possible confounders such as age, height, body weight, educational history, alcohol consumption, and smoking status. The sway length in E-standing was larger than that in R-standing, even after the adjustment for possible confounders. Our results indicate that the difference in the instructional set caused a significant measurement bias. Thorough-going unification of instructions for the stabilometry should be recommended when stabilometry is performed in an epidemiological investigation.
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Shen, Zheng, Hu He, Yanjun Zhang, and Yihe Sun. "A Video Specific Instruction Set Architecture for ASIP design." VLSI Design 2007 (November 15, 2007): 1–7. http://dx.doi.org/10.1155/2007/58431.
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This paper describes a novel video specific instruction set architecture for ASIP design. With single instruction multiple data (SIMD) instructions, two destination modes, and video specific instructions, an instruction set architecture is introduced to enhance the performance for video applications. Furthermore, we quantify the improvement on H.263 encoding. In this paper, we evaluate and compare the performance of VS-ISA, other DSPs (digital signal processors), and conventional SIMD media extensions in the context of video coding. Our evaluation results show that VS-ISA improves the processor's performance by approximately 5x on H.263 encoding, and VS-ISA outperforms other architectures by 1.6x to 8.57x in computing IDCT.
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Et.al, Maria Shu Hong Bee Abdullah. "Effective Instructions by Novice Teacher to Improve Teaching Repertoire in School." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (April 10, 2021): 181–84. http://dx.doi.org/10.17762/turcomat.v12i3.654.
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This paper highlights a review on the importance of giving clear instructions and strategies to improve oral instruction by novice teachers as they improve their teaching repertoires in schools. Essentially, this will help teachers to develop a clear oral instruction for good class management. It is an agreeable fact that giving instruction is a skill that takes many years of experience to master and meets the ideal set of practice that teachers set for themselves. Novice teachers face a lot of challenges to master the skill of giving instruction effectively and that is a mark of great quality of a teacher. An effective instructional strategy will deliver the lesson clearly and help learners to understand the focus, engage actively and take ownership of their learning.
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Kim, Dae-Hwan. "Addressing Mode and Bit Extensions to the Thumb-2 Instruction Set Architecture." European Journal of Electrical Engineering and Computer Science 5, no. 2 (March 22, 2021): 13–17. http://dx.doi.org/10.24018/ejece.2021.5.2.308.
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Thumb-2 is the most recent instruction set architecture for ARM processors which are one of the most widely used embedded processors. In this paper, two extensions are proposed to improve the performance of the Thumb-2 instruction set architecture, which are addressing mode extensions and sign/zero extensions combined with data processing instructions. To speed up access to an element of an aggregated data, the proposed approach first introduces three new addressing modes for load and store instructions. They are register-plus-immediate offset addressing mode, negative register offset addressing mode, and post-increment register offset addressing mode. Register-plus-immediate offset addressing mode permits two offsets and negative register offset allows offset to be a negative value of a register content. Post-increment register offset mode automatically modifies the offset address after the memory operation. The second is the sign/zero extension combined with a data processing instruction which allows the result of a data processing operation to be sign/zero extended to accelerate a type conversion. Several least frequently used instructions are reduced to provide the encoding space for the new extensions. Experiments show that the proposed approach improves performance by an average of 8.6% when compared to the Thumb-2 instruction set architecture.
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El Hadj Youssef, Wajih, Ali Abdelli, Fethi Dridi, Rim Brahim, and Mohsen Machhout. "An Efficient Lightweight Cryptographic Instructions Set Extension for IoT Device Security." Security and Communication Networks 2022 (February 5, 2022): 1–17. http://dx.doi.org/10.1155/2022/9709601.
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The Internet of Things is changing all sectors such as manufacturing, agriculture, city infrastructure, and the automotive industry. All these applications ask for secure processors that can be embedded in the IoT devices. Furthermore, these devices are restricted in terms of computing capabilities, memory, and power consumption. A major challenge is how to meet the need for security in such resource-constrained devices. This paper presents a customized version of LEON3, the ReonV RISCV (Reduced Instruction Set Computer-five) processor, dedicated for IoT applications that has strong effective security mechanisms built in at the design stage. Firstly, efficient lightweight cipher designs are elaborated and validated. Then, the proposed cryptographic instructions (PRESENT and PRINCE) are integrated into the default instruction set architecture of the ReonV processor core. The instruction set extensions (ISE) of lightweight cipher modules can be instantiated in software routines exactly as the instructions of the base architecture. A single instruction is needed to implement a full lightweight cryptographic instruction. The customized ReonV RISCV processor is implemented on a Xilinx FPGA platform and is evaluated for Slice LUTs plus FF-pairs, frequency, and throughput. Obtained results show that our proposed concepts not only can achieve good encryption results with high performance and reduced cost but also are secure enough to resist against the most common attacks.
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Lowndes, Bethany, Katherine Law, Amro Abdelrahman, Erik Prytz, Carl-Oscar Jonson, Matthew Sztajnkrycer, Hunter Hawthorne, Walter Franz, Renaldo Blocker, and M. Susan Hallbeck. "Preliminary Investigation of Civilian Clinician Perspectives & Just-in-Time Guidance for Tourniquet Use to “Stop the Bleed”." Military Medicine 184, Supplement_1 (March 1, 2019): 28–36. http://dx.doi.org/10.1093/milmed/usy331.
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Abstract Objective The American College of Surgeons (ACS) encourages clinicians to provide training to laypeople on tourniquet application. It is unclear whether clinicians are confident in their abilities and equipped with adequate knowledge, skills, and resources. This study aimed to determine surgical trainee knowledge and attitudes regarding tourniquet application and compare the effectiveness of instructions. Methods Thirty surgical trainees performed a tourniquet application simulation using a Combat Application Tourniquet and one of the three instructions sets developed by ACS, Department of Homeland Security, and the tourniquet manufacturer. Participants reported tourniquet knowledge, attitudes, and confidence and discussed the instructions. One instruction set was updated and compared to the original set with 20 new trainees. Results Participants with ACS instructions passed the greatest number of steps (p < 0.01) and completed the task significantly faster compared to those with manufacturer instructions (p < 0.01). Participants (80%) reported favorable views toward tourniquets but 30–60% did not align with to ACS tourniquet guidelines. Focus group participants suggested revisions to the ACS instructions. Comparing the original and revised version of these instructions resulted in no significant improvements. Conclusions ACS instructions provide guidance; however, improvements to tourniquet instruction are needed for success in controlling exsanguinating hemorrhage.
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Ryabokin, N. O., and Y. M. Shatkovsky. "The concept of instruction, its communicative tasks." Bulletin of Luhansk Taras Shevchenko National University, no. 4 (335) (2020): 27–37. http://dx.doi.org/10.12958/2227-2844-2020-4(335)-27-37.
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This article deals with the concept of instructions, its types and communication tasks. It was found that the instruction can be characterized as an official business document of technical content and its design at all levels has a high degree of standardization, which ensures the economy in writing and perception of this text. The instructional discourse is investigated and its features are determined: the presence of different speech genres, in particular, the operation manual, the memo, the user manual, the prescription, the service directive; certain speech tactics, namely, informing, shifting responsibility, prompted to action; minimal change in communicative roles. Analyzed four standard types of instructions: 1) instructions for goods (household appliances, food, vehicles, etc.); 2) annotation to medicines; 3) departmental instructions (rules for filling out documents, customer behavior: customs declaration, fire instructions, etc.) 4) job description (rules of behavior for employees in a certain position) and six new types were added: audio / video instructions, interactive instructions, pop-up hints, hypertext knowledge base, hypertext online resource, electronic document. It was also found that the communicative tasks of the instructions are the message of information and the prescription of actions and for the design of the texts of the instructions of the product the optimal system of language means. It was determined that the compositional structure of the text of a typical instruction contains, as a rule, the following sections: introduction, general information, technical data, delivery set, safety requirements, the procedure for installing and preparing the product for work, the procedure for operating the product, product care, maintenance, rules storage and transportation, possible malfunctions and methods of their elimination, warranty obligations.
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Zhang, Huizhen, and Yonghong Chen. "Code mapping algorithm for custom instructions on reconfigurable instruction set processors." International Journal of Electronics 102, no. 1 (September 17, 2014): 18–31. http://dx.doi.org/10.1080/00207217.2014.938308.
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Tan, Vivian Z., Meredith Q. Lee, Daryl L. Wong, Katherin S. Huang, Melissa Y. Chan, Clement C. Yan, and Meredith T. Yeung. "The Chinese (Mandarin) instructions of the 6-minute walk test: A validation study." Hong Kong Physiotherapy Journal 41, no. 01 (January 13, 2021): 45–53. http://dx.doi.org/10.1142/s1013702521500049.
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Background/Objective: To date, a validated Chinese (Mandarin) six-minute walk test (6MWT) translated instruction is not available. Translation of the Chinese 6MWT instruction is done in an ad hoc manner within the Chinese-speaking populations. This study aimed to develop a set of valid and reliable Chinese (Mandarin) instructions of the 6MWT. Methods: Translation was performed from the original English instruction via the recommended “Process of translation and adaptation of instruments” by the World Health Organization to generate the Chinese instructions. The Chinese instructions were tested with 52 healthy adult participants for its validity. Each participant underwent three 6MWTs and a cardiopulmonary exercise test. Randomization allowed participants to undergo the walk test in both the original English and the new Chinese instructions. Face and content validity, intra-rater and inter-rater reliability of the Chinese instructions of the 6MWT were established through the translation process. Criterion validity was established by analyzing the results of the 6MWT and cardiopulmonary exercise test. Results: Intraclass correlation coefficient for inter-rater reliability was excellent ([Formula: see text], 95% confidence [Formula: see text]–1.000). Similarly, the intra-rater reliability across the three raters was high (R1: [Formula: see text], 95% confidence interval [Formula: see text]–1.000; R2: [Formula: see text], 95% [Formula: see text]–1.000; R3: [Formula: see text], 95% [Formula: see text]–1.000). The 6-min walk distances collected from the Chinese and English instructed trials correlated positively with the maximal oxygen consumption ([Formula: see text], [Formula: see text]; [Formula: see text], [Formula: see text]). Conclusion: This is the first study to develop and validate the Chinese (Mandarin) instructions of the 6MWT, and the translation is as reliable and valid as the original English instructions.
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Wu, Ning, Tao Jiang, Lei Zhang, Fang Zhou, and Fen Ge. "A Reconfigurable Convolutional Neural Network-Accelerated Coprocessor Based on RISC-V Instruction Set." Electronics 9, no. 6 (June 16, 2020): 1005. http://dx.doi.org/10.3390/electronics9061005.
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As a typical artificial intelligence algorithm, the convolutional neural network (CNN) is widely used in the Internet of Things (IoT) system. In order to improve the computing ability of an IoT CPU, this paper designs a reconfigurable CNN-accelerated coprocessor based on the RISC-V instruction set. The interconnection structure of the acceleration chain designed by the predecessors is optimized, and the accelerator is connected to the RISC-V CPU core in the form of a coprocessor. The corresponding instruction of the coprocessor is designed and the instruction compiling environment is established. Through the inline assembly in the C language, the coprocessor instructions are called, coprocessor acceleration library functions are established, and common algorithms in the IoT system are implemented on the coprocessor. Finally, resource consumption evaluation and performance analysis of the coprocessor are completed on a Xilinx FPGA. The evaluation results show that the reconfigurable CNN-accelerated coprocessor only consumes 8534 LUTS, accounting for 47.6% of the total SoC system. The number of instruction cycles required to implement functions such as convolution and pooling based on the designed coprocessor instructions is better than using the standard instruction set, and the acceleration ratio of convolution is 6.27 times that of the standard instruction set.
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Kuriyama, Naoko, Kimihiko Yamagishi, and Takashi Kusumi. "Effects of Instructions and Representation on Mathematical Problem-Solving." Psychological Reports 93, no. 2 (October 2003): 603–9. http://dx.doi.org/10.2466/pr0.2003.93.2.603.
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We investigated whether specific instructions have different representations for target problems, and hence whether task representations mostly affect the direction of typical errors in permutation problem-solving. We hypothesized that different instructions produce specific representations of a permutation problem in an identical description. The 39 participants were randomly assigned to the three groups: the equation instruction group, the subgoal instruction group, and the control group. Results confirmed our prediction that the treatment groups solved the problem more correcdy than the control group. More importantly, a subgoal instruction (a set of steps in a meaningful task) decreased the typical mistakes. Educational implications are discussed.
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Wong, Tingh Wee, Bryan Ng, and Chee Onn Wong. "Encoding Custom Instruction Generation as Satisfiability Problem." Advanced Materials Research 403-408 (November 2011): 502–10. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.502.
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The emergence of Application-specific Instruction-set Processor (ASIP) has encouraged the proliferation of tool-chains used to streamline its design flow. One of the features much sought-after in these tool-chains is notably the automatic generation of Application-specific Functional Units (AFUs) which, in turn, involves the custom instruction generation as a crucial step. Whereupon an additional step is assumed to pipeline the patterns identified for fulfilling the I/O constraint, custom instructions that correspond to maximal valid subgraphs are mostly beneficial to the speedup gain. Therefore, we present in this paper a propositional satisfiability approach to efficiently identify the custom instructions which contain a large number of valid nodes. Our approach is different substantially from the previous works where it uses an edge classification method to reduce the search space for convexity checking. The experiment results show that our method can, in a matter of few seconds, identify a set of custom instructions that speed up the application to a few times faster.
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Liu, Hui, Jian Fei Ouyang, and Yuan Liu. "Four Instructions CPU." Applied Mechanics and Materials 198-199 (September 2012): 1115–20. http://dx.doi.org/10.4028/www.scientific.net/amm.198-199.1115.
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This paper introduces using digital electronic technology of knowledge and logic devices designed a four instruction set of the microprocessor, this processor enable the operation of eight-bit binary number. Complete hardware and instruction set of microprocessor design, the microprocessor can add two unsigned eight-bit binary number, subtraction, multiplication and division functions.
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Bourguignon, Nicolas J., Senne Braem, Egbert Hartstra, Jan De Houwer, and Marcel Brass. "Encoding of Novel Verbal Instructions for Prospective Action in the Lateral Prefrontal Cortex: Evidence from Univariate and Multivariate Functional Magnetic Resonance Imaging Analysis." Journal of Cognitive Neuroscience 30, no. 8 (August 2018): 1170–84. http://dx.doi.org/10.1162/jocn_a_01270.
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Verbal instructions are central to humans' capacity to learn new behaviors with minimal training, but the neurocognitive mechanisms involved in verbally instructed behaviors remain puzzling. Recent functional magnetic resonance imaging (fMRI) evidence suggests that the right middle frontal gyrus and dorsal premotor cortex (rMFG-dPMC) supports the translation of symbolic stimulus–response mappings into sensorimotor representations. Here, we set out to (1) replicate this finding, (2) investigate whether this region's involvement is specific to novel (vs. trained) instructions, and (3) study whether rMFG-dPMC also shows differences in its (voxel) pattern response indicative of general cognitive processes of instruction implementation. Participants were shown instructions, which they either had to perform later or merely memorize. Orthogonal to this manipulation, the instructions were either entirely novel or had been trained before the fMRI session. Results replicate higher rMFG-dPMC activation levels during instruction implementation versus memorization and show how this difference is restricted to novel, but not trained, instruction presentations. Pattern similarity analyses at the voxel level further reveal more consistent neural pattern responses in rMFG-dPMC during the implementation of novel versus trained instructions. In fact, this more consistent neural pattern response seemed to be specific to the first instruction presentation and disappeared after the instruction had been applied once. These results further support a role of rMFG-dPMC in the implementation of novel task instructions and highlight potentially important differences in studying this region's gross activation levels versus (the consistency of) its response patterns.
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Hamed, Ahmed, M. Watheq El-Kharashi, Ashraf Salem, and Mona Safar. "Two-Layer Bus-Independent Instruction Set Architecture for Securing Long Protocol Data Units in Automotive Open System Architecture-Based Automotive Electronic Control Units." Electronics 11, no. 6 (March 18, 2022): 952. http://dx.doi.org/10.3390/electronics11060952.
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In this paper, we propose a bus-independent hardware (HW)-based approach to secure long protocol data units (PDUs) in Automotive Open System Architecture (AUTOSAR)-based automotive electronic control units (ECUs). Our approach is based on extending previous works that implemented two AUTOSAR communication (COM) application-specific instruction set processors (ASIPs). COM ASIP V1 introduced two instructions to handle the transmission and reception of PDUs no larger than 8 bytes and signals no larger than 32 bits individually through send signal and receive signal instructions. COM ASIP V2 introduced two extra instructions to handle long signals and PDUs of arbitrary lengths. We extended the instruction set architecture (ISA) of our previous ASIPs by introducing six new instructions, in COM ASIP V3, to hash PDUs that contain these signals to authenticate transmission and reception of such PDUs. The experimental results show that COM ASIP V3 can handle (i.e., transmit, receive, calculate hash, or verify hash) a 64-byte controller area network flexible data-rate (CAN FD) frame in 1.575 μs and a 254-byte FlexRay frame in 6.301 μs. These measurements indicate that the throughput of our new COM ASIP is much higher, 42× to 75×, than the throughput required by these communication buses.
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Farley, Sally D., and Mark F. Stasson. "Relative Influences of Affect and Cognition on Behavior: Are Feelings or Beliefs More Related to Blood Donation Intentions?" Experimental Psychology 50, no. 1 (January 2003): 55–62. http://dx.doi.org/10.1027//1618-3169.50.1.55.
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This study tested the relative predictive power of affect and cognition on global attitude and behavioral intention within the tripartite model of attitude structure. Participants (N = 264) completed questionnaires that included an item regarding blood donation experience, five semantic differential items, four behavioral intention items, and one global attitude item. Participants were randomly assigned to either an affective or cognitive instruction set for the semantic differential items. As predicted, semantic differentials were more highly correlated with both global attitude and behavioral intention when completed under the affective instructions than under the cognitive instructions. In addition, donors’ and non-donors’ attitudes on the semantic differential scales were distinguished from one another only when they were elicited under the affective instruction set. Results provide support for the tripartite model of attitude structure. Future research should examine the relative importance of affect and cognition in less emotion-laden domains.
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Sugimura, Takeshi, and Noriko Sato. "Factors Affecting Assumptions about Mutual Exclusivity and Novel Name-Nameless Category." Perceptual and Motor Skills 82, no. 3_suppl (June 1996): 1147–53. http://dx.doi.org/10.2466/pms.1996.82.3c.1147.
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48 five-yr.-old girls and boys were given the first set for a task which had three familiar and one unfamiliar drawings and were asked to select one drawing for the novel word. Then they were given the second set for the task which had four different familiar and four types of unfamiliar drawings and were asked to select the drawings for the novel word under the labeling or the inclusion instructions. These selections were repeated four times successively. Based on the selection patterns in the second set, children whose selecting was consistent with the assumption of mutual exclusivity and those whose selecting was consistent with the novel name-nameless assumption were identified. Children were more sensitive to the former assumption for the labeling than for the inclusion instructions. Children who were sensitive to the latter assumption extended the novel word mainly to the shape category for the labeling instruction, although they could extend the novel word to the unnamed and broader category for the inclusion instruction. The findings suggest that children show flexibility in applying the two assumptions.
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Klaczynski, Paul A., and Wejdan Felmban. "Effects of Thinking Dispositions, General Ability, Numeracy, and Instructional Set on Judgments and Decision-Making." Psychological Reports 123, no. 2 (December 14, 2018): 341–70. http://dx.doi.org/10.1177/0033294118806473.
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To explore hypotheses based on Stanovich’s proposal that analytic processing comprises a reflective-level, an algorithmic level, and specific mindware, 342 participants completed measures of thinking dispositions, general ability (GA), numeracy, and probabilistic and nonprobabilistic reasoning. In a control condition, numeracy predicted probabilistic reasoning at high levels of both thinking dispositions and GA, and GA predicted nonprobabilistic reasoning at high levels of thinking dispositions. In a logic instruction condition, numeracy predicted probabilistic reasoning when GA was high, and GA affected nonprobabilistic reasoning directly. Thinking dispositions moderated neither relationship. Instead, instructions facilitated reasoning for low thinking disposition/high-ability participants, suggesting that logic instructions cued low thinking disposition individuals to engage in higher order reflective processing. The evidence is consistent with the proposals that reflective processes are essential to the allocation of algorithmic resources, and algorithmic resources are necessary for effective mindware implementation.
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Pargellis, A. N. "Digital Life Behavior in the Amoeba World." Artificial Life 7, no. 1 (January 2001): 63–75. http://dx.doi.org/10.1162/106454601300328025.
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Amoeba is a computer model designed to facilitate the study of the origin and evolution of digital life. Specifically, an initially disordered system, consisting of random sequences of machine instructions, self-organizes into an ordered system containing self-replicating programs. The current version of Amoeba broadens the original system's capability by using a basis set of 32 machine instructions that is computationally universal. In addition, Amoeba uses a set of 64 address labels, each of which is randomly assigned to a machine instruction each time a sequence is randomly created. This eliminates the constraint that occurs when the complements of predefined codons are used for addressing. A more open-ended system results because programs can now form subroutines that are arranged in an arbitrary manner.
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Kreifeldt, John C., and Kodali V. N. Rao. "Fuzzy Sets: An application to Warnings and Instructions." Proceedings of the Human Factors Society Annual Meeting 30, no. 12 (September 1986): 1192–96. http://dx.doi.org/10.1177/154193128603001212.
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Instructions and Warnings while often requiring the reader to make fairly precise sensory judgements or physical actions, yet convey these requests in the qualitative terms of common discourse, such as the phrase “fairly precise” in this sentence, or the instruction “press firmly”. The consequences of “not following instructions” can range from less than satisfactory product performance (e.g., “poor shine”) to broken equipment or even serious personal injury. The writer of instructions and warnings must know (1) how such qualitative or “fuzzy” terms will be quantitatively translated into action and (2) how to design terms (e.g. “press firmly but not hard”) to produce the desired user action. This paper describes initial work undertaken to apply fuzzy set theory to these problems and comparison of empirical definitions of a membership function.
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Ivannikov, A. D. "Emulators as a Tool for Control Digital System Software Debugging." INFORMACIONNYE TEHNOLOGII 27, no. 7 (July 8, 2021): 339–49. http://dx.doi.org/10.17587/it.27.339-349.
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The simulation of control digital systems at the architecture level, that is, emulation of the instruction set, memory cells and internal programmable registers, as well as the interrupt system and direct memory access is considered. Emulators are used for debugging embedded digital system software and in the development of new custom processors. Requirements for emulators are formalized. It is shown that the main requirements are adequate simulation of digital systems at the architecture level, the presence of a set of convenient debugging modes, as well as high efficiency of emulators, that is, the minimum possible average number of instrumental computer instructions required to simulate one instruction of the target digital system. A classification of the debugging capabilities of emulators and possible ways of implementing debugging modes is given. The composition of the emulators is described. A graphical model of the structure of the emulator is proposed. The simulation process for each instruction is presented as a sequence of execution of smaller operations. If different instructions include the same operations, these operations can be performed by the same software modules. These modules can be included in all the corresponding blocks of the emulator that simulate the execution of instructions, or the emulator can include only one copy of each operational program module, and the module can be accessed while simulating the corresponding instruction. Determination of the structure of the emulator is formalized as an extreme task, the objective function of which is the minimum average time for simulating the execution of one instruction of the target digital system, and the limitation is the maximum allowable memory size of the instrumental computer occupied by the emulator. A practical method for determining the structure of the emulator is proposed.
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Park, Seonghwan, Dongwook Kang, Jeonghwan Kang, and Donghyun Kwon. "Bratter: An Instruction Set Extension for Forward Control-Flow Integrity in RISC-V." Sensors 22, no. 4 (February 11, 2022): 1392. http://dx.doi.org/10.3390/s22041392.
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In recent decades, there has been an increasing number of studies on control flow integrity (CFI), particularly those implementing hardware-assisted CFI solutions that utilize a special instruction set extension. More recently, ARM and Intel, which are prominent processor architectures, also announced instruction set extensions for CFI called branch target identification (BTI) and control-flow enhancement technology (CET), respectively. However, according to our preliminary analysis, they do not support various CFI solutions in an efficient and scalable manner. In this study, we propose Bratter, a new instruction set extension for forward CFI solutions on RISC-V. At the center of Bratter, there are Branch Tag Registers and dedicated instructions for these registers. We implemented well-known CFI solutions (i.e., branch regulation and function signature check) using Bratter to evaluate its performance. Our experimental results show that, by using Bratter, even when these two solutions work together, they impose only 1.20% and 5.99% overhead for code size and execution time, respectively.
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Guironnet de Massas, P., P. Amblard, and F. Pétrot. "On SPARC LEON-2 ISA Extensions Experiments for MPEG Encoding Acceleration." VLSI Design 2007 (July 10, 2007): 1–10. http://dx.doi.org/10.1155/2007/28686.
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This paper presents the necessary steps to modify the implementation of the SPARCV8 architecture to enhance it with multimedia-oriented instructions. The purpose is improving video compression performance without designing dedicated coprocessors. We investigate the complexity of modifying a standard processor instruction set and show that, although not trivial, this is feasible in a few weeks. We implemented 12 new instructions and use some of them to optimize the computation of a demanding step of the MPEG encoding. The result is a performance increase of 67% in the execution of a part of this algorithm, allowing us to expect a 30% speedup in the execution of an MPEG video compression. The area increase of the integer unit is about 18% and the clock frequency is not significantly modified in an LEON-2 implementing 6 among 12 of the new instructions.
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Garber, Malcolm, and Stephen J. Newton. "The Influence of Instructions on the Ratings of Problem Behaviors." Behavioral Disorders 15, no. 1 (November 1989): 41–49. http://dx.doi.org/10.1177/019874298901500102.
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In this replication of Wickman's classic study which compared a group of teacher ratings about problem behaviors with those of mental health professionals, two sets of instructions were administered to both groups. One set of instructions focused attention on problem behaviors that would impact on current classroom management. The other set of instructions spotlighted behaviors that would be detrimental to future personality development. There were 189 teachers in one group while 187 were randomly assigned to a second group with different instructions. Both groups of 89 mental health workers were also given the same instructions as each of the teacher groups. A statistically significant difference between teachers and mental health workers emerged (p < .001). Main effects for instructions were not statistically different. However, a statistically significant interaction (p < .01) emerged. Though teachers seemed to maintain their ratings of behavior problems despite the instructions, mental health workers regarded different sets of problem behaviors to be more important depending on which set of instructions they were provided. Teachers were more consistent in rating acting-out types of behavior problems. This study lends support to the idea that teacher ratings of problem behaviors may be more relevant than previous Wickman studies have indicated.
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Fujita, Rafael A., Nilson R. S. Silva, Bruno L. S. Bedo, Paulo R. P. Santiago, Paulo R. V. Gentil, and Matheus M. Gomes. "Mind–Muscle Connection: Limited Effect of Verbal Instructions on Muscle Activity in a Seated Row Exercise." Perceptual and Motor Skills 127, no. 5 (May 25, 2020): 925–38. http://dx.doi.org/10.1177/0031512520926369.
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Verbal instruction increases electromyographic (EMG) activity in the first three repetitions of an exercise, but its effect on an entire exercise set until failure is unknown. Once there are changes in motor unit recruitment due to fatigue, the effect of verbal instructions can change during different intervals of a set. This study analyzed whether verbal instruction emphasized the contraction of back muscles (i.e., myoelectric activity) during initial, intermediate, and final exercise repetitions performed until failure. Twenty participants with little or no experience in strength training performed a seated row exercise with and without verbal instruction. Surface electrodes were fixed over the latissimus dorsi, teres major, biceps brachii, and posterior deltoid (PD) muscles. Myoelectric activity was computed by mean amplitude and by the median frequency. We analyzed data with repeated measures multivariate analysis of variance and found that, with verbal instruction, there was increased EMG mean amplitude in the latissimus dorsi (15.21%, p = .030) and reduced EMG mean amplitude in the PD (14.39%, p = .018) on initial repetitions. Other muscle EMG amplitudes did not change. On intermediate repetitions, there was reduced signal amplitude only in the PD (15.03%, p = .022). The verbal instruction did not interfere with signal amplitude on final repetitions nor in the median frequency throughout the series. Verbal instruction seems to have little effect on increasing myoelectric activity of these targeted muscles in an entire set of a resistance training.
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Wang, Guang, and Yin Sheng Gao. "An Implementation of Configurable SIMD Core on FPGA." Applied Mechanics and Materials 336-338 (July 2013): 1925–29. http://dx.doi.org/10.4028/www.scientific.net/amm.336-338.1925.
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In order to meet the computing speed required by 4G wireless communications, and to provide the different data processing widths required by different algorithms, an SIMD (Single Instruction Multiple Data) core has been designed. The ISA (Instruction Set Architecture) and main components of the SIMD core are discussed focus on how the SIMD core can be configured. Finally, the simulation result of the multiplication of two 8*8 matrices is presented to show the execution of instructions in the proposed SIMD core, and the result verifies the correctness of the SIMD core design.
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TRAHAN, JERRY L., and HOSANGADI BHANUKUMAR. "PARALLEL RANDOM ACCESS MACHINES WITHOUT BOOLEAN OPERATIONS." Parallel Processing Letters 04, no. 01n02 (June 1994): 117–24. http://dx.doi.org/10.1142/s0129626494000132.
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The class of problems solved within given time and processor bounds on a Parallel Random Access Machine (PRAM) varies with the instruction set. Previous research has classified the contributions of various instructions, such as multiplication, shifts, and string manipulation operations, to the PRAM. This paper examines the significant contribution of Boolean operations, which play essential roles in many PRAM algorithms and in simulations by the PRAM of other models of computation.
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Morrow, Daniel G., Von O. Leirer, Jill M. Andrassy, Elizabeth Decker Tanke, and Elizabeth A. L. Stine-Morrow. "SPECIAL SECTION: Medication Instruction Design: Younger and Older Adult Schemas for Taking Medication." Human Factors: The Journal of the Human Factors and Ergonomics Society 38, no. 4 (December 1996): 556–73. http://dx.doi.org/10.1518/001872096778827305.
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We examined whether older and younger adults share a schema for taking medication and whether instructions are better recalled when they are organized to match this schema. Experiment 1 examined age differences in schema organization. Participants sorted medication items (e.g., purpose, dose, possible side effects) according to similarity and then ordered the items to create a preferred instruction set. Cluster analysis of the sort and order data showed that younger and older adults share a schema for taking medication. Secondary regression analyses found that verbal ability (i.e., vocabulary scores) predicted individual differences in schema organization. In Experiment 2 participants recalled instructions that were either compatible with this schema in terms of grouping and order of items or were presented in nonpreferred orders. Younger participants remembered more information than did older participants, but both age groups better remembered and preferred the more schema-compatible instructions. Secondary analyses showed that recall was also positively related to verbal ability. Along with our earlier research, this study suggests that older and younger adults possess a schema for taking medication and that instructions that are compatible with this schema provide an environmental support that improves memory for medication information.
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Artzi, Yoav, and Luke Zettlemoyer. "Weakly Supervised Learning of Semantic Parsers for Mapping Instructions to Actions." Transactions of the Association for Computational Linguistics 1 (December 2013): 49–62. http://dx.doi.org/10.1162/tacl_a_00209.
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The context in which language is used provides a strong signal for learning to recover its meaning. In this paper, we show it can be used within a grounded CCG semantic parsing approach that learns a joint model of meaning and context for interpreting and executing natural language instructions, using various types of weak supervision. The joint nature provides crucial benefits by allowing situated cues, such as the set of visible objects, to directly influence learning. It also enables algorithms that learn while executing instructions, for example by trying to replicate human actions. Experiments on a benchmark navigational dataset demonstrate strong performance under differing forms of supervision, including correctly executing 60% more instruction sets relative to the previous state of the art.
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Shahbazi, Karim, and Mohammad Eshghi. "Design of a Specific Instructions Set Processor for AES Algorithm." International Journal of Computer Applications 93, no. 4 (May 16, 2014): 36–40. http://dx.doi.org/10.5120/16205-5496.
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Inoue, Hiroshi, Moriyoshi Ohara, and Kenjiro Taura. "Faster set intersection with SIMD instructions by reducing branch mispredictions." Proceedings of the VLDB Endowment 8, no. 3 (November 2014): 293–304. http://dx.doi.org/10.14778/2735508.2735518.
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Naqvi, Syed Rameez, Ali Roman, Tallha Akram, Majed M. Alhaisoni, Muhammad Naeem, Sajjad Ali Haider, Omer Chughtai, and Muhammad Awais. "An Optimization Framework for Codes Classification and Performance Evaluation of RISC Microprocessors." Symmetry 11, no. 7 (July 19, 2019): 938. http://dx.doi.org/10.3390/sym11070938.
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Pipelines, in Reduced Instruction Set Computer (RISC) microprocessors, are expected to provide increased throughputs in most cases. However, there are a few instructions, and therefore entire assembly language codes, that execute faster and hazard-free without pipelines. It is usual for the compilers to generate codes from high level description that are more suitable for the underlying hardware to maintain symmetry with respect to performance; this, however, is not always guaranteed. Therefore, instead of trying to optimize the description to suit the processor design, we try to determine the more suitable processor variant for the given code during compile time, and dynamically reconfigure the system accordingly. In doing so, however, we first need to classify each code according to its suitability to a different processor variant. The latter, in turn, gives us confidence in performance symmetry against various types of codes—this is the primary contribution of the proposed work. We first develop mathematical performance models of three conventional microprocessor designs, and propose a symmetry-improving nonlinear optimization method to achieve code-to-design mapping. Our analysis is based on four different architectures and 324,000 different assembly language codes, each with between 10 and 1000 instructions with different percentages of commonly seen instruction types. Our results suggest that in the sub-micron era, where execution time of each instruction is merely in a few nanoseconds, codes accumulating as low as 5% (or above) hazard causing instructions execute more swiftly on processors without pipelines.
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Muhammad Masadeh, Walid, and Abdullah Tayel Al Hassan. "Combating money laundering and terrorism financing instructions in Jordan." Banks and Bank Systems 13, no. 3 (September 5, 2018): 81–94. http://dx.doi.org/10.21511/bbs.13(3).2018.08.
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This study aims to identify the extent of the response of operating banks in Jordan to the anti-money laundering and terrorism financing instructions set by the Central Bank of Jordan, and to enumerate the effectiveness of these sets of laws, the echelon of cooperation with the relevant government agencies and the impact of contiguous political and security conditions on the anti-money laundering and financing of terrorism. To attain the objectives of this study and to test its hypotheses, a descriptive analytical method was followed based on related data of the Central Bank instructions and the engaged procedures by operating banks to combat money laundering and financing of terrorism. Therefore, a questionnaire was designed and distributed to the managers of anti-money laundering departments in operating banks in Jordan. The study shows various outcomes, the most important is the high responding of operating banks in Jordan to the instructions of the anti-money laundering and terrorism financing issued by the Central Bank of Jordan. The existence of practical application of money laundering and terrorism financing instructions fights against money laundering and terrorism financing in banks in Jordan at a soaring level. In addition to the functional cooperation by the competent governmental authorities in the fight against money laundering and terrorism financing, this study introduces a set of recommendations to reinforce the cooperation level for every related party to achieve a high level of cooperation in the field of the anti-money laundering and financing terrorism.
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Novkovic, Teodora, Zeljko Lukac, Petar Jovanovic, and Ivan Kastelan. "Graphic Library Optimization for MIPS Architecture." Elektronika ir Elektrotechnika 26, no. 2 (April 25, 2020): 69–76. http://dx.doi.org/10.5755/j01.eie.26.2.25871.
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The aim of this paper and research was to analyse the efficiency of the compiler-generated code for the graphics library and to present results obtained by optimization for the MIPS (Million Instructions Per Second) architecture. Libpng is the official Portable Network Graphics reference library for use in applications that read, create, and manipulate PNG (Portable Network Graphics) raster image files. Given the data structure in the PNG files, as well as the capabilities of the MIPS instruction set, it was expected that significant improvements could be made. Graphic library libpng is optimized by using MIPS instruction set extension and tested on MIPS Malta 74K platform. Test results show, that by using MIPS optimization test, execution times are substantially improved. Our libpng optimization have achieved performance increase of 10 %–78 % depending on optimized routine.
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Qiao, Wan, and Dake Liu. "A scalable ASIP for BP Polar decoding with multiple code lengths." MATEC Web of Conferences 232 (2018): 01046. http://dx.doi.org/10.1051/matecconf/201823201046.
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In this paper, we propose a flexible scalable BP Polar decoding application-specific instruction set processor (PASIP) that supports multiple code lengths (64 to 4096) and any code rates. High throughputs and sufficient programmability are achieved by the single-instruction-multiple-data (SIMD) based architecture and specially designed Polar decoding acceleration instructions. The synthesis result using 65 nm CMOS technology shows that the total area of PASIP is 2.71 mm2. PASIP provides the maximum throughput of 1563 Mbps (for N = 1024) at the work frequency of 400MHz. The comparison with state-of-art Polar decoders reveals PASIP’s high area efficiency.
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M S, Harish M. S., and Jayadevappa D. "Design & Simulation Of 64-Bit Hybrid Processor Instruction Set Using Verilog." International Journal of Engineering & Technology 7, no. 4.36 (December 9, 2018): 373. http://dx.doi.org/10.14419/ijet.v7i4.36.23809.
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As a part of my ongoing research on implementation of multi core hybrid processor on FPGA, I have developed data flow designs for most popularly used 20 processor instructions. I have made digital design, wrote code in Verilog HDL and simulated all the 20 instructions using Xilinx ISE 14.5. The data flow designs, symbolic representation and simulation results are explained in detail in this technical paper. This is partial implementation of Hybrid Processor & the other sub modules implementation on Xilinx FPGA will be published in my subsequent technical paper.
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M S, Harish M. S., and Jayadevappa D. "Design & Simulation Of 64-Bit Hybrid Processor Instruction Set Using Verilog." International Journal of Engineering & Technology 7, no. 4.36 (December 9, 2018): 373. http://dx.doi.org/10.14419/ijet.v7i4.36.23810.
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As a part of my ongoing research on implementation of multi core hybrid processor on FPGA, I have developed data flow designs for most popularly used 20 processor instructions. I have made digital design, wrote code in Verilog HDL and simulated all the 20 instructions using Xilinx ISE 14.5. The data flow designs, symbolic representation and simulation results are explained in detail in this technical paper. This is partial implementation of Hybrid Processor & the other sub modules implementation on Xilinx FPGA will be published in my subsequent technical paper.
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Hevener, W., F. Barnes, and D. A. Munafo. "0629 Feasibility of Observed but Physically Unaided Continuous Positive Airway Pressure Set Ups." Sleep 43, Supplement_1 (April 2020): A240. http://dx.doi.org/10.1093/sleep/zsaa056.625.
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Abstract Introduction We sought to determine if an observed but physically unaided CPAP set up, utilizing only a detailed set of CPAP instructions without direct involvement of a Respiratory Therapist, could yield similar Medicare compliance rates when compared to the conventional method of hands-on instruction. Methods This was a single center, prospective trial. All patients were CPAP naïve. A total of 393 patients completed the physically unaided set ups utilizing a starter kit designed by Resmed (Airsense 10 Autoset, instructions and 3 mask options, P10,N20,F20). Patients were asked to set themselves up under observation with only verbal assistance provided if requested. No patient required conversion to conventional set up. 5287 completed the conventional set ups. We compared the success of observed but unaided CPAP set ups to the success rate for conventional CPAP set ups performed with physical assistance. The primary success endpoint was Medicare compliance within 90 days. Results The two groups were not significantly different with regard to gender, age, baseline AHI, and initial mask selection. The Medicare compliance of the unaided set ups was not significantly different from the conventional set ups (75% vs. 77% respectively, p=NS). Similarly, adherence at ten days (65% vs. 69%, p=NS) and thirty days (65% vs. 68%, p=NS) was no different between the two groups and the percentage of mask re-fits required at ten and thirty days was similarly no different. Conclusion We conclude that for the CPAP equipment used, observed but physically unaided CPAP set ups can yield similar Medicare compliance rates when compared to physically aided CPAP set ups. Further, we speculate that because these techniques yielded similar success rates the principal factor determining ultimate success is patient follow up and support once therapy is initiated. Support None.
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DOROJEVETS, MIKHAIL. "ARCHITECTURE AND DESIGN OF AN 8-BIT FLUX-1 SUPERCONDUCTOR RSFQ MICROPROCESSOR." International Journal of High Speed Electronics and Systems 12, no. 02 (June 2002): 521–29. http://dx.doi.org/10.1142/s0129156402001435.
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The first single-chip superconductor FLUX-1 microprocessor has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using 4 kA/cm2, 1.75-μm Nb/AlOx/Nb Josephson junction technology as a result of the collaboration between SUNY Stony Brook and TRW, Inc. A FLUX-1 chip represents an 8-bit deeply pipelined microprocessor prototype with a target clock frequency of 17-20 GHz. A new parallel partitioned architecture has been developed in order to tolerate interconnect delays and fill long FLUX-1 processor pipelines with useful instructions. The processor includes the 16 × 32-bit pipelined instruction memory, 8 integer arithmetic-logic units interleaved with 8 registers, the branch unit, and I/O ports for 5-GHz chip-to-chip communication over Nb microstrip lines on a chip carrier. The FLUX-1 instruction set consists of ~25 arithmetic, logical, and control instructions. A FLUX-1 microprocessor chip contains 65,759 Josephson junctions on a 10.6 mm × 13.2 mm die with flip-chip packaging. First FLUX-1 chips fabricated in August 2001 are currently under testing at TRW, Inc.
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Zhang, Song, Yi Zhang, Lian Fa Bai, and Wen Jiang Li. "Design on Embedded Processor with Configurable Divider." Applied Mechanics and Materials 336-338 (July 2013): 1504–9. http://dx.doi.org/10.4028/www.scientific.net/amm.336-338.1504.
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By analyzing Cortex-M3 Instruction Set and AHB Bus protocol, a Cortex-M3 Instruction Set compatible 32-bit RISC embedded microprocessor with built-in an optimized 5+2-stage pipeline was realized in this paper. The performance of the 32-bit RISC processor is optimized by deepening pipeline and optimizing functional modules compared with Cortex-M3. According to division instructions, a configurable hardware divider in different realization ways was realized for different applications. The design of the system architecture was completed using Verilog hardware description language (Verilog HDL) and Top-down methodology. The logic function was corrected by VCS simulation FPGA verification. Design Compiler synthesis result shows that, the maximal dominant frequency of the RISC embedded microprocessor could be up to 95MHz with the 0.18um CMOS process of SMIC, and is improved by 31.94% compared with STM32 Cortex-M3 (72MHz).
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Benhadjyoussef, Noura, Wajih Elhadjyoussef, Mohsen Machhout, Rached Tourki, and Kholdoun Torki. "Enhancing a 32-Bit Processor Core with Efficient Cryptographic Instructions." Journal of Circuits, Systems and Computers 24, no. 10 (October 25, 2015): 1550158. http://dx.doi.org/10.1142/s0218126615501583.
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Embedded processor is often expected to achieve a higher security with good performance and economical use of resource. However, the choice regarding the best solution for how cryptographic algorithms are incorporated in processor core is one of the most challenging assignments a designer has to face. This paper presents an inexpensive instruction set extensions (ISE) of efficient cryptographic algorithms on 32-bit processors assuring various types of instruction (public/private key cryptography, random number generator (RNG) and secure hash function (SHF)). These extensions provide hardware instructions that implement a full algorithm in a single instruction. Our enhanced LEON2 SPARC V8 core with cryptographic ISE is implemented using Xilinx XC5VFX70t FPGA device and an ASIC CMOS 40-nm technology. The total area of the resulting chip is about 1.93 mm2 and the estimated power consumption of the chip is 16.3 mW at 10 MHz. Hardware cost and power consumption evaluation are provided for different clock frequencies and the achieved results show that our circuit is able to be arranged in many security constrained devices.
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Wallace, Andrew. "Placement, Gender, Pedagogy: Virgil's Fourth Georgic in Print*." Renaissance Quarterly 56, no. 2 (2003): 377–407. http://dx.doi.org/10.2307/1261851.
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AbstractThe article examines the narrative conclusion of the Georgics, in which the nymph Cyrene distills from Proteus' tale of Orpheus and Eurydice a set of practical instructions for her son to carry out. It argues that the tendency to minimize or ignore Cyrene's crucial role at the end of the poem is inseparable from Virgil's attempt to inspect the mechanics of instruction. Renaissance editors, commentators, and illustrators grappled uneasily with Virgil's attempt to make gender and placement integral components of Cyrene's pedagogy, and with the notion that successful instruction would culminate in a scene in which the teacher might still need to be present.
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Koch, Dirk, Christian Beckhoff, and Jim Torresen. "Efficient Interfacing of Partially Reconfigurable Instruction Set Extensions for Softcore CPUs on FPGAs." Journal of Integrated Circuits and Systems 6, no. 1 (December 27, 2011): 35–42. http://dx.doi.org/10.29292/jics.v6i1.336.
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Swapping just small fractions of the configuration of an FPGA can be very beneficial in many applications. This is in particular useful for reconfiguring the instruction set of embedded soft core processors. In this paper, we will sketch that present design techniques include a substantial overhead for integrating reconfigurable parts into the rest of the system. This overhead can cost more logic resources than the actual module implementations. For removing this overhead, we propose a novel technique to constrain the communication resources between the static system and the partial regions.We will demonstrate for a reconfigurable soft core processor that instructions can be integrated into the system without causing any additional logic overhead for the communication. In addition, we reveal how such systems can be easily implemented with our tool ReCoBus-Builder. Furthermore, we will analyze the overhead in terms of reconfiguration time and present a metric helping to take design decisions.
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Ghose, Tandra, and Mary A. Peterson. "Task set and instructions influence the weight of figural priors: A psychophysical study with extremal edges and familiar configuration." Attention, Perception, & Psychophysics 83, no. 6 (April 20, 2021): 2709–27. http://dx.doi.org/10.3758/s13414-021-02282-5.
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AbstractIn figure–ground organization, the figure is defined as a region that is both “shaped” and “nearer.” Here we test whether changes in task set and instructions can alter the outcome of the cross-border competition between figural priors that underlies figure assignment. Extremal edge (EE), a relative distance prior, has been established as a strong figural prior when the task is to report “which side is nearer?” In three experiments using bipartite stimuli, EEs competed and cooperated with familiar configuration, a shape prior for figure assignment in a “which side is shaped?” task.” Experiment 1 showed small but significant effects of familiar configuration for displays sketching upright familiar objects, although “shaped-side” responses were predominantly determined by EEs. In Experiment 2, instructions regarding the possibility of perceiving familiar shapes were added. Now, although EE remained the dominant prior, the figure was perceived on the familiar-configuration side of the border on a significantly larger percentage of trials across all display types. In Experiment 3, both task set (nearer/shaped) and the presence versus absence of instructions emphasizing that familiar objects might be present were manipulated within subjects. With familiarity thus “primed,” effects of task set emerged when EE and familiar configuration favored opposite sides as figure. Thus, changing instructions can modulate the weighing of figural priors for shape versus distance in figure assignment in a manner that interacts with task set. Moreover, we show that the influence of familiar parts emerges in participants without medial temporal lobe/ perirhinal cortex brain damage when instructions emphasize that familiar objects might be present.
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Pan, Lihang, Guoqing Tu, Shubo Liu, Zhaohui Cai, and Xingxing Xiong. "A Lightweight AES Coprocessor Based on RISC-V Custom Instructions." Security and Communication Networks 2021 (December 30, 2021): 1–13. http://dx.doi.org/10.1155/2021/9355123.
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With the increasing popularity of the Internet of Things (IoT), the issue of its information security has drawn more and more attention. To overcome the resource constraint barrier for secure and reliable data transmission on the widely used IoT devices such as wireless sensor network (WSN) nodes, many researcher studies consider hardware acceleration of traditional cryptographic algorithms as one of the effective methods. Meanwhile, as one of the current research topics in the reduced instruction set computer (RISC), RISC-V provides a solid foundation for implementing domain-specific architecture (DSA). To this end, we propose an extended instruction scheme for the advanced encryption standard (AES) based on RISC-V custom instructions and present a coprocessor designed on the open-source core Hummingbird E203. The AES coprocessor uses direct memory access channels to achieve parallel data access and processing, which provides flexibility in memory space allocation and improves the efficiency of cryptographic components. Applications with embedded AES custom instructions running on an experimental prototype of the field-programmable gate array (FPGA) platform demonstrated a 25.3% to 37.9% improvement in running time over previous similar works when processing no less than 80 bytes of data. In addition, the application-specific integrated circuit (ASIC) experiments show that in most cases, the coprocessor only consumes up to 20% more power than the necessary AES operations.
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Palenciano, Ana F., Carlos González-García, Juan E. Arco, and María Ruz. "Transient and Sustained Control Mechanisms Supporting Novel Instructed Behavior." Cerebral Cortex 29, no. 9 (October 25, 2018): 3948–60. http://dx.doi.org/10.1093/cercor/bhy273.
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Abstract The success of humans in novel environments is partially supported by our ability to implement new task procedures via instructions. This complex skill has been associated with the activity of control-related brain areas. Current models link fronto-parietal and cingulo-opercular networks with transient and sustained modes of cognitive control, based on observations during repetitive task settings or rest. The current study extends this dual model to novel instructed tasks. We employed a mixed design and an instruction-following task to extract phasic and tonic brain signals associated with the encoding and implementation of novel verbal rules. We also performed a representation similarity analysis to capture consistency in task-set encoding within trial epochs. Our findings show that both networks are involved while following novel instructions: transiently, during the implementation of the instruction, and in a sustained fashion, across novel trials blocks. Moreover, the multivariate results showed that task representations in the cingulo-opercular network were more stable than in the fronto-parietal one. Our data extend the dual model of cognitive control to novel demanding situations, highlighting the high flexibility of control-related regions in adopting different temporal profiles.
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Duijn, Tina van, Simon Thomas, and Rich SW Masters. "Chipping in on the role of conscious processing during children's motor learning by analogy." International Journal of Sports Science & Coaching 14, no. 3 (April 2, 2019): 383–92. http://dx.doi.org/10.1177/1747954119841162.
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The capacity for storing and manipulating information (a function of working memory) is not fully developed until adulthood, so children are not always able to process explicit instructions when learning a new skill. A teaching method that may solve this problem is analogy learning, which compares the to-be-learned skill with a well-known concept by way of a single metaphorical instruction. In adults, analogy learning has been shown to lead to lower load on working memory by reducing the need for conscious processing; however, the effects are unclear in children. If analogy instructions work similarly in children, the propensity to consciously control movements may affect how well children learn by analogy. It is in the interest of coaches and teachers to determine whether analogy instructions can be used to reduce conscious processing in children, and whether propensity for conscious control of movements (movement specific reinvestment) predicts benefits from analogy learning. Thirteen-year-old golf novices (n = 44) were pre-tested and post-tested after practicing a golf-chipping task using explicit rules. One week later, an analogy for learning the golf chip was introduced, and an identical set of post-tests was repeated. Propensity for conscious control/reinvestment predicted improvement in accuracy after the analogy was introduced. Children's motor learning by analogy may be affected by their propensity for conscious control of movements, which suggests that coaches should adapt instructions to individual differences between learners.
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Roth, Wolff-Michael. "The gap between instruction (plan) and situated action: A challenge to semiotics?" Semiotica 2018, no. 221 (March 26, 2018): 1–27. http://dx.doi.org/10.1515/sem-2016-0084.
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AbstractIn this study, I describe a potential challenge to semiotics, which exists in the fact that no interpretation of an instruction (text) can get us closer to doing what the instructional text describes. I provide a praxeological description of a situation in a software development firm where the instructions (rules) for a particular type of meeting are inscribed on the whiteboard in front of which the meetings were held. I discuss the gap between instructions and the behavior they describe and the moral order of praxis that is not inscribed in instructions.
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Noguchi, Takafumi, Hidekazu Kajiwara, Kazunori Chida, and Sakae Inamori. "Development of a Programming Teaching-Aid Robot with Intuitive Motion Instruction Set." Journal of Robotics and Mechatronics 29, no. 6 (December 20, 2017): 980–91. http://dx.doi.org/10.20965/jrm.2017.p0980.
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A robot that consists of a compact disc (CD) and an embedded microcomputer has been developed as a robotics learning tool for elementary and junior high school students. The students can program the robot to draw a variety of shapes by placing a pen in the center hole of the CD. As the movement track of the robot can be recorded, the students can preserve their devised program execution results. In addition, intuitive instructions can be used to control the robot. This allows to input the program by operating several push-button switches. The program instructions can be viewed on the robot’s 8 LEDs-display interface. This robot is a unique teaching tool, which can be used to learn the mechanism of the robot composed of sensors, actuators, and a computer, without using a personal computer.