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Relevant bibliographies by topics / Trench-gate

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Journal articles
Dissertations / Theses
Book chapters
Conference papers

Academic literature on the topic 'Trench-gate'

Author: Grafiati

Published: 3 June 2025

Last updated: 31 July 2025

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Journal articles on the topic "Trench-gate"

1

Kojima, Takahito, Shinsuke Harada, Keiko Ariyoshi, et al. "Reliability Improvement and Optimization of Trench Orientation of 4H-SiC Trench-Gate Oxide." Materials Science Forum 778-780 (February 2014): 537–40. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.537.

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Reliability of gate oxide for trench-gate MOSFET was improved by deposited oxide film with uniform thickness and high-temperature annealing after trench etching. Optimum wafer orientation and trench direction for the trench gate was investigated, and the gate oxide on (11-20) plane of carbon face exhibited the longest lifetime. Influences by the roughness of sidewall and the radius of trench corner are discussed.

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Seok, Ogyun, Hyoung Woo Kim, In Ho Kang, Min-Woo Ha, and Wook Bahng. "Effects of junction profiles in bottom protection p-well on electrical characteristics of 1.2 kV SiC trench-gate MOSFETs." European Physical Journal Applied Physics 88, no. 3 (2019): 30103. http://dx.doi.org/10.1051/epjap/2020190269.

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Effects of junction profiles in bottom protection p-well (BPW) on electrical characteristics of 1.2 kV SiC trench-gate MOSFETs were investigated using simulation methods. Breakdown mechanisms of BPW in the device were also elucidated by energy-band diagram and electric-field distribution across trench-gate. Monte Carlo Al-implantation simulation on the trench structure for BPW formation was carried out with variations in peak depth (DBPW), concentration (NBPW), and thickness of SiO2 spacer (Tspacer) on trench sidewall. The SiC trench-gate MOSFETs with deep DBPW, high NBPW, and thin Tspacer are

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3

Wang, Bo. "Analysis of junction capacitance characteristics of trench gate IGBT." E3S Web of Conferences 237 (2021): 02024. http://dx.doi.org/10.1051/e3sconf/202123702024.

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Trench gate field termination IGBT represents the latest structure of insulated gate bipolar transistor (IGBT). Because the internal current of IGBT includes the charging and discharging current of gate capacitance and internal junction capacitance during switching transient, the influence of junction capacitance should be considered. The conductive channel of trench gate structure is different from that of planar gate structure, and the analysis method of junction capacitance using planar gate structure will inevitably bring some deviation. Based on the characteristics of trench gate structur

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Jones, Ben, Alex Croot, Jacob Mitchell, et al. "Demonstrating SiC <i>In Situ</i> Rounded Trench Processing Technologies for Future Power Trench MOSFET Applications." Solid State Phenomena 359 (August 22, 2024): 163–70. http://dx.doi.org/10.4028/p-us98lu.

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Effective control of device geometry is key to mitigating high localized electric fields in next-generation SiC power devices. Advanced trench processing allows for highly tunable trench-gate architectures in trench MOSFETs. By utilizing a two-step inductively coupled plasma reactive ion etch (ICP-RIE) process, a high degree of trench base corner rounding can be achieved, irrespective of trench opening corner geometry prior to post etch treatments. Sentaurus TCAD device modelling highlights the importance of effective electric field dispersion at the gate oxide using rounded trench corners, wh

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Wang, Bo. "Analysis of base characteristics of trench gate field termination IGBT." E3S Web of Conferences 237 (2021): 02023. http://dx.doi.org/10.1051/e3sconf/202123702023.

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Trench gate structure represents the latest structure of Insulated Gate Bipolar Transistor(IGBT). Because there are great differences in model analysis coordinate system and carrier transport between trench gate structure and planar gate structure, the modeling method using planar gate structure will inevitably have great deviation. Based on the characteristics of trench gate structure and model analysis coordinate system, the base region is divided into PNP and PIN by considering the two-dimensional effect of carriers. According to whether the trench of PIN part can be covered by depletion la

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Cho, Doohyung, and Kwangsoo Kim. "Trench Power MOSFET using Separate Gate Technique for Reducing Gate Charge." Journal of IKEEE 16, no. 4 (2012): 283–89. http://dx.doi.org/10.7471/ikeee.2012.16.4.283.

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Huang, Lin Hua, Yong Liu, Xin Peng, et al. "Design of Al<sub>2</sub>O<sub>3</sub>/LaAlO<sub>3</sub>/SiO<sub>2</sub> Gate Stack on Various Channel Planes for High-Performance 4H-SiC Trench Power MOSFETs." Solid State Phenomena 358 (August 21, 2024): 79–87. http://dx.doi.org/10.4028/p-9mknrr.

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An Al2O3/LaAlO3/SiO2 gate stack is designed and implemented on various trench-gate channel planes for high-performance trench power MOSFETs. The designed high-k gate stack achieves a significant enhancement in the gate blocking capability (~1.73X) and maintains a low interface state density (Dit), in comparison to the SiO2 gate. Moreover, owing to the implementation of the high-k gate stack, the high-k trench gate MOSFETs conduct a drain current of approximately 1.3 times larger than that of the SiO2 trench gate MOSFETs on all 24 channel planes at the same overdrive voltage (Vgs-Vth) of 10 V.

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Miyahara, Shinichiro, H. Watanabe, T. Yamamoto, et al. "Effect of Damage Removal Treatment after Trench Etching on the Reliability of Trench MOSFET." Materials Science Forum 740-742 (January 2013): 789–92. http://dx.doi.org/10.4028/www.scientific.net/msf.740-742.789.

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Guaranteeing the reliability of gate oxides is one of the most important topics to realize regarding the SiC power MOSFET. In the case of trench MOSFET, since the gate oxides are formed on the trench sidewall, the damage and roughness on the trench sidewall can affect the lifetime of the gate oxides. Generally speaking, damage removal treatment is processed after trench dry etching in most cases. In Si processes, sacrificial oxidation, H2 anneal and CDE (Chemical Dry Etching) are adopted commonly. In the case of SiC processes, sacrificial oxidation, H2 anneal, and SiH4/Ar anneal have been repo

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Kagawa, Yasuhiro, Rina Tanaka, Nobuo Fujiwara, et al. "Introduction of Depletion Stopper for Reduction of JFET Resistance for 4H-SiC Trench MOSFET." Materials Science Forum 821-823 (June 2015): 761–64. http://dx.doi.org/10.4028/www.scientific.net/msf.821-823.761.

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This paper investigates thereduction of parasitic resistance (JFET resistance) betweenthe p-well and the grounded p-type gate-oxide protection layer (BPW)of a trench-gate SiC-MOSFET. Forming a deeptrench is a way to reducethe JFET resistance, but this consequently leads to high electric field at thebottom oxide. In order to improve the trade-off between the specific on-resistance (Ron,sp) and the maximum bottom oxide electric field (Eox), wenewly developed a trench-gate SiC-MOSFET with an n-type region, named DepletionStopper (DS), formed under the entire p-welllayer. As aresult of fabrication

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Manosukritkul, Phasapon, Amonrat Kerdpardist, Montree Saenlamool, Ekalak Chaowicharat, Amporn Poyai, and Wisut Titiroongruang. "An Improvement of the Breakdown Voltage Characteristics of NPT-TIGBT by Using a P-Buried Layer." Advanced Materials Research 717 (July 2013): 158–63. http://dx.doi.org/10.4028/www.scientific.net/amr.717.158.

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In this paper, we introduced a P-buried (Pb) layer under trench gate which relieved the electric field crowding in the Non Punch Through Trench gate Insulated Gate Bipolar Transistor (NPT-TIGBT) structure. The Pblayer, with carrier concentration of 5x1016cm-3, was created underneath the trench gate within the n-drift layer. In this way, the concentration of electric field at the trench bottom corner decreased. As a result, the breakdown voltage characteristics of NPT-TIGBT improved. The structures were proposed and verified by T-CAD Sentuarus simulation. From the simulation results, the breakd

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Dissertations / Theses on the topic "Trench-gate"

1

Bowles, Marc W. "The trench and gate groundwater remediation system." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape15/PQDD_0024/MQ31330.pdf.

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Tamil, Selva Kruphalan. "Investigation of Trench Gate IGBTs in MMC based VSC for HVDC." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-240408.

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The following is a thesis project involving investigation of applicability of trench type IGBTs in present and future VSC based HVDC convertors. The work involves three major sections – theoretical loss evaluation of adoption of Trench technology (both IGBT and BIGT) for HVDC Light® applications, testing the Trench IGBT prototype with existing gate units and finalizing with a hypothesis and a practical solution for unexplained turn-on phenomenon observed during testing. The thesis concludes with the suggestion of suitable driving mechanisms (e.g. reduced number of current sources and removal o

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Thomas, David A. "Characterization of water fluxes at a trench and gate groundwater remediation site." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape9/PQDD_0018/MQ48049.pdf.

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Hoyne, William E. "Three dimensional flow and transport modelling of a Trench and Gate system in a low permeability till." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ55217.pdf.

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Maglie, Rodolphe de. "Modélisation de différentes technologies de transistors bipolaires à grille isolée pour la simulation d'applications en électronique de puissance." Toulouse 3, 2007. https://tel.archives-ouvertes.fr/tel-00153597.

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L'analyse et la conception des systèmes en électronique de puissance nécessitent la prise en compte de phénomènes complexes propres à chaque composant du système mais aussi en accord avec son environnement. La description précise du comportement d'un système passe par la simulation utilisant des modèles suffisamment précis de tous ces composants. Dans notre étude, les modèles basés sur la physique des semiconducteurs permettent de décrire le comportement de la charge stockée dans la base large et peu dopée des composants bipolaires. Cette description fine est indispensable à la bonne précision

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Gay, Roméric. "Développement de composants analogiques embarqués dans des microcontrôleurs destinés à l'Internet des Objets (loT)." Electronic Thesis or Diss., Aix-Marseille, 2022. http://www.theses.fr/2022AIXM0218.

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L’objectif de ces travaux de thèse a été d'améliorer les performances, le coût et la surface de silicium occupés par un microcontrôleur fabriqué sur la base d’une technologie mémoire embarquée CMOS (eNVM) 40 nm. Ces améliorations ont été réalisées grâce au développement de nouvelles architectures de transistors adaptées au besoin du marché de l’IoT. Dans une première partie, le contexte dans lequel s’inscrit cette thèse est exposé par la présentation des limites technologiques et économiques de technologie CMOS. Dans une deuxième partie, le procédé de fabrication eNVM ainsi que l’architecture

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Ramadout, Benoit. "Capteurs d’images CMOS à haute résolution à Tranchées Profondes Capacitives." Thesis, Lyon 1, 2010. http://www.theses.fr/2010LYO10068.

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Les capteurs d'images CMOS ont connu au cours des six dernières années une réduction de la taille des pixels d'un facteur quatre. Néanmoins, cette miniaturisation se heurte à la diminution rapide du signal maximal de chaque pixel et à l'échange parasite entre pixels (diaphotie). C'est dans ce contexte qu'a été développé le Pixel à Tranchées Profondes Capacitives et Grille de Transfert verticale (pixel CDTI+VTG). Basé sur la structure d'un pixel « 4T », il intègre une isolation électrique par tranchées, une photodiode profonde plus volumineuse et une grille verticale permettant le stockage prof

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Hsu, Sheng-Tai, and 徐盛泰. "Improvement of Trench Gate MOSFET Gate Oxide Process." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/99k854.

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碩士<br>國立交通大學<br>工學院半導體材料與製程設備學程<br>102<br>This paper is mainly investigate TEOS gas at the vertical furnace LPCVD method to grow UMOSFET gate oxide process, and improved to achieve production condition. Can be divided into three main parts: First, research of this TEOS LPCVD process when the pressure controlled at 1.3torr and the vertical reaction chamber due to reaction gas concentration decreasing from bottom to top zone, this difference affect the deposition thickness distribution of reaction chamber top zone is bowl shaped and bottom zone is bull's-eye shaped, these wafer to wafer and with

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Tai, Shih-Hsiang, and 戴士翔. "Optimal Design of Trench Gate Insulted Gate Bipolar Transistor." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/99755982922692722594.

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碩士<br>國立臺灣科技大學<br>電子工程系<br>90<br>In recent years, the performance and fabrication of IGBT’s have been significantly improved and the application field of IGBT have widely been expending, especially in high power electronic device. It is reported that the Trench-Gate IGBT has superior characteristics in power loss compared to conventional planar IGBT. In this thesis, the Trench-Gate IGBT has a high power gain, high input impedance, and high switching speed. Due to these advantage, the effort to improve the Trench-Gate IGBT performances operating above 600V and 100A/cm² are the goal in this thes

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Chen, Wen-Tsung, and 陳文聰. "Optimal Design of Trench-Gate Power MOSFET's." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/93425617005975900499.

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碩士<br>國立臺灣科技大學<br>電子工程系<br>89<br>Abstract Power MOSFET’s are important discrete devices for a variety of power conversion applications in the voltage range below 200 V because of low conduction power loss, high input impedance, and high switching speed. Due to these advantages, the effort to improve the power MOSFET’s performance operating above 30 V is the goal in this thesis. We use Tsuprem4 process simulator and MEDICI device simulator to help designing the device. To enhance the process toleration, we qualify the device in 35 V and obtain the optimal process parameters and ch

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Book chapters on the topic "Trench-gate"

1

Tahalyani, Geeta, Raghvendra Sahai Saxena, and T. Vigneswaran. "High Performance Trench Gate Power MOSFET of Indium Phosphide." In Nanoelectronic Materials and Devices. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-7191-1_16.

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Erlbacher, Tobias. "Lateral Power Transistors Combining Planar and Trench Gate Topologies." In Power Systems. Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-00500-3_8.

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3

Zhang, Qing Chun, Sei Hyung Ryu, Charlotte Jonas, Anant Agarwal, and John Palmour. "Simulations of 10 kV Trench Gate IGBTs on 4H-SiC." In Silicon Carbide and Related Materials 2005. Trans Tech Publications Ltd., 2006. http://dx.doi.org/10.4028/0-87849-425-1.1405.

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Bharti, Deepshikha, and Aminul Islam. "U-Shaped Gate Trench Metal Oxide Semiconductor Field Effect Transistor: Structures and Characteristics." In Nanoscale Devices. CRC Press, 2018. http://dx.doi.org/10.1201/9781315163116-4.

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Jaiswal, Nilesh Kumar, and V. N. Ramakrishnan. "A Vertical GaN Split Gate Trench MOSFET Device with Reduced Switching Energy Losses." In Springer Proceedings in Physics. Springer Nature Singapore, 2024. http://dx.doi.org/10.1007/978-981-97-1571-8_41.

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Bhattacharya, Arkaprio, Ananya Barman, Trina Dutta, and Swagata Bhattacherjee. "Investigation of Channel Doping Effects on High-Frequency Noise for Trench Double Gate JLFETs." In Springer Proceedings in Physics. Springer Nature Switzerland, 2024. https://doi.org/10.1007/978-3-031-69146-1_6.

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"Trench-Gate Power MOSFETs." In Silicon Carbide Power Devices. WORLD SCIENTIFIC, 2006. http://dx.doi.org/10.1142/9789812774521_0011.

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"Trench-Gate Power MOSFETs." In Modern Silicon Carbide Power Devices. WORLD SCIENTIFIC, 2023. http://dx.doi.org/10.1142/9789811284281_0012.

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"Shielded Trench-Gate Power MOSFETs." In Silicon Carbide Power Devices. WORLD SCIENTIFIC, 2006. http://dx.doi.org/10.1142/9789812774521_0012.

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"SiC Trench-Gate Power MOSFETs." In Gallium Nitride and Silicon Carbide Power Devices. WORLD SCIENTIFIC, 2016. http://dx.doi.org/10.1142/9789813109414_0012.

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Conference papers on the topic "Trench-gate"

1

Wang, Chen, Ying Yang, Zixuan Liu, and Qiyang Zhao. "Shallow Trench Design for Silicon Carbide Planar-Gate MOSFETs." In 2024 3rd International Symposium on Semiconductor and Electronic Technology (ISSET). IEEE, 2024. https://doi.org/10.1109/isset62871.2024.10779926.

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Biswal, Rasmiranjan, Alok Naugarhiya, and Nilesh Goel. "Analysis of Trench Gate IGBT with GaN-AlN Dielectric Stacking." In 2024 IEEE Third International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES). IEEE, 2024. http://dx.doi.org/10.1109/icpeices62430.2024.10719131.

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Cao, Xiangxin, MinHan Mi, Pengfei Wang, Xiang Du, Xinyi Wen, and Feiyang Chen. "Influence of Gate Trench Length on Millimeter Wave Aigan/Gan Hemt." In 2024 21st China International Forum on Solid State Lighting & 2024 10th International Forum on Wide Bandgap Semiconductors (SSLCHINA: IFWS). IEEE, 2024. https://doi.org/10.1109/sslchinaifws64644.2024.10835275.

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Ramadout, Benoit, Guo-Neng Lu, and Jean-Pierre Carrere. "MOSFET with additional lateral trench gate." In 2009 21st International Conference on Microelectronics (ICM 2009). IEEE, 2009. http://dx.doi.org/10.1109/icm.2009.5418609.

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Chang, H. R., B. J. Baliga, J. W. Kretchmer, and P. A. Piacente. ""Insulated gate bipolar transistor (IGBT) with a trench gate structure "." In 1987 International Electron Devices Meeting. IRE, 1987. http://dx.doi.org/10.1109/iedm.1987.191518.

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Jae In Lee, Jongchan Choi, Young-seok Bae, and Man Young Sung. "A novel trench IGBT with a rectangular oxide beneath the trench gate." In 2009 1st Asia Symposium on Quality Electronic Design (ASQED 2009). IEEE, 2009. http://dx.doi.org/10.1109/asqed.2009.5206237.

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Katoh, Shunsuke, Yusuke Kawaguchi, and Akio Takano. "High channel mobility double gate trench MOSFET." In 2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD). IEEE, 2014. http://dx.doi.org/10.1109/ispsd.2014.6856002.

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Cailin Wang, Cheng Sun, and Junya Han. "A new trench-planner gate MOSFET structure." In 2009 IEEE 6th International Power Electronics and Motion Control Conference. IEEE, 2009. http://dx.doi.org/10.1109/ipemc.2009.5157566.

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Sarnecki, Lori L. "Locating Gate Oxide Failures Using KOH." In ISTFA 2016. ASM International, 2016. http://dx.doi.org/10.31399/asm.cp.istfa2016p0208.

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Abstract This paper presents two new methods using potassium hydroxide (KOH) as a wet etch technique to successfully stop on gate oxide and find the submicron gate oxide failures that correspond to failure response sites. Applications of this new technique to submicron gate oxide failures on both planar and deep trench MOSFET devices are reported in this paper.

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Nakano, H., Y. Onozawa, R. Kawano, T. Yamazaki, and Y. Seki. "600V trench-gate IGBT with Micro-P structure." In IC's (ISPSD). IEEE, 2009. http://dx.doi.org/10.1109/ispsd.2009.5158019.

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