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Journal articles on the topic 'Trench-gate'

Author: Grafiati

Published: 3 June 2025

Last updated: 31 July 2025

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1

Kojima, Takahito, Shinsuke Harada, Keiko Ariyoshi, et al. "Reliability Improvement and Optimization of Trench Orientation of 4H-SiC Trench-Gate Oxide." Materials Science Forum 778-780 (February 2014): 537–40. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.537.

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Reliability of gate oxide for trench-gate MOSFET was improved by deposited oxide film with uniform thickness and high-temperature annealing after trench etching. Optimum wafer orientation and trench direction for the trench gate was investigated, and the gate oxide on (11-20) plane of carbon face exhibited the longest lifetime. Influences by the roughness of sidewall and the radius of trench corner are discussed.

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2

Seok, Ogyun, Hyoung Woo Kim, In Ho Kang, Min-Woo Ha, and Wook Bahng. "Effects of junction profiles in bottom protection p-well on electrical characteristics of 1.2 kV SiC trench-gate MOSFETs." European Physical Journal Applied Physics 88, no. 3 (2019): 30103. http://dx.doi.org/10.1051/epjap/2020190269.

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Effects of junction profiles in bottom protection p-well (BPW) on electrical characteristics of 1.2 kV SiC trench-gate MOSFETs were investigated using simulation methods. Breakdown mechanisms of BPW in the device were also elucidated by energy-band diagram and electric-field distribution across trench-gate. Monte Carlo Al-implantation simulation on the trench structure for BPW formation was carried out with variations in peak depth (DBPW), concentration (NBPW), and thickness of SiO2 spacer (Tspacer) on trench sidewall. The SiC trench-gate MOSFETs with deep DBPW, high NBPW, and thin Tspacer are

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3

Wang, Bo. "Analysis of junction capacitance characteristics of trench gate IGBT." E3S Web of Conferences 237 (2021): 02024. http://dx.doi.org/10.1051/e3sconf/202123702024.

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Trench gate field termination IGBT represents the latest structure of insulated gate bipolar transistor (IGBT). Because the internal current of IGBT includes the charging and discharging current of gate capacitance and internal junction capacitance during switching transient, the influence of junction capacitance should be considered. The conductive channel of trench gate structure is different from that of planar gate structure, and the analysis method of junction capacitance using planar gate structure will inevitably bring some deviation. Based on the characteristics of trench gate structur

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4

Jones, Ben, Alex Croot, Jacob Mitchell, et al. "Demonstrating SiC <i>In Situ</i> Rounded Trench Processing Technologies for Future Power Trench MOSFET Applications." Solid State Phenomena 359 (August 22, 2024): 163–70. http://dx.doi.org/10.4028/p-us98lu.

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Effective control of device geometry is key to mitigating high localized electric fields in next-generation SiC power devices. Advanced trench processing allows for highly tunable trench-gate architectures in trench MOSFETs. By utilizing a two-step inductively coupled plasma reactive ion etch (ICP-RIE) process, a high degree of trench base corner rounding can be achieved, irrespective of trench opening corner geometry prior to post etch treatments. Sentaurus TCAD device modelling highlights the importance of effective electric field dispersion at the gate oxide using rounded trench corners, wh

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5

Wang, Bo. "Analysis of base characteristics of trench gate field termination IGBT." E3S Web of Conferences 237 (2021): 02023. http://dx.doi.org/10.1051/e3sconf/202123702023.

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Trench gate structure represents the latest structure of Insulated Gate Bipolar Transistor(IGBT). Because there are great differences in model analysis coordinate system and carrier transport between trench gate structure and planar gate structure, the modeling method using planar gate structure will inevitably have great deviation. Based on the characteristics of trench gate structure and model analysis coordinate system, the base region is divided into PNP and PIN by considering the two-dimensional effect of carriers. According to whether the trench of PIN part can be covered by depletion la

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6

Cho, Doohyung, and Kwangsoo Kim. "Trench Power MOSFET using Separate Gate Technique for Reducing Gate Charge." Journal of IKEEE 16, no. 4 (2012): 283–89. http://dx.doi.org/10.7471/ikeee.2012.16.4.283.

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7

Huang, Lin Hua, Yong Liu, Xin Peng, et al. "Design of Al<sub>2</sub>O<sub>3</sub>/LaAlO<sub>3</sub>/SiO<sub>2</sub> Gate Stack on Various Channel Planes for High-Performance 4H-SiC Trench Power MOSFETs." Solid State Phenomena 358 (August 21, 2024): 79–87. http://dx.doi.org/10.4028/p-9mknrr.

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An Al2O3/LaAlO3/SiO2 gate stack is designed and implemented on various trench-gate channel planes for high-performance trench power MOSFETs. The designed high-k gate stack achieves a significant enhancement in the gate blocking capability (~1.73X) and maintains a low interface state density (Dit), in comparison to the SiO2 gate. Moreover, owing to the implementation of the high-k gate stack, the high-k trench gate MOSFETs conduct a drain current of approximately 1.3 times larger than that of the SiO2 trench gate MOSFETs on all 24 channel planes at the same overdrive voltage (Vgs-Vth) of 10 V.

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8

Miyahara, Shinichiro, H. Watanabe, T. Yamamoto, et al. "Effect of Damage Removal Treatment after Trench Etching on the Reliability of Trench MOSFET." Materials Science Forum 740-742 (January 2013): 789–92. http://dx.doi.org/10.4028/www.scientific.net/msf.740-742.789.

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Guaranteeing the reliability of gate oxides is one of the most important topics to realize regarding the SiC power MOSFET. In the case of trench MOSFET, since the gate oxides are formed on the trench sidewall, the damage and roughness on the trench sidewall can affect the lifetime of the gate oxides. Generally speaking, damage removal treatment is processed after trench dry etching in most cases. In Si processes, sacrificial oxidation, H2 anneal and CDE (Chemical Dry Etching) are adopted commonly. In the case of SiC processes, sacrificial oxidation, H2 anneal, and SiH4/Ar anneal have been repo

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9

Kagawa, Yasuhiro, Rina Tanaka, Nobuo Fujiwara, et al. "Introduction of Depletion Stopper for Reduction of JFET Resistance for 4H-SiC Trench MOSFET." Materials Science Forum 821-823 (June 2015): 761–64. http://dx.doi.org/10.4028/www.scientific.net/msf.821-823.761.

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This paper investigates thereduction of parasitic resistance (JFET resistance) betweenthe p-well and the grounded p-type gate-oxide protection layer (BPW)of a trench-gate SiC-MOSFET. Forming a deeptrench is a way to reducethe JFET resistance, but this consequently leads to high electric field at thebottom oxide. In order to improve the trade-off between the specific on-resistance (Ron,sp) and the maximum bottom oxide electric field (Eox), wenewly developed a trench-gate SiC-MOSFET with an n-type region, named DepletionStopper (DS), formed under the entire p-welllayer. As aresult of fabrication

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10

Manosukritkul, Phasapon, Amonrat Kerdpardist, Montree Saenlamool, Ekalak Chaowicharat, Amporn Poyai, and Wisut Titiroongruang. "An Improvement of the Breakdown Voltage Characteristics of NPT-TIGBT by Using a P-Buried Layer." Advanced Materials Research 717 (July 2013): 158–63. http://dx.doi.org/10.4028/www.scientific.net/amr.717.158.

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In this paper, we introduced a P-buried (Pb) layer under trench gate which relieved the electric field crowding in the Non Punch Through Trench gate Insulated Gate Bipolar Transistor (NPT-TIGBT) structure. The Pblayer, with carrier concentration of 5x1016cm-3, was created underneath the trench gate within the n-drift layer. In this way, the concentration of electric field at the trench bottom corner decreased. As a result, the breakdown voltage characteristics of NPT-TIGBT improved. The structures were proposed and verified by T-CAD Sentuarus simulation. From the simulation results, the breakd

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11

Yoneda, Kenji, Yoshihiro Todokoro, and Morio Inoue. "Thin silicon dioxide and nitrided oxide using rapid thermal processing for trench capacitors." Journal of Materials Research 6, no. 11 (1991): 2362–70. http://dx.doi.org/10.1557/jmr.1991.2362.

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Electrical characteristics of trench capacitors using RTO (Rapid Thermal Oxidation) oxides, nitroxides, and reoxidized nitroxides as the gate insulators are discussed. High temperature RTO is effective in preventing oxide thinning at the trench corner, and so the dielectric strength of trench capacitors is improved drastically. The mean time to failure (MTTF) of trench capacitors using RTO is more than ten times longer than that of trench capacitors using conventional furnaces. Using reoxidized nitroxides as the gate insulator, superior charge to breakdown (QBD) is obtained. RTP (Rapid Thermal

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12

Kagawa, Yasuhiro, Nobuo Fujiwara, Katsutoshi Sugawara, et al. "4H-SiC Trench MOSFET with Bottom Oxide Protection." Materials Science Forum 778-780 (February 2014): 919–22. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.919.

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Ensuring gate oxide reliability and low switching loss is required for a trench gate SiC-MOSFET. We developed a trench gate SiC-MOSFET with a p-type region, named Bottom P-Well (BPW), formed at the bottom of the trench gate for bottom oxide protection. We can see an effective reduction in the maximum bottom oxide electric field (Eox) and a significant improvement in dynamic characteristics with a grounded BPW, whose dV/dt is 76 % larger than that with a floating BPW due to reduction in gate-drain capacitance (Cgd). The grounded BPW is found to be an effective means of both suppressing Eox and

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13

Wei, Zhaoxiang, Hao Fu, Xiaowen Yan, et al. "Influence of Different Device Structures on the Degradation for Trench-Gate SiC MOSFETs: Taking Avalanche Stress as an Example." Materials 15, no. 2 (2022): 457. http://dx.doi.org/10.3390/ma15020457.

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The variations in the degradation of electrical characteristics resulting from different device structures for trench-gate SiC metal-oxide-semiconductor field effect transistors (MOSFETs) are investigated in this work. Two types of the most advanced commercial trench products, which are the asymmetric trench SiC MOSFET and the double-trench SiC MOSFET, are chosen as the targeted devices. The discrepant degradation trends caused by the repetitive avalanche stress are monitored. For the double-trench device, the conduction characteristic improves while the gate-drain capacitance (Cgd) increases

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14

Nakano, Yuki, R. Nakamura, H. Sakairi, Shuhei Mitani та T. Nakamura. "690V, 1.00 mΩcm² 4H-SiC Double-Trench MOSFETs". Materials Science Forum 717-720 (травень 2012): 1069–72. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.1069.

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The trench gate structure MOSFET, with its lack of JFET resistance, is one of the structures able to achieve low on-state resistance [1,2]. In 2008, this group succeeded in fabricating 790V SiC trench MOSFETs with the lowest Ron,sp (1.7 mΩcm2) at room temperature. However these devices had issues regarding oxide destruction at the trench bottom during high drain-source voltage application. In order to improve this problem, this group developed the double-trench MOSFET structure. This structure has both source trenches and gate trenches. This paper compares two kinds of trench MOSFETs: the conv

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15

Yang, Ling Ling. "A Novel Structure Trench IGBT with Full Hole-Barrier Layer." Applied Mechanics and Materials 543-547 (March 2014): 757–61. http://dx.doi.org/10.4028/www.scientific.net/amm.543-547.757.

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A Full Hole-barrier Trench gate Insulated Gate Bipolar Transistor (FH-TIGBT) device structure is proposed for the first time. Compared with Carrier Stored Trench IGBT (CSTBT), which adds a carrier stored n layer between p base and n base in Trench IGBT (TIGBT), the new structure appends an n region located in the bottom of the trench gate. The result of Process and device simulations shows that the proposed device has lowered saturation voltage and larger capability of carrying current compared to either conventional trench IGBT or CSTBT. And the characteristics of turn-off time and breakdown

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16

Park, Dong Gyu, Hyunwoo Kim, and Jang Hyun Kim. "Improvement Breakdown Voltage by a Using Crown-Shaped Gate." Electronics 12, no. 3 (2023): 474. http://dx.doi.org/10.3390/electronics12030474.

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In this paper, a crown-shaped trench gate formed by a sidewall spacer in insulated gate bipolar transistors (IGBT) is proposed to improve breakdown voltage. When a sidewall spacer is added to trench bottom corners, the electric field is distributed to the surface of the sidewall spacer and decreased to 48% peak value of the electric field. Thus, the sidewall spacer IGBT improved to 5% breakdown voltage. Another study proposed an additional oxide layer for trench bottom corners and improved breakdown voltage similar to the proposed IGBT. Previous studies have shown degradation in other electric

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17

Na, Jaeyeop, Jinhee Cheon, and Kwangsoo Kim. "4H-SiC Double Trench MOSFET with Split Heterojunction Gate for Improving Switching Characteristics." Materials 14, no. 13 (2021): 3554. http://dx.doi.org/10.3390/ma14133554.

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In this paper, a novel 4H-SiC split heterojunction gate double trench metal-oxide-semiconductor field-effect transistor (SHG-DTMOS) is proposed to improve switching speed and loss. The device modifies the split gate double trench MOSFET (SG-DTMOS) by changing the N+ polysilicon split gate to the P+ polysilicon split gate. It has two separate P+ shielding regions under the gate to use the P+ split polysilicon gate as a heterojunction body diode and prevent reverse leakage `current. The static and most dynamic characteristics of the SHG-DTMOS are almost like those of the SG-DTMOS. However, the r

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18

Deng, Xiaochuan, Rui Liu, Songjun Li, Ling Li, Hao Wu, and Xuan Li. "SiC Fin-Shaped Gate Trench MOSFET with Integrated Schottky Diode." Materials 14, no. 22 (2021): 7096. http://dx.doi.org/10.3390/ma14227096.

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A silicon carbide (SiC) trench MOSFET featuring fin-shaped gate and integrated Schottky barrier diode under split P type shield (SPS) protection (FS-TMOS) is proposed by finite element modeling. The physical mechanism of FS-TMOS is studied comprehensively in terms of fundamental (blocking, conduction, and dynamic) performance and transient extreme stress reliability. The fin-shaped gate on the sidewall of the trench and integrated Schottky diode at the bottom of trench aim to the reduction of gate charge and improvement on the third quadrant performance, respectively. The SPS region is fully u

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19

Hung, Chia Lung, Yi Kai Hsiao, Chang Ching Tu, and Hao Chung Kuo. "Investigation of 4H-SiC UMOSFET Architectures for High Voltage and High Speed Power Switching Applications." Materials Science Forum 1088 (May 18, 2023): 41–49. http://dx.doi.org/10.4028/p-56sbi2.

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A comparative TCAD (Technology Computer Aided Design) simulation study of various 4H-SiC trench gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (or U-shaped trench gate MOSFET abbreviated for UMOSFET) architectures for high voltage and high-speed switching applications is reported. The DC (Direct Current) and AC (Alternating Current) characteristics of the different trench gate structures are investigated. Particularly, compared to conventional 4H-SiC UMOSFETs, the breakdown voltage of the UMOSFET having a p-type implanted bottom shield is increased by 44%. However, due to the

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20

Zhang, Meng, Baikui Li, and Jin Wei. "Exploring SiC Planar IGBTs towards Enhanced Conductivity Modulation Comparable to SiC Trench IGBTs." Crystals 10, no. 5 (2020): 417. http://dx.doi.org/10.3390/cryst10050417.

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The state-of-the-art silicon insulated-gate bipolar transistor (IGBT) features a trench gate, since it enhances the conductivity modulation. The SiC trench IGBT, however, faces the critical challenge of a high electric field in the gate oxide, which is a crucial threat to the device’s reliability. In this work, we explore the possibility of using a SiC planar IGBT structure to approach high performance to the level of a SiC trench IGBT, without suffering the high gate oxide field. The proposed SiC planar IGBT features buried p-layers directly under the p-bodies, and thus can be formed using th

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21

Lee, Kwang Won, Jake Choi, Young Ho Seo, Kyeong Seok Park, Martin Domeij, and Fredrik Allerstam. "Design Optimization and Reliability Evaluation in 1.2 kV SiC Trench MOSFET with Deep P Structure." Solid State Phenomena 361 (August 26, 2024): 47–52. http://dx.doi.org/10.4028/p-d7iozt.

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In this paper, 1.2 kV SiC trench MOSFET with deep P structure has been proposed to effectively shield the trench bottom oxide. The various design splits, such as N concentration between deep P and deep P to trench distance, were experimentally evaluated and TCAD simulations were performed to extract maximum oxide electric field at trench bottom. Based on trade off results, critical design parameters were optimized to obtain low Rdson and stable breakdown voltage with acceptable oxide electric field. To evaluate trench gate oxide reliability in wafer level, gate oxide integrity (GOI/Vramp), cha

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22

Yan, Siao-Cheng, Chen-Han Wu, Chong-Jhe Sun, Yi-Wen Lin, Yi-Ju Yao, and Yung-Chun Wu. "Trench FinFET Nanostructure with Advanced Ferroelectric Nanomaterial HfZrO2 for Sub-60-mV/Decade Subthreshold Slope for Low Power Application." Nanomaterials 12, no. 13 (2022): 2165. http://dx.doi.org/10.3390/nano12132165.

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Ferroelectric fin field-effect transistors with a trench structure (trench Fe-FinFETs) were fabricated and characterized. The inclusion of the trench structures improved the electrical characteristics of the Fe-FinFETs. Moreover, short channel effects were suppressed by completely surrounding the trench channel with the gate electrodes. Compared with a conventional Fe-FinFET, the fabricated trench Fe-FinFET had a higher on–off current ratio of 4.1 × 107 and a steep minimum subthreshold swing of 35.4 mV/dec in the forward sweep. In addition, the fabricated trench Fe-FinFET had a very low drain-

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23

Lan, Zhong, Yangjie Ou, Xiarong Hu, and Dong Liu. "A Novel 4H-SiC Asymmetric MOSFET with Step Trench." Micromachines 15, no. 6 (2024): 724. http://dx.doi.org/10.3390/mi15060724.

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In this article, a silicon carbide (SiC) asymmetric MOSFET with a step trench (AST-MOS) is proposed and investigated. The AST-MOS features a step trench with an extra electron current path on one side, thereby increasing the channel density of the device. A thick oxide layer is also employed at the bottom of the step trench, which is used as a new voltage-withstanding region. Furthermore, the ratio of the gate-to-drain capacitance (Cgd) to the gate-to-source capacitance (Cgs) is significantly reduced in the AST-MOS. As a result, the AST-MOS compared with the double-trench MOSFET (DT-MOS) and d

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24

Wu, Hao, Xuan Li, Xiaochuan Deng, et al. "A Novel 6500 V SiC Trench MOSFET with Integrated Unipolar Diode for Improved Third Quadrant and Switching Characteristics." Micromachines 15, no. 1 (2023): 92. http://dx.doi.org/10.3390/mi15010092.

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A 6500 V SiC trench MOSFET with integrated unipolar diode (UD-MOS) is proposed to improve reverse conduction characteristics, suppress bipolar degradation, and reduce switching loss. An N type base region under the trench dummy gate provides a low barrier path to suppress hole injection during the reverse conduction operation. The reverse conduction voltage VON is reduced to 1.11 V, and the reverse recovery charge (QRR) is reduced to 1.22 μC/cm2. The gate-to-drain capacitance (CGD) and gate-to-source capacitance (CGS) of the UD-MOS are also reduced to improve switching loss due to the thick ox

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25

Kim, J., S. G. Kim, T. M. Roh, and B. Lee. "High-density trench gate DMOSFETs with trench contact structure." Electronics Letters 40, no. 11 (2004): 699. http://dx.doi.org/10.1049/el:20040478.

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26

Nida, Selamnesh, Thomas Ziemann, Bhagyalakshmi Kakarla, and Ulrike Grossner. "Effect of Negative Gate Bias on Single Pulse Avalanche Ruggedness of 1.2 kV Silicon Carbide MOSFETs." Materials Science Forum 924 (June 2018): 735–38. http://dx.doi.org/10.4028/www.scientific.net/msf.924.735.

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When power MOSFETs experience a voltage spike initiating avalanche generation, a large amount of power is dissipated at the device junction. This leads to self-heating and lowers the threshold voltage. Some sources indicate that unintended opening of the channel creates a positive feedback, thereby increasing heat generation and leading to thermal runaway. Therefore, keeping MOSFETs off by applying a negative gate bias should improve avalanche ruggedness. In this report, this claim is investigated by comparing single pulse avalanche ruggedness of commercial 1.2 kV, 80 mÎ© planar and trench MOS

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27

Ou, Yangjie, Zhong Lan, Xiarong Hu, and Dong Liu. "Novel SiC Trench MOSFET with Improved Third-Quadrant Performance and Switching Speed." Micromachines 15, no. 2 (2024): 254. http://dx.doi.org/10.3390/mi15020254.

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A SiC double-trench MOSFET embedded with a lower-barrier diode and an L-shaped gate-source in the gate trench, showing improved reverse conduction and an improved switching performance, was proposed and studied with 2-D simulations. Compared with a double-trench MOSFET (DT-MOS) and a DT-MOS with a channel-MOS diode (DTC-MOS), the proposed MOS showed a lower voltage drop (VF) at IS = 100 A/cm2, which can prevent bipolar degradation at the same blocking voltage (BV) and decrease the maximum oxide electric field (Emox). Additionally, the gate–drain capacitance (Cgd) and gate–drain charge (Qgd) of

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28

Green, Ronald, Damian Urciuoli, and Aivars J. Lelis. "Short-Circuit Robustness of SiC Trench MOSFETs." Materials Science Forum 924 (June 2018): 715–18. http://dx.doi.org/10.4028/www.scientific.net/msf.924.715.

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An investigation into the robustness of 1200-V/80-mΩ commercial trench-gate MOSFETs reveals that the critical energy for failure during short-circuit operation is reached in shorter times in comparison to similarly rated planar DMOSFETs under similar stress conditions. This critical energy for trench devices was estimated to be between 615 mJ to 660 mJ depending on the gate-drive voltage. These values are considerably smaller when compared to DMOSFETs from the same manufacturer. In comparison to planar designs, trench devices can have lower losses, and manufactured with much smaller chip size

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29

Wei, Jia Xing, Si Yang Liu, Sheng Li, et al. "Investigations on the Resistance Reduction Effect of Double-Trench SiC MOSFETs under Repetitive Avalanche Stress." Materials Science Forum 1004 (July 2020): 998–1003. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.998.

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The unexpected resistance reduction effect of double-trench SiC MOSFETs under repetitive avalanche stress is investigated in this work. After enduring repetitive avalanche stress, the ON-state drain-source resistance (Rdson) of the device decreases. With the help of TCAD simulations, the dominant mechanism is proved to be the injection of positive charges into the gate trench bottom oxide, which is almost irreversible under zero-voltage bias condition at room temperature. For the injected positive charges attract extra electrons just beneath the gate trench bottom, where the carriers pass thro

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30

Shi, Limeng, Jiashu Qian, Michael Jin, et al. "Gate Oxide Reliability in Silicon Carbide Planar and Trench Metal-Oxide-Semiconductor Field-Effect Transistors Under Positive and Negative Electric Field Stress." Electronics 13, no. 22 (2024): 4516. http://dx.doi.org/10.3390/electronics13224516.

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This work investigates the gate oxide reliability of commercial 1.2 kV silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) with planar and trench gate structures. The performance of threshold voltage (Vth) and gate leakage current (Igss) in SiC MOSFETs is evaluated under positive and negative gate voltage stress. The oxide lifetimes of SiC planar and trench MOSFETs at 150 °C are measured using constant voltage Time-Dependent Dielectric Breakdown (TDDB) testing. From the test results, it is found that electron trapping and hole trapping in SiO2 caused by oxide ele

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31

Jiang, Jheng-Yi, Tian-Li Wu, Feng Zhao, and Chih-Fang Huang. "Numerical Study of 4H-SiC UMOSFETs with Split-Gate and P+ Shielding." Energies 13, no. 5 (2020): 1122. http://dx.doi.org/10.3390/en13051122.

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In this paper, performances of a 4H-SiC UMOSFET with split gate and P+ shielding in different configurations are simulated and compared, with an emphasis on the switching characteristics and short circuit capability. A novel structure with the split gate in touch with the P+ shielding is proposed. The key design issues for 4H-SiC UMOSFETs are trench gate dielectric protection and reverse transfer capacitance Crss reduction. Based on simulation results, it is concluded that a UMOSFET with a gate structure combining split gate grounded to the trench bottom protection P+ shielding layer and a cur

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32

Vudumula, Pavan, Umesh Chand, Lakshmi Kanta Bera, Calvin Hung Ming Chua, Navab Singh та Surasit Chung. "Temperature-Dependent Evaluation of Commercial 1.2 kV, 40 mΩ 4H-SiC MOSFETs: A Comparative Study between Planar, One-Side Shielded Trench, and Double Trench Gate Structures". Solid State Phenomena 360 (23 серпня 2024): 133–37. http://dx.doi.org/10.4028/p-9zwfjb.

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This research investigates the static and dynamic characteristics of 4H-Silicon Carbide (SiC) MOSFETs with different gate structures: planar (Device A), one-side shielded trench (Device B), and double trench (Device C). We analyze threshold voltage, on-state resistance, transconductance, gate-to-source capacitances, and reverse transfer/miller capacitances with gate bias. Additionally, non-linear charges, including input charge, miller plateau, and total gate charge, are examined. Switching losses are assessed over a temperature range of 25° C to 125° C. Our findings reveal distinct performanc

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33

Zhang, Meng, Baikui Li, Zheyang Zheng, Xi Tang, and Jin Wei. "A New SiC Planar-Gate IGBT for Injection Enhancement Effect and Low Oxide Field." Energies 14, no. 1 (2020): 82. http://dx.doi.org/10.3390/en14010082.

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A new silicon carbide (SiC) planar-gate insulated-gate bipolar transistor (IGBT) is proposed and comprehensively investigated in this paper. Compared to the traditional SiC planar-gate IGBT, the new IGBT boasts a much stronger injection enhancement effect, which leads to a low on-state voltage (VON) approaching the SiC trench-gate IGBT. The strong injection enhancement effect is obtained by a heavily doped carrier storage layer (CSL), which creates a hole barrier under the p-body to hinder minority carriers from being extracted away through the p-body. A p-shield is located at the bottom of th

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34

Chen, Xudong, Jianbing Cheng, Guobing Teng, and Houdong Guo. "Novel trench gate field stop IGBT with trench shorted anode." Journal of Semiconductors 37, no. 5 (2016): 054008. http://dx.doi.org/10.1088/1674-4926/37/5/054008.

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35

Zou, Yuan, Jue Wang, Hongyi Xu, and Hengyu Wang. "Investigation of SiC Trench MOSFETs’ Reliability under Short-Circuit Conditions." Materials 15, no. 2 (2022): 598. http://dx.doi.org/10.3390/ma15020598.

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In this paper, the short-circuit robustness of 1200 V silicon carbide (SiC) trench MOSFETs with different gate structures has been investigated. The MOSFETs exhibited different failure modes under different DC bus voltages. For double trench SiC MOSFETs, failure modes are gate failure at lower dc bus voltages and thermal runaway at higher dc bus voltages, while failure modes for asymmetric trench SiC MOSFETs are soft failure and thermal runaway, respectively. The shortcircuit withstanding time (SCWT) of the asymmetric trench MOSFET is higher than that of the double trench MOSFETs. The thermal

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Kim, Dae Won, Man Young Sung, and Ey Goo Kang. "A dual trench gate emitter switched thyristor (DTG-EST) with dual trench gate electrode and different gate oxide thickness." Microelectronic Engineering 70, no. 1 (2003): 50–57. http://dx.doi.org/10.1016/s0167-9317(03)00390-3.

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Banzhaf, Christian T., Michael Grieb, Achim Trautmann, Anton J. Bauer, and Lothar Frey. "Influence of Diverse Post-Trench Processes on the Electrical Performance of 4H-SiC MOS Structures." Materials Science Forum 778-780 (February 2014): 595–98. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.595.

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This paper focuses on the evaluation of subsequent process steps (post-trench processes, PTPs) after 4H silicon carbide (4H-SiC) trench etching with respect to the electrical performance of trenched gate metal oxide semiconductor field effect transistors (Trench-MOSFETs). Two different types of PTP were applied after 4H-SiC trench formation, a high temperature post-trench anneal (PTA) [1] and a sacrificial oxidation (SacOx) [2]. We found significantly improved electrical properties of Planar-MOS structures using a SacOx as PTP, prior to gate oxide deposition. Besides excellent quasi-static cap

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Banzhaf, Christian T., Michael Grieb, Achim Trautmann, Anton J. Bauer, and Lothar Frey. "Investigation of Trenched and High Temperature Annealed 4H-SiC." Materials Science Forum 778-780 (February 2014): 742–45. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.742.

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This study focuses on the effects of a high temperature anneal after dry etching of trenches (post-trench anneal, PTA) on 4Hsilicon carbide (4H-SiC). We aim at the optimum 4H-SiC post-trench treatment with respect to the fabrication and the operation of a trenched gate metal oxide semiconductor field effect transistor (Trench-MOSFET). PTA significantly reduces micro-trenches, also called sub-trenches [, in the corners of the bottom of the trench. This is highly beneficial in case the etched trench sidewall is used as the channel of a Trench-MOSFET. However, PTA is also shown to cause a slight

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Wu, Jiale, Houyong Zhou, and Yi Chen. "A Novel Super-junction MOSFET with Enhanced Switching Performance and Ruggedness." Journal of Physics: Conference Series 2524, no. 1 (2023): 012028. http://dx.doi.org/10.1088/1742-6596/2524/1/012028.

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Abstract In this paper, a novel super-junction (SJ) MOSFET with enhanced switching performance and ruggedness is proposed and investigated by the method of TCAD simulations. An N+/P- polysilicon junction gate electrode and separation layer between P-base and P-pillar are introduced to the trench SJ-MOSFET. For the N+/P- junction trench gate, the P- polysilicon located in the bottom of the trench plays the role of insulating layer, which efficiently reduces the gate charge (QG), thus increasing the switching speed and reducing the switching loss. The P-pillar does not contact with P-base so a d

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Cui, Wenrong, Jianbin Guo, Hang Xu, and David Wei Zhang. "A High-Density 4H-SiC MOSFET Based on a Buried Field Limiting Ring with Low Qgd and Ron." Micromachines 16, no. 4 (2025): 447. https://doi.org/10.3390/mi16040447.

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In this study, we propose an optimized shield gate trench 4H-SiC structure with effective gate oxide protection. The proposed device has a split trench with a P+ shield region, and the P+ shield is grounded by the middle deep trench. Our simulation results show that the peak electric field near the gate oxide is almost completely suppressed. Compared with a conventional P+ shield device, our proposed structure achieves a 78% reduction in the Qgd and a 108% increase in the FoM (figure of merit) simultaneously. Additionally, it is estimated that the device cell pitch can be reduced to 1.8 μm wit

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Na, Jaeyeop, Jinhee Cheon, and Kwangsoo Kim. "High performance 4H-SiC MOSFET with deep source trench." Semiconductor Science and Technology 37, no. 4 (2022): 045004. http://dx.doi.org/10.1088/1361-6641/ac5103.

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Abstract In this study, we investigated a 4H-SiC deep source trench metal-oxide semiconductor field-effect transistor (DST-MOSFET) using technology computer-aided design numerical simulations. The proposed DST-MOSFET comprises a P-pillar formed along with the DST and a side P+ shielding region (SPR), which replaces the gate trench bottom SPR. Owing to the superjunction generated by the P-pillar and N-drift region, the static characteristics of the DST-MOSFET were superior to those of the trench gate MOSFET (UMOSFET) and double-trench MOSFET (DT-MOSFET). The specific on-resistance and Baliga’s

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Qian, Zhehong, Wenrong Cui, Tianyang Feng, et al. "A Novel High-Speed Split-Gate Trench Carrier-Stored Trench-Gate Bipolar Transistor with Enhanced Short-Circuit Roughness." Micromachines 15, no. 6 (2024): 680. http://dx.doi.org/10.3390/mi15060680.

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A novel high-speed and process-compatible carrier-stored trench-gate bipolar transistor (CSTBT) combined with split-gate technology is proposed in this paper. The device features a split polysilicon electrode in the trench, where the left portion is equipotential with the cathode. This design mitigates the impact of the anode on the trench gate, resulting in a reduction in the gate-collector capacitance (CGC) to improve the dynamic characteristics. On the left side of the device cell, the P-layer, the carrier-stored (CS) layer and the P-body are formed from the bottom up by ion implantation an

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Fukui, Yutaka, Katsutoshi Sugawara, Kohei Adachi, et al. "Impact of Stripe Trench-Gate Structure for 4H-SiC Trench MOSFET with Bottom Oxide Protection Layer." Materials Science Forum 924 (June 2018): 761–64. http://dx.doi.org/10.4028/www.scientific.net/msf.924.761.

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An optimized layout for a trench-gate SiC-MOSFET with a self-aligned Bottom P-Well (BPW) was investigated for reduction of the specific on-resistance and switching loss. The static and dynamic characteristics of trench-gate MOSFETs with lattice and stripe in-plane structures were evaluated by varying the distance between neighboring BPWs (dBPWs). For the stripe structure, more significant improvements on the specific on-resistance (Ron,sp), gate-source threshold voltage (Vth) were achieved compared with the lattice structure, which was found to be due to the difference in the spread of the dep

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Tsou, L. Y., D. S. Kuo, R. H. Egloff, and S. Mukherjee. "Stacked oxide as trench gate dielectric." Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films 10, no. 4 (1992): 728–32. http://dx.doi.org/10.1116/1.577717.

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Jones, Ben, Jacob Mitchell, Jon Evans, et al. "Introducing Foundry-Compatible SiC and GaN Trench Processing Technologies for Reliable Automotive Application." Materials Science Forum 1062 (May 31, 2022): 582–87. http://dx.doi.org/10.4028/p-xd84zm.

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In this paper we report the progress of our SiC trench etch development using enhanced ICP-based etch technology. Computer modelling of the electric field strength in the gate oxide as a function of corner geometry was used to illustrate trench corner rounding as an effective method to avoid to high gate oxide field strengths. This is an effort to examine a major ongoing issue in device reliability, and to govern future device design.

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Takaya, Hidefumi, Jun Morimoto, Toshimasa Yamamoto, et al. "4H-SiC Trench MOSFET with Thick Bottom Oxide." Materials Science Forum 740-742 (January 2013): 683–86. http://dx.doi.org/10.4028/www.scientific.net/msf.740-742.683.

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A 4H-SiC trench MOSFET has been developed that features trench gates with a thick oxide layer on the bottoms of the trenches. The maximum electric field strength and gate-drain charge of this device are 46% and 38%, respectively lower than that of a conventional MOSFET. The drain-source breakdown voltage is 1400V and the specific on-resistance is 4.4mΩcm2 at a gate bias of 20V and a drain voltage of 2V.

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Zsolt, VISY. "The excavation in the Roman castellum of Énlaka - Inlăceni in 2022-2023." ANGVSTIA 27 (December 30, 2024): 113–32. https://doi.org/10.36935/ang.v27.5.

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Previous results were to determine the full extent and warehouse wing of the principia, followed by the eastern, northern and southern vallum trimming in 2016, 2019 and 2021. The purpose of the excavations was also to verify or refute the three- and four-period defensive works assumed by Komp. The 2022 excavation did not confirm his complicated periodization. The wall of the stone fort runs further north of the northern gate tower of the porta praetoria, based on previous surveys and geophysical surveys. The cause of this phenomenon was the slipping of the clay soil. The porta praetoria had tw

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Boldyrjew-Mast, Roman, Patrick Heimler, Xing Liu, et al. "Study of the Bias Driven Threshold Voltage Drift of 1.2 kV SiC MOSFETs in Power Cycling and High Temperature Gate Bias Tests." Solid State Phenomena 361 (August 26, 2024): 13–20. http://dx.doi.org/10.4028/p-s5n0pk.

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Threshold voltage instability remains a challenging aspect for metal-oxide semiconductor-field-effect-transistors (MOSFETs) made from silicon carbide (SiC). SiC MOSFETs from two manufacturers, with planar and trench gate structure respectively, have been tested under different test procedures, including power cycling and high temperature gate bias tests. The standard power cycling test setup has been modified to enable an in situ threshold voltage read-out procedure with the hysteresis method. The recorded threshold voltage drift has been compared with results from high temperature gate bias t

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Inoue, Jun, Shinichiro Kuroki, Seiji Ishikawa, et al. "4H-SiC Trench pMOSFETs for High-Frequency CMOS Inverters." Materials Science Forum 963 (July 2019): 837–40. http://dx.doi.org/10.4028/www.scientific.net/msf.963.837.

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Low-parasitic-capacitance 4H-SiC pMOSFETs using pseudo-self-aligned process were demonstrated for high-frequency CMOS inverters. In these pMOSFETs, device characteristics including parasitic capacitances (gate-source, gate-drain capacitance) were investigated and low parasitic capacitance was achieved by the trench gate structure.

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Liu, Li, Bo Pang, Siqiao Li, Yulu Zhen, and Gangpeng Li. "Research on the Short-Circuit Characteristics of Trench-Type SiC Power MOSFETs Under Single and Repetitive Pulse Strikes." Micromachines 16, no. 7 (2025): 768. https://doi.org/10.3390/mi16070768.

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This paper investigates the short-circuit characteristics of 1.2 kV symmetrical and asymmetrical trench-gate SiC MOSFETs. Based on the self-designed short-circuit test platform, single and repetitive short-circuit tests were carried out to characterize the short-circuit capability of the devices under different electrical stresses through the short-circuit withstanding time (SCWT). Notably, the asymmetric trench structure exhibited a superior short-circuit capability under identical test conditions, achieving a longer SCWT compared to its symmetrical counterpart. Moreover, TCAD was used to mod

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