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Dissertations / Theses on the topic 'Triple Modular Redundancy'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 July 2025

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1

Al-Kofahi, Khalid A. "Reliability analysis of triple modular redundancy system with spare /." Online version of thesis, 1993. http://hdl.handle.net/1850/11565.

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2

Baldwin, Andrew Lockett. "A Fault-Tolerant Alternative to Lockstep Triple Modular Redundancy." PDXScholar, 2012. https://pdxscholar.library.pdx.edu/open_access_etds/331.

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Semiconductor manufacturing defects adversely affect yield and reliability. Manufacturers expend vast resources to reduce defects within their processes. As the minimum feature size get smaller, defects become increasingly difficult to prevent. Defects can change the behavior of a logic circuit resulting in a fault. Manufacturers and designers may improve yield, reliability, and profitability by using design techniques that make products robust even in the presence of faults. Triple modular redundancy (TMR) is a fault tolerant technique commonly used to mask faults using voting outcomes from t

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3

Johnson, Jonathan Mark. "Synchronization Voter Insertion Algorithms for FPGA Designs Using Triple Modular Redundancy." Diss., CLICK HERE for online access, 2010. http://contentdm.lib.byu.edu/ETD/image/etd3418.pdf.

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4

Kakarla, Sujana. "Partial evaluation based triple modular redundancy for single event upset mitigation." [Tampa, Fla.] : University of South Florida, 2005. http://purl.fcla.edu/fcla/etd/SFE0001146.

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5

Gallagher, William Lynn. "Fault tolerant multipliers and dividers using time shared triple modular redundancy /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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6

Albandes, Iuri. "Use of Approximate Triple Modular Redundancy for Fault Tolerance in Digital Circuits." Doctoral thesis, Universidad de Alicante, 2018. http://hdl.handle.net/10045/88248.

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La triple redundancia modular (TMR) es una técnica bien conocida de mitigación de fallos que proporciona una alta protección frente a fallos únicos pero con un gran coste en términos de área y consumo de potencia. Por esta razón, la redundancia parcial se suele aplicar para aligerar estos sobrecostes. En este contexto, la TMR aproximada (ATMR), que consisten en la implementación de la redundancia triple con versiones aproximadas del circuito a proteger, ha surgido en los últimos años como una alternativa a la replicación parcial, con la ventaja de obtener mejores soluciones de compromiso entre

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7

Majewicz, Peter J. "Implementation of a Configurable Fault Tolerant Processor (CFTP) using Internal Triple Modular Redundancy (TMR)." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2005. http://library.nps.navy.mil/uhtbin/hyperion/05Dec%5FMajewicz.pdf.

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Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, December 2005.<br>Thesis Advisor(s): Herschel H Loomis, Jr., Alan A. Ross. Includes bibliographical references (p. 85). Also available online.

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8

Yuan, Rong. "Triple modular redundancy (TMR) in a configurable fault-tolerant processor (CFTP) for space applications." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2003. http://library.nps.navy.mil/uhtbin/hyperion-image/03Dec%5FYuan.pdf.

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Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, December 2003.<br>Thesis advisor(s): Herschel H. Loomis Jr., Alan A. Ross. Includes bibliographical references (p. 259). Also available online.

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9

Benites, Luis Alberto Contreras. "Automated design flow for applying triple modular redundancy in complex semi-custom digital integrated circuits." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2018. http://hdl.handle.net/10183/181177.

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Os efeitos de radiação têm sido um dos problemas mais sérios em aplicações militares e espaciais. Mas eles também são uma preocupação crescente em tecnologias modernas, mesmo para aplicações comerciais no nível do solo. A proteção dos circuitos integrados contra os efeitos da radiação podem ser obtidos através do uso de processos de fabricação aprimorados e de estratégias em diferentes estágios do projeto do circuito. A técnica de TMR é bem conhecida e amplamente empregada para mascarar falhas únicas sem detectálas. No entanto, o projeto de circuitos TMR não é automatizado por ferramentas EDA

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10

Cannon, Matthew Joel. "Improving the Single Event Effect Response of Triple Modular Redundancy on SRAM FPGAs Through Placement and Routing." BYU ScholarsArchive, 2019. https://scholarsarchive.byu.edu/etd/7551.

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Triple modular redundancy (TMR) with repair is commonly used to improve the reliability of systems. TMR is often employed for circuits implemented on field programmable gate arrays (FPGAs) to mitigate the radiation effects of single event upsets (SEUs). This has proven to be an effective technique by improving a circuit's sensitive cross-section by up to 100x. However, testing has shown that the improvement offered by TMR is limited by upsets in single configuration bits that cause TMR to fail.This work proposes a variety of mitigation techniques that improve the effectiveness of TMR on FPGAs.

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11

Swift, James D. "Root Cause Analysis and Classification of Single Point Failures in Designs Applying Triple Modular Redundancy in SRAM FPGAs." BYU ScholarsArchive, 2020. https://scholarsarchive.byu.edu/etd/8744.

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Radiation effects encountered in space or aviation environments can affect the configuration bits in Field Programmable Gate Arrays (FPGA) causing errors in FPGA output. One method of increasing FPGA reliability in radiation environments includes adding redundant logic to mask errors and allow time for repair. Despite the redundancy added with triple modular redundancy (TMR) and configuration scrubbing there exist some configuration bits that individually affect multiple TMR domains causing errors in FPGA output. A new tool called DeBit is introduced that identifies hardware resources associat

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12

Chenet, Cristiano Pegoraro. "Análise de soft errors em conversores analógico-digitais e mitigação utilizando redundância e diversidade." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/127693.

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Este trabalho aborda os soft errors em conversores de dados analógico-digitais e a mitigação usando redundância e diversidade. Nas tecnologias CMOS recentes, os efeitos singulares (SEEs, Single Event Effects) são um grupo de efeitos da radiação espacial que afetam a confiabilidade e disponibilidade dos sistemas. Os soft errors são SEEs que não danificam diretamente o sistema e podem ser posteriormente corrigidos. Seus principais subgrupos são o Single Event Upset (SEU), o Single Event Transient (SET) e o Single Event Functional Interrupt (SEFI). Uma das técnicas em nível de sistema amplamente

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13

Almeida, Antonio Felipe Costa de. "Investigating techniques to reduce soft error rate under single-event-induced charge sharing." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/169238.

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The interaction of radiation with integrated circuits can provoke transient faults due to the deposit of charge in sensitive nodes of transistors. Because of the decrease the size in the process technology, charge sharing between transistors placed close to each other has been more and more observed. This phenomenon can lead to multiple transient faults. Therefore, it is important to analyze the effect of multiple transient faults in integrated circuits and investigate mitigation techniques able to cope with multiple faults. This work investigates the effect known as single-event-induced charg

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14

Bilagi, Vedanth. "Experimental Study Of Fault Cones And Fault Aliasing." PDXScholar, 2012. https://pdxscholar.library.pdx.edu/open_access_etds/64.

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The test of digital integrated circuits compares the test pattern results for the device under test (DUT) to the expected test pattern results of a standard reference. The standard response is typically obtained from simulations. The test pattern and response are created and evaluated assuming ideal test conditions. The standard response is normally stored within automated test equipment (ATE). However the use of ATE is the major contributor to the test cost. This thesis explores an alternative strategy to the standard response. As an alternative to the stored standard response, the response i

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15

Pratt, Brian Hogan. "Analysis and Mitigation of SEU-induced Noise in FPGA-based DSP Systems." BYU ScholarsArchive, 2011. https://scholarsarchive.byu.edu/etd/2482.

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This dissertation studies the effects of radiation-induced single-event upsets (SEUs) on digital signal processing (DSP) systems designed for field-programmable gate arrays (FPGAs). It presents a novel method for evaluating the effects of radiation on DSP and digital communication systems. By using an application-specific measurement of performance in the presence of SEUs, this dissertation demonstrates that only 5-15% of SEUs affecting a communications receiver (i.e. 5-15% of sensitive SEUs) cause critical performance loss. It also reports that the most critical SEUs are those that affect the

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16

Li, Yubo. "Reliability Techniques for Data Communication and Storage in FPGA-Based Circuits." BYU ScholarsArchive, 2012. https://scholarsarchive.byu.edu/etd/3501.

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This dissertation studies the effects of radiation-induced single-event upsets (SEUs) on field-programmable gate array(FPGA)-based circuits. It analyzes and quantifies a special case in data communication, that is, the synchronization issue of signals when they are sent across clock domains in triple modular redundancy (TMR) circuits with the presence of SEUs. After demonstrating that synchronizing errors cannot be eliminated in such case, this dissertation continues to present novel synchronizer designs that can guarantee reliable synchronization of triplicated signals. Fault injection tests

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17

Aguilera, Carlos Julio González. "Avaliação de conversores AD sob efeitos de radiação e mitigação utilizando redundância com diversidade." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2018. http://hdl.handle.net/10183/179530.

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Este trabalho aborda um sistema de aquisição de dados (SAD) analógico-digital, baseado em um esquema redundante com diversidade de projeto, que é testado em dois ambientes diferentes de radiação. O primeiro experimento considera um teste de dose total ionizante (Total Ioninzig Dose - TID) sob irradiação gama, e o segundo experimento considera os efeitos de eventos singulares (Single Event Effects - SEE) sob irradiação por íons pesados. O SAD é composto, principalmente, por três conversores analógicos-digitais (ADCs) e dois votadores. A técnica usada é a Redundância Modular Tripla (Triple Modul

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18

Rowberry, Hayden Cole. "A Soft-Error Reliability Testing Platform for FPGA-Based Network Systems." BYU ScholarsArchive, 2019. https://scholarsarchive.byu.edu/etd/7739.

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FPGAs are frequently used in network systems to provide the performance and flexibility that is required of modern computer networks while allowing network vendors to bring products to market quickly. Like all electronic devices, FPGAs are vulnerable to ionizing radiation which can cause applications operating on an FPGA to fail. These low-level failures can have a wide range of negative effects on the performance of a network system. As computer networks play a larger role in modern society, it becomes increasingly important that these soft errors are addressed in the design of network system

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19

Keller, Andrew Mark. "Using On-Chip Error Detection to Estimate FPGA Design Sensitivity to Configuration Upsets." BYU ScholarsArchive, 2017. https://scholarsarchive.byu.edu/etd/6302.

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SRAM-based FPGAs provide valuable computation resources and reconfigurability; however, ionizing radiation can cause designs operating on these devices to fail. The sensitivity of an FPGA design to configuration upsets, or its SEU sensitivity, is an indication of a design's failure rate. SEU mitigation techniques can reduce the SEU sensitivity of FPGA designs in harsh radiation environments. The reliability benefits of these techniques must be determined before they can be used in mission-critical applications and can be determined by comparing the SEU sensitivity of an FPGA design with and wi

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20

Lynch, John Daniel. "Stochastic fault simulation of triple-modular redundant asynchronous pipeline circuits." Oregon Health & Science University, 2009. http://content.ohsu.edu/u?/etd,664.

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Ph.D.<br>Electrical Engineering<br>The expected unreliability of nano-scale electronic components has renewed interest in the decades-old field of fault-tolerant logic design. Fault-tolerant design makes it possible to build reliable systems from unreliable components. This has spurred recent research into the application of classical FT techniques to nanoelectronics. Meanwhile, the growing gap between logic gate and wire delays, and the growing power consumption of clock generation and distribution circuits, in nanometer-scale silicon integrated circuits has renewed research in asynchronous,

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21

Santos, André Flores dos. "Análise do uso de redundância em circuitos gerados por síntese de alto nível para FPGA programado por SRAM sob falhas transientes." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2017. http://hdl.handle.net/10183/178392.

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Este trabalho consiste no estudo e análise da suscetibilidade a efeitos da radiação em projetos de circuitos gerados por ferramenta de Síntese de Alto Nível para FPGAs (Field Programmable Gate Array), ou seja, circuitos programáveis e sistemas em chip, do inglês System-on-Chip (SOC). Através de um injetor de falhas por emulação usando o ICAP (Internal Configuration Access Port) localizado dentro do FPGA é possível injetar falhas simples ou acumuladas do tipo SEU (Single Event Upset), definidas como perturbações que podem afetar o funcionamento correto do dispositivo através da inversão de um b

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22

Lin, Pin Hsi, and 林品希. "Hardware-Efficient Triple-Modular-Redundancy Soft-Error-Tolerant Arithmetic Circuit Architecture Design." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/4ta3yt.

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23

Chiu, Chin-Yang, and 邱錦洋. "Adaptive Triple Modular Redundancy Technique for Reliability Enhancement of Phase Change Memory." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/tqfmhr.

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碩士<br>國立臺灣科技大學<br>電機工程系<br>106<br>Due to the rapid development of technology, it has brought more convenient life to human beings. For example, consumer electronics products have entered the daily life of human beings and are everywhere. The continuous evolution of the generations, the storage of data has always been a very important link, so the human demand for storage devices has gradually increased with the evolution of the generation. Among them, phase change memory is regarded as one of the mainstream memory candidates of the next generation. It has many advantages, such as non-volatilit

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24

"Stochastic fault simulation of triple-modular redundant asynchronous pipeline circuits." Oregon Health & Science University, 2009. http://content.ohsu.edu/u?/etd,664.

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