Dissertations / Theses on the topic 'Turbo decoder'

Since its introduction in 1993, the turbo coding error-correction technique has generated a tremendous interest due to its near Shannon-limit performance. Two key innovations of turbo codes are parallel concatenated encoding and iterative decoding. In its IMT-2000 initiative, the International Telecommunication Union (ITU) adopted turbo coding as a channel coding standard for Third-Generation (3G) wireless high-speed (up to 2 Mbps) data services (cdma2000 in North America and W-CDMA in Japan and Europe). For battery-powered hand-held wireless terminals, energy consumption is a major concern. In this thesis, a new design for an energy-efficient turbo decoder that is suitable for 3G wireless high-speed data terminals is proposed. The Log-MAP decoding algorithm is selected for implementation of the constituent Soft-Input/Soft-Output (SISO) decoder; the algorithm is approximated by a fixed-point representation that achieves the best performance/complexity tradeoff. To attain energy reduction, a two-stage design approach is adopted. First, a novel dynamic-iterative technique that is appropriate for both good and poor channel conditions is proposed, and then applied to reduce energy consumption of the turbo decoder. Second, a combination of architectural-level techniques is applied to obtain further energy reduction; these techniques also enhance throughput of the turbo decoder and are area-efficient. The turbo decoder design is coded in the VHDL hardware description language, and then synthesized and mapped to a 0. 18μm CMOS technology using the standard-cell approach. The designed turbo decoder has a maximum data rate of 5 Mb/s (at an upper limit of five iterations) and is 3G-compatible. Results show that the adopted two-stage design approach reduces energy consumption of the turbo decoder by about 65%. A prototype for the new turbo codec (encoder/decoder) system is implemented on a Xilinx XC2V6000 FPGA chip; then the FPGA is tested using the CMC Rapid Prototyping Platform (RPP). The test proves correct functionality of the turbo codec implementation, and hence feasibility of the proposed turbo decoder design.

A new coding scheme called "turbo coding" has generated tremendous interest in channel coding of digital communication systems due to its high error correcting capability. Two key innovations in turbo coding are parallel concatenated encoding and iterative decoding. A soft-in soft-out component decoder can be implemented using the maximum a posteriori (MAP) or the maximum likelihood (ML) decoding algorithm. While the MAP algorithm offers better performance than the ML algorithm, the computation is complex and not suitable for hardware implementation. The log-MAP algorithm, which performs necessary computations in the logarithm domain, greatly reduces hardware complexity. With the proliferation of the battery powered devices, power dissipation, along with speed and area, is a major concern in VLSI design. In this thesis, we investigated a low-power design of a turbo decoder based on the log-MAP algorithm. Our turbo decoder has two component log-MAP decoders, which perform the decoding process alternatively. Two major ideas for low-power design are employment of a variable number of iterations during the decoding process and shutdown of inactive component decoders. The number of iterations during decoding is determined dynamically according to the channel condition to save power. When a component decoder is inactive, the clocks and spurious inputs to the decoder are blocked to reduce power dissipation. We followed the standard cell design approach to design the proposed turbo decoder. The decoder was described in VHDL, and then synthesized to measure the performance of the circuit in area, speed and power. Our decoder achieves good performance in terms of bit error rate. The two proposed methods significantly reduce power dissipation and energy consumption.
Master of Science

The aim is to explain the Turbo convolutional and block turbo codes and decoding the secure message. The practical part focuses on the design of a demonstration program in Matlab. The work is divided into four parts. The first two deal with theoretical analysis of coding and decoding. The third section contains a description created a demonstration program that allows you to navigate the process of encoding and decoding. The fourth is devoted to simulation and performance of turbo codes.

Turbo codes was first presented in 1993 by C. Berrou, A. Glavieux and P. Thitimajshima. Since then this class of error correcting codes has become one of the most popular, because of its good properties. The turbo codes are able to come very close to theoretical limit, the Shannon limit. Turbo codes are for example used in the third generation of mobile phone (3G) and in the standard IEEE 802.16 (WiMAX).

There are some drawbacks with the algorithm for decoding turbo codes. The deocoder uses a Maximum A Posteriori (MAP) algorithm, which is a complex algorith. Because of the use of many variables in the decoder the decoding circuit will consume a lot of power due to memory accesses and internal communication. One way in which this can be reduced is to make early decisions.

In this work I have focused on making early decision of the encoder states. One major part of the work was also to be sure that the expressions were written in a way that as few variables as possible are needed. A termination condition is also introduced. Simulations based on estimations of the number of memory accesses, shows that the number of memory accesses will significantly decrease.

One technique that is used to reduce the errors brought upon signals, when transmitted over noisy channels, is error control coding. One type of such coding, which has a good performance, is turbo coding. In some of the TMS320C64xTM digital signal processors there is a built in coprocessor that performs turbo decoding. This thesis is performed on the account of Communication Developments, within Saab AB and presents an evaluation of this coprocessor. The evaluation deals with both the memory consumption as well as the data rate. The result is also compared to an implementation of turbo coding that does not use the coprocessor.
En teknik som används för att minska de fel som en signal utsätts för vid transmission över en brusig kanal är felrättande kodning. Ett exempel på sådan kodning som ger ett mycket bra resultat är turbokodning. I några digitalsignalprocessorer, av sorten TMS320C64xTM, finns en inbyggd coprocessor som utför turboavkodning. Denna uppsats är utförd åt Communication Development inom Saab AB och presenterar en utvärdering av denna coprocessor. Utvärderingen avser såväl minnesförbrukning som datatakt och innehåller även en jämförelse med en implementering av turbokodning utan att använda coprocessorn.

Turbo codes are a new class of codes that can achieve exceptional error performance and energy efficiency at low signal-to-noise ratios. Decoding turbo codes is a complicated procedure that often requires custom hardware if it is to be performed at acceptable speeds. Configurable computing machines are able to provide the performance advantages of custom hardware while maintaining the flexibility of general-purpose microprocessors and DSPs. This thesis presents an implementation of a turbo decoder on an FPGA-based configurable computing platform. Portability and flexibility are emphasized in the implementation so that the decoder can be used as part of a configurable software radio. The system presented performs turbo decoding for a variable block size with a variable number of decoding iterations while using only a single FPGA. When six iterations are performed, the decoder operates at an information bit rate greater than 32 kbps.
Master of Science

This thesis presents high performance turbo decoder architecture for VLSI implementation in terms of area, power and critical path delay. A Max-Log-MAP (MLMAP) algorithm is used to implement the turbo decoder with sliding window (SW) method to reduce the latency. Low power and area efficient turbo decoder implementation is achieved by reducing memory blocks required to control the SW method and to store the branch metrics used for computing log-likelihood-ratio (LLR). Retiming and reordering method is applied to implementing the units needed to calculate the LLR and the state metrics, to save hardware costs. A novel method is proposed to achieve high speed turbo decoder implementation for high throughput without significant area and power overheads. The proposed method addresses the inherent critical path delay problem in the state metric computation process by normalising the branch metrics. A two-step soft-output Viterbi algorithm (TSOVA) based turbo decoder is implemented exploiting a novel concept for implementing a traceback algorithm (TBA) to achieve low area and power turbo decoder implementations as compared to the MLMAP turbo decoder without any significant BER performance degradation. Two reconfigurable application specific turbo decoders are implemented to support variable constraint length and binary and duo-binary turbo codes for targeting various wireless communication systems. The reconfigurable turbo decoder architectures are realised by a proposed mapping method applied to the process for computing the state metrics and the LLR values. It is found that radix-4 based turbo decoder architecture can be exploited to implement the reconfigurable turbo decoder for binary and duo-binary turbo codes.

This Diploma thesis aims to explain the data coding using turbo codes. These codes belong to the group of error correction codes. We can reach the high efficiency using these codes. The first part describes process of encoding and decoding. There are describes parts of encoder and decoder. Principle of encoding and decoding demonstrate a simple example. The end of this part contains description of two most frequently used decoding algorithms (SOVA and MAP). The second part contains description of computer program that was made for using as teaching aid. This program was created in Matlab GUI. This program enables to browse error correction process step by step. This program contains graphic interface with many options and display results. In the third part is described program created in Matlab Simulink that was implemented into the TMS320C6713 kit and there is description of measuring procedure. For verification of efficiency of turbo codes was measured any parameters. Some of these parameters are: number of decoding iterations, generating polynoms and using of puncturing. The last part contains measured value and result evaluation.

Turbo codes are a recently discovered class of error correction codes that achieve near-Shannon limit performance. Because of their complexity and highly parallel nature, turbo-coded applications are well suited for configurable computing. Field-programmable gate arrays (FPGAs), which are the main building blocks of configurable computing machines (CCMs), allow users to design flexible hardware that is optimized for performance, speed, power consumption, and chip-area. This thesis presents the implementation and performance of an improved turbo decoder on a configurable computing platform. The design's performance and throughput are emphasized in light of its algorithmic improvements, and its flexibility is emphasized as it is ported to a newer, more efficient architecture with more hardware resources. Because this decoder will eventually become the error correction component of a software radio, the design must maintain a high data rate, interface easily with other modules, and conserve hardware resources for future research developments.
Master of Science

Recent years have seen a huge evolution of wireless communication standards in the domains of mobile phone, local and wide area networks and video broadcasting. These evolutions aim at increasing the requirements in terms of throughput, robustness against destructive channel effects and convergence of services in a smart terminal. As an example, the fourth generation (4G) of cellular wireless standards aims at providing mobile broadband solution to laptop computer wireless modems, smartphones, and other mobile devices. Diverse features such as ultra-broadband Internet access, IP telephony, gaming services, and streamed multimedia are provided. In order to enable such advanced services at the algorithmic level, new state of the art data processing techniques have been developed and adopted in the emerging wireless communication standards. At the architecture level, many efforts are being conducted towards the design of flexible high throughput hardware platforms which can be configured to the required configuration. In order to reach high flexibility, the I. A. S. (Algorithm Silicon Interaction) team of the Lab-STICC laboratory has developed an Application Specific Instruction Set Processor (ASIP) based multi-standard multiprocessor Turbo decoder. This architecture is based on the DecASIP processor. Previous work provides an efficient way to reach the high performance and high flexibility requirements of emergent standards. However, dynamic reconfiguration aspect of the architecture has not been addressed. In this context, this Ph. D work targets the development of a dynamically reconfigurable multiprocessor Turbo decoder for future communication standards. For that purpose, this thesis work is divided in several steps. The first step consists on the study of the initial processor architecture in order to propose optimizations in a multiprocessor context. This step leads to a new implementation of the DecASIP processor integrating a new configuration memory organization in order to reduce the configuration transfer latency. The second step leads to the development of a configuration infrastructure allowing an efficient and high speed configuration transfer for the ASIPs and the controller of the platform. The proposed approach is based on a low complexity unidirectional pipeline bus implementing optimized transfer mechanisms such as multicast and broadcast. This configuration infrastructure provides an efficient solution in order to transfer an entire configuration for 128 processors in less than one microsecond. Finally, the last step of this thesis work concerns the development of a configuration management of the proposed platform in order to adapt the configuration parameters regarding the environment evolution and the application requirements. This step leads on an approach allowing the support of dynamic configuration of the platform in the context of highly constrained scenario in terms of throughput and error rate performances where each frame or group of frames is associated to a specific configuration. This thesis work will allow the laboratory to present a prototype of a dynamically reconfigurable Turbo decoder respecting future communication standards requirements in terms of flexibility, throughput and error rate performances. Such a contribution gathers the skills present in the Lab-STICC laboratory at the decoding algorithm, multiprocessor architecture, dynamic reconfiguration and self-adaptation levels in a single prototype
Les travaux de thèse présentés dans ce manuscrit s'inscrivent dans le cadre de la conception des systèmes de communication sans fils. En effet, depuis plusieurs années, les standards de communication dans le domaine des réseaux téléphoniques mobiles, des réseaux sans fils locaux et étendus ainsi que des réseaux de diffusion de vidéo numériques ont fortement évolués. Ces évolutions ont notamment imposé une augmentation significative du débit et de la robustesse des communications vis à vis des effets de l'environnement sur les canaux de communication. Face aux nombreux standards devant être gérés par les appareils mobiles, la convergence des services au sein des terminaux devient un enjeu crucial. Par exemple, la 4ème génération (4G) de standards pour la communication sans fils à haut débit a pour objectif de fournir des solutions pour les modems d'ordinateurs portables, les smartphones, ainsi que tout autre appareil mobile communicant. Diverses fonctions comme l'accès internet haut débit, la téléphonie sur IP, les jeux en ligne, et le multimédia en streaming seront alors disponibles. De nouveaux algorithmes ont ainsi été développés et validés afin de permettre la mise en œuvre de ces nouveaux services en vue de leur intégration dans les standards de communication sans fils émergents. Au niveau architectural, de nombreux efforts ont également été fournis pour réaliser de nouvelles plateformes offrant des débits importants et une grande flexibilité permettant notamment une configuration dynamique de la plateforme afin de s’adapter aux conditions d'exécution et à la demande des utilisateurs. Pour atteindre ce niveau de performance et de flexibilité, l'équipe I. A. S (Interaction Algorithme Silicium) du laboratoire Lab-STICC a développé un Turbo-décodeur multistandard et multiprocesseur à base de processeurs ASIP (Application Specific Instruction Set Processor) nommé DecASIP. Ces précédents travaux ont démontré l'intérêt de l'utilisation d'une architecture multiprocesseur pour atteindre un haut degré de performance et de flexibilité. Toutefois, l'aspect reconfiguration dynamique de la plateforme n'avait pas été abordé. Ces travaux de thèse s'articulent donc autour de cette plateforme et ont pour but de développer un récepteur multistandard dynamiquement reconfigurable pour les futurs standards de communication. Ces travaux sont divisés en plusieurs étapes afin d'atteindre cet objectif. La première étape a été l'étude du processeur DecASIP afin d'optimiser sa conception dans le cadre d'un système multiprocesseur reconfigurable. Cette étape a donné lieu à une nouvelle spécification intégrant une réorganisation du stockage des paramètres de configuration. Cette première contribution a permis d'optimiser les performances de reconfiguration du DecASIP. Une nouvelle implémentation du DecASIP optimisé a également été proposée. La seconde étape a eu pour but de définir une infrastructure de communication dédiée à la reconfiguration. Cette deuxième contribution a permis d'optimiser le chargement des nouvelles configurations et le contrôle des DecASIP. Pour cela, une approche basée sur une architecture de bus unidirectionnel pipeliné de faible complexité et offrant des mécanismes de multicast et de broadcast a été proposée. Cette solution permet le transfert d'une configuration pour 128 processeurs avec une latence inférieur à la microseconde. Enfin, la dernière étape des travaux de thèse a été l'étude d'une politique de management de la plateforme afin d'adapter ses paramètres en fonction des données recueillis sur l'environnement et sur l'application exécutée. Cette dernière contribution a abouti au développement d'une approche permettant de supporter la reconfiguration dynamique de la plateforme dans le cas de scénarios à fortes contraintes de débits et de taux d'erreur binaire où chaque trame ou groupe de trames de données est associé à une configuration particulière. Les résultats de ces travaux permettront au laboratoire de proposer un démonstrateur de Turbo-décodeur dynamiquement reconfigurable respectant les besoins des futurs standards de communication en termes de débit, de correction d'erreurs, et de flexibilité. Un tel démonstrateur permettra de tirer profit du savoir-faire du Lab-STICC au niveau des algorithmes de décodage, des architectures multiprocesseurs, de la reconfiguration dynamique et de l'auto-adaptation

This thesis concentrates on the analysis of the sphere decoder (SD) for MIMO detection. It provides optimal maximum likelihood (ML) performance with reduced complexity compared to the maximum likelihood detector (MLD). However, a field-programmable gate array (FPGA) implementation of the algorithm presents several disadvantages due to its variable complexity and the sequential nature of its tree search. This research proposes a fixed-complexity sphere decoder (FSD) to overcome the drawbacks of the SD. It provides a fixed complexity and achieves quasi-maximum likelihood (ML) performance, combining a search through a small subset of the transmitted constellation with a novel channel matrix ordering. This represents a novel approach compared to most optimizations of the SD in the literature, which concentrate on reducing the average complexity of the algorithm. As a result, an implementation of the FSD is shown to provide the same error performance using less FPGA resources and achieving a considerably higher (and constant) throughput compared to previous SD hardware implementations. The same FSD concept is applied to a large MIMO system with 4 antennas at both ends of the link and 64-quadrature amplitude modulation (QAM). A list extension of the FSD (LFSD) combines the same channel matrix ordering and an extended fixed search to generate a list of candidates for short-value calculation. Depending on the size of the extended search, different levels of performance and complexity can be achieved making the algorithm suitable for reconfigurable architectures. Its FPGA implementation shows how soft-value information can be obtained with a fully pipelined architecture. It provides a constant throughput which is considerably higher than previously presented soft-MIMO detector implementations.

As the demands of communication systems have become more complex and varied, software defined radios (SDR) have become increasingly popular. With behavior that can be modified in software, SDR's provide a highly flexible and configurable development environment. Despite its programmable behavior, the maximum performance of an SDR is still rooted in its hardware. This limitation and the desire for the use of SDRs in different applications have led to the rise of various pieces of hardware to serve as SDR platforms. These platforms vary in aspects such as their performance limitations, implementation details, and cost. In this way the choice of SDR platform is not solely based on the cost of the hardware and should be closely examined before making a final decision. This thesis examines the various SDR platform families available on the market today and compares the advantages and disadvantages present for each during development. As many different types of hardware can be considered an option to successfully implement an SDR, this thesis specifically focuses on general purpose processors, system on chip, and field-programmable gate array implementations. When examining these SDR families, the Freescale BSC9131 is chosen to represent the system on chip implementation, while the Nutaq PicoSDR 2x2 Embedded with Virtex6 SX315 is used for the remaining two options. In order to test each of these platforms, a Viterbi algorithm is implemented on each and the performance measured. This performance measurement considers both how quickly the platform is able to perform the decoding, as well as its bit error rate performance in order to ascertain the implementations' accuracy. Other factors considered when comparing each platform are its flexibility and the amount of options available for development. After testing, the details of each implementation are discussed and guidelines for choosing a platform are suggested.

碩士
國立臺灣大學
電子工程學研究所
100
The next-generation communication system, long term evolution (LTE), is currently the most popular mobile wireless technology in the market. LTE allows wireless service providers to improve the economics of deploying mobile broadband networks. The performance of LTE is better than the today’s 3G or 3.5G wireless network. LTE has already been the new standard of a next-generation communication system announced by the third generation partnership project (3GPP). Compared to the 3G and 3.5G communication systems, the obvious advantage of LTE is its high data rate. In order to provide high data rate transmission, a parallelized architecture of channel decoder is needed for hardware implementation. However, a highly parallelized architecture will require large power consumption and chip area. So we will use some low power architectures to reduce the memory usage for having a smaller chip area and consuming lower power. Besides, we also use the hardware reused technique to increase the area efficiency. According to the ideas above, we propose a dual mode Viterbi/turbo- code decoder to reduce the power dissipation and area. In this Thesis, we will introduce the channel coding in a communication system briefly first. Then, we explain the decoding algorithms for the convolutional code and turbo-code. And the proposed low power architecture and hardware sharing are described. Finally, the implementation flow and result are depicted.

碩士
國立清華大學
電機工程學系
97
For the 3rd Generation Partnership Project(3GPP) specification, the turbo code is applied in the transmitted data because the data needs a better error correction capability. With the increase of the utilization of the turbo decoder in the next generation system, decoding speed for the MAP decoder has become more and more critical. Hence, the target of this thesis is to design a high throughput MAP decoder for the turbo decoder. We propose a radix-16 MAP algorithm to reduce the decoding cycle, and a modified term method to improve the decoding performance. Then, we propose a separate-CS architecture which can operate sixteen inputs simultaneously to reduce the latency of the MAP decoder, and a cut-bank-jump-permute method for the interleaver memory to solve the collision problem. Finally, we implement the proposed high-radix modified log-MAP decoder. The throughput of the proposed decoder is 393Mb/s which is better than some references. Moreover, the proposed decoder can combine the other techniques even to increase the throughput in the same performance.

碩士
國立中央大學
電機工程研究所
90
Turbo codes, proposed by Berrou et al. in 1993, which are parallel concatenated convolution codes joined through interleavers. Iterative decoding techniques are used for decoding. It has been shown that any decoder that accepts soft inputs (include a priori values) and generates soft outputs can be used for iterative decoding. Turbo code can achieve almost near Shannon limit error correction performance, its powerful error correcting capability is very attractive for mobile wireless applications to combat channel fading. Turbo code has been adopted as the channel coding schemes for the services of high transmission rates in a number of the 3rd generation mobile systems (3GPP), such as WCDMA and CDMA2000. In this thesis, we focus on the realization of the soft-input and soft-output comment decoder. The operating algorithm of Turbo code decoder is much complicated than the conventional convolutional decoder, and there are several implementation issues. There are several algorithms that meet the requirements of the soft-input and soft-output structure. A Soft-Output Viterbi Algorithm (SOVA) proposed by Hagenauer is used to implement the soft-input and soft-output convolutional decoder. In realization, we first discuss the proposed architecture and the implementation issues. Then, the encoding/decoding process is simulated by Matlab program and verified by Verilog HDL. Finally, the architecture of the SOVA decoder is then mapped on circuit design, and the layout implementation is made by using TSMC standard cell and 0.35μm TSMC CMOS SPDM technology.

碩士
國立中山大學
資訊工程學系研究所
92
Turbo Code, due to its excellent error correction capability, has been widely used in many modern wireless digital communication systems as well as data storage systems in recent years. However, because the decoding of the Turbo Code involves finding all the state probability and transition sequence, its hardware implementation is not straightforward as it requires a lot of memory and memory operation. In this thesis, a design of Turbo Code decoder IP (Intellectual Property) is proposed which can be parameterized with different word-lengths and code rates. The design of the core SISO (Soft-In Soft-Out) unit used in Turbo Code decoder is based on the algorithm of SOVA (Soft-Output Viterbi Algorithm). Based on the hybrid trace-back scheme, the SISO proposed in this thesis can achieve fast path searching and path memory reduction which can be up to 70% compared with the traditional trace-back approach. In addition, every iterative of Turbo Code decoding performs two SISO operations on the block of data with normal and interleaving order. In our proposed architecture, these two SISO operations can be implemented on a single SISO unit with only slightly control overhead. In order to improve the bit error rate performance, the threshold and normalization techniques are applied to our design. In addition, the termination criteria circuit is also included in our design such that the iteration cycle of the decoding can be reduced. The proposed Turbo Code decoder has been thoroughly tested and verified, and can be qualified as a robust IP.

碩士
國立交通大學
電機與控制工程系所
97
Turbo code has been widely used in communication systems, because of its outstanding error correction performance. To increase throughput and decrease the required memory. Radix-4 architecture for Turbo decoder was studied. However, the critical path of the recursive architecture in Radix-4 turbo decoder is long, As a result conventional Radix-4 architecture [15] cannot achieve twice throughput over the conventional Radix-2 architecture. In this thesis, we proposed a Look-Up Table scheme for the recursive architecture and the throughput increases up to 62%. The performance of the proposed scheme is worse than the Log-MAP (optimal) by only 0.025dB. In VLSI implementation, we propose a method for input buffer and it can reduce the dual-RAM by the single-RAM to save area and power. The proposed method can reduce the area by 57.8% and the power by 71.83%. The chip is fabricated in TSMC 0.18 μm CMOS process, operating at 167MHz clock rate with voltage supply 1.62V. The power consumption is 135mW at decoding rate 22Mb/s, with code rate 1/3 for 3GPP standard. The core area is 2.65 mm², contain 200K gate counts.

碩士
國立中正大學
通訊工程研究所
97
The Raptor codes – the best approximation to a digital fountain. These codes are rateless. We use IRA code for pre-coder of Raptor code for encoder, and use the turbo-like structure to our joint Raptor decoder. The turbo-like structure is 2-stage BP algorithm cascade structure. Two decoders exchange the soft information each iteration, which is similar to the series-turbo code. We also design the IRA permutation to help us find out the permutation matrix more efficient. Extending recent works on distributed source coding, this paper considers distributed source coding. The idea is to use two source of dependent encoder (via Slepian-Wolf coding). These codes integrated in the Distributed source coding (DSC) will have better performance in BER for AWGN channel.

碩士
國立交通大學
電信工程系所
97
In this thesis, a contention free algorithm for solving memory collision problem of parallel Turbo decoder architecture using the simulated annealing algorithm is presented. Furthermore, we proposed two area-efficient extrinsic memory schemes based on the parallel contention free Turbo decoder. One of the proposed schemes employs only multiple single port memories with one temporary buffer instead of the original dual port or two port memories. And the other scheme further employs an additional non-linear extrinsic mapping architecture. The proposed schemes lead to approximately 37% and 46% memory area reduction, respectively, for 16-parallel Turbo decoder in comparison to the conventional dual port memory scheme under the UMC 0.13-μm CMOS process.

碩士
國立臺北科技大學
電腦與通訊研究所
93
In communication system, turbo decoder is widely used nowaday. However, the specifications of turbo decoders are difference in various communication applications. It will cost lot of time and labor to design turbo decoder with traditional methods, which does not meet Time to Market requirement. In this thesis, we propose a De-interleaver free table turbo decoder SIP generator. This IP generator not only provides IC designer to generate a turbo decoder with configurable parameter but also the automatic performance simulation which produces the SNR and BER relation charts for IC designers to evaluate the error correction efficiency. Moreover, we analyzed the characteristics of interleaver and de-interleaver then re-arranged the extrinsic memory access order; thus only one interleaver table is needed to perform the function of interleaver and de-interleaver. This new architecture effectively reduces the extrinsic memory to half and shrinks the chip area and lowers the power consumption. Finally as to verify our SIP generator, we have synthesized the turbo decoder chips which consist 1, 2, and 4 parallel MAP decoders by TSMC 0.18 1p6m process, and also performed efficiency analysis. The experimental results show that the memory area is reduced by 9.5%~15.6% and power consumption by 5.7%~11.11% without degrading the decoding speed.

碩士
國立臺北科技大學
電腦與通訊研究所
94
Turbo code is a forward error correct code which has good error correction capability and near Shannon limiting performance. Traditional turbo decoder needs large memory size and has long decoding latency for implementation. This paper presents a dummy-beta-latency-free algorithm which can reduce the decoding latency of sliding window from 4L to 1L. In hardware implementation, we can use a dummy-beta memory unit to replace one backward calculation unit and two SISO sub-memories. Experimental results show that our architecture can save 27%~45% memory bit and 65%~68% memory area. Then, we have verified this algorithm using Xilinx FPGA (HW-V4-ML402-USA) system. Finally, a dummy-beta-latency-free turbo decoder is designed using TSMC 0.18μm 1P6M CMOS technology. The chip occupies 1.9mm 1.9mm and has a clock frequency of 104.1Mbps.

碩士
國立中央大學
通訊工程學系
106
In the LTE uplink, tail biting convolutional coding and trubo coding are used in the channel coding, this paper follow 3GPP TS 36.212 to design turbo code decoder. We separate this paper into two parts. In first part, the algorithm which is used in the decoder will be introduced. The maximum a posterior probability (MAP) algorithm is too complex for the hardware, so the Max-Log-MAP algorithm which is next only to MAP is used. We use AWGN(Additive white Gaussian noise) channel as the simulation environment, and follow the algorithm simulation to decide the fixed-point. The second part, we follow the result of simulation and the trubo code encoder which provided from 3GPP TS 36.212 to design the turbo code decoder. Then, we use the parallel architecture to improve the throughput and implement on the FPGA to verification. Finally, we observe the performance after implementation

碩士
國立雲林科技大學
電機工程系碩士班
93
Turbo code, which has closely approached the Shannon Limit Theorem, was first proposed by Berrou, Glavieux and Thitimajashima in 1993. Because the turbo code exhibits very small average probability of error at low signal-to-noise ratio, it has attracted a lot of research interest and has been widely applied to many wireless communication systems. In this thesis, we mainly focus on the investigation of the S-random interleaver in a turbo code. The major drawback of the traditional S-random interleaver is its slow generation of the interleaved sequence. A novel approach that can effectively raise about 94 % ~ 95 % (compare with trade S random interleaver) the generation speed is proposed in this thesis. Several types of interleavers are examined and the comparisons on their generation time as well as the corresponding bit error rate performance of the system are also proposed. In the latter part of this thesis, we propose a new decoding structure to lower down the computational burden of the system. The proposed structure has successfully saved the chip area by about 9.3%, and also has increased the processing speed by about 3.3%. The hardware structure has been verified on Altera Quartus II.

碩士
國立臺北科技大學
電腦與通訊研究所
98
In this thesis, we proposed a novel parallel phase turbo decoding algorithm for VLSI architecture. Traditional sliding window turbo algorithm exchanges extrinsic information phase by phase, it will induce a long decoding latency. The proposed algorithm exchanges extrinsic information as soon as it had been calculated half the frame size, thus, it can not only eliminate (De-)Interleaver delay but also save the storage space. Besides, we modify the received data RAM to reduce the decoding time. By using this method, the decoder can reduce half frame decoding latency. To verify the function of the proposed parallel phase turbo decoder, we have used Xilinx Virtex-5 FPGA to emulate the hardware architectures, and we have designed this turbo decoder chip with TSMC 0.18μm 1P6M CMOS process. The gate counts of this decoder chip are 128284. The chip size including I/O pad is 1.91×1.91mm2, and power consumption is 151.76mW. The simulation results show that, compared to traditional sliding window method, for different code size, parallel phase turbo decoding method has 51.29% ~ 58.63% decoding time saved, with 8 iteration times at 100MHz working frequency.

碩士
國立臺北科技大學
電腦與通訊研究所
99
Turbo codes use an iterative algorithm that allows the BER performance to achieve the Shannon limit to carry out decoding. Relative literatures and developments have been researched over decades. One of the requirements of communication standard is throughput which can be satisfied by using parallel or high radix architecture. However, both methods would cause the degradation of the BER performance because they shorten the interleaver length. Hence, we propose a dual phase decoding architecture for two SISO decoders based on different decoding phase. Compared with traditional parallel turbo decoder, the BER performance can improve about 0.2 dB. Experimental results show that our chip can decrease 17% chip area and can reduce power consumption effectively. Also emulation of the Xilinx Virtex-5 FPGA board shows that our turbo decoder can achieve 7.5 Mb/s throughput while operating at 100 MHz, and only consumes 255 mW. We also use TSMC 0.18 μm 1P6M CMOS technology to synthesis and layout our turbo decoder, the decoder chip size including pads is 3.03 mm2 with 130k gate counts.

碩士
長庚大學
電機工程學系
98
This thesis proposes extrinsic-information-based decoding algorithms for original block turbo codes (BTCs) and hybrid block turbo codes. Since the number of algebraic decodings dominates the complexity of BTC decoding, it is important for BTC research to reduce the number of algebraic decodings without noticeable loss of bit-error rate performance. In each iterative decoding process, the algorithm compares the extrinsic information of the mth iteration and the (m-1)th iteration to determine when the HIHO decoding starts. Additionally, in BTC decoding, the decoder can use the other proposed algorithm to determine the rows/columns that are decoded using HIHO decoding to achieve the reduction of the number of algebraic decodings.

碩士
明志科技大學
機電工程研究所
96
In recent years, considerable interest has been devoted to turbo codes that achieve near-Shannon limit performance. At the receiver, decoding can be done in an iterative way either using the maximum a-posteriori (MAP) algorithm or the soft-output Viterbi algorithm (SOVA). The SOVA is less complex, but has a performance degradation of about 0.7 dB compared to the MAP. Instead of using the MAP algorithm, decoding turbo codes with the max-log-MAP algorithm is a good compromise between performance and complexity. However, it has been found that the output information produced by a turbo decoder does not correctly predict the a posteriori probability (APP) of the hard decision for bad channels. In fact, the output information is too optimistic, and thus a correction of the output information is necessary. To compensate for this, in this thesis we try to explore the feasibility of developing a novel soft-output normalization scheme that extends the existing hard decision aided (HDA) techniques to scale the associated output information of a tturbo decoder. It is expected that the proposed novel soft-output normalization scheme integrating with the associated stopping mechanism will be effective not only in reducing the decoding latency time but also in achieving lower bit error rates (BERs) and frame error rates (FERs) when compared to a conventional turbo decoder with or without a previously proposed normalization scheme under various noisy conditions. The performance of the proposed novel soft-output normalization scheme integrating with the associated stopping mechanism has been evaluated by software simulation on a personal computer. Simulations comparing the new scheme with other well-known normalization techniques show that the proposed normalization scheme can achieve about 0.2 dB coding gain improvement on average while reducing up to about iteration for decoding.

碩士
國立臺北科技大學
電腦通訊與控制研究所
92
Excellent error correction capability and near Shannon limiting performance make turbo code to be the most important error correcting code recently. However, turbo decoder uses enormous calculations and iterations, which is difficult to be implemented and has a long decoding latency. In this thesis, we focus on turbo code algorithms and develop a new VLSI architecture for high-speed turbo decoder. Firstly, we have proposed a new low-latency-normalization method in our design, which can speed up the decoder throughput about 18%~34% and reduce chip area of state metric memory (SMM) about 13% in comparison with others. Secondly, we have also proposed an extendable parallel turbo decoder architecture that can raise the decoding speed efficiently and is very suitable for high-speed decoding applications. For demonstrating the architecture of our extendable parallel turbo decoder, we have designed a four-parallel turbo decoder with TSMC 2P4M technology. This decoder occupies chip area, consumes 353mW, supports a 129Mbps data rate and retains BER lower than 10-6 for SNR=2dB with four iterations.

碩士
國立清華大學
電機工程學系
91
Turbo codes, due to its excellent capability of maintaining low bit error rate (BER) under high transmission speed and low SNR environment, are adopted in various 3GPP standards for mobile communication systems, such as CDMA 2000, WCDMA, .., etc. Recently, many research efforts have been directed toward developing efficient algorithms, architectures, and VLSI circuits for implementing the much more complicated turbo code decoder. Among many decoding algorithms, the MAP (maximum a posteriori probability) algorithm is the one with the lowest bit-error-rate and also the highest complexity. In this thesis, the focus is on the design and implementation of a high efficient MAP-based turbo decoder. All the designs have been verified using simulation as well as FPGA implementation on Altera Flex 10K100 and EP20K1000E. The main contributions of the thesis can be divided into three parts: 1. Several VLSI MAP decoder architectures with different operation control and data flow together with techniques for improving decoder circuit efficiency are proposed and analyzed. A comparison of their throughput (decoding speed) and cost (circuit area and memory usage) indicates that the proposed Two-Beta architecture has the fastest decoding speed of exceeding 4.5 Mbps and reasonable cost. 2. The relation between some parameters in the MAP algorithm, such as correcting methods of max* operation and noise variance, and BER of decoding are also analyzed with extensive simulations. Trade-offs between the circuit cost, speed, and BER can be made based on these simulation results. 3. A novel design of deinterleaver circuit is also proposed which can drastically reduce the memory usage and hence save VLSI chip area.

碩士
國立臺北科技大學
電腦與通訊研究所
96
In this thesis, we present two low latency decoding methods for VLSI Turbo decoder. In our design, we propose a novel sliding window operating flow, called Decoding Phase Overlapping method. It can improve the hardware efficiency and reduce the decoding delay of Turbo decoder. With this improved methodology, we have four decoding windows latency can be saved in comparison with traditional decoders. Besides, we also propose a novel Synchronous Decoding architecture, that modifies the data received buffer to reduce the decoding time. Finally we have integrated the two methods to save the decoding latency of Turbo decoder further. To verify the proposed low latency Turbo decoders, we have used the Xilinx Virtex-4 FPGA to emulate the hardware architectures, and we have designed this Turbo decoder chip with TSMC 0.18μm 1P6M CMOS technology. This decoder chip is 71488 gate counts. Chip size including I/O pad is 1.72×1.72mm2. Power consumption is 124.97mW. Experimental result shows that for different code size, the decoding phase overlapping method has 2.86% ~ 19.05% decoding time saved, and the synchronous decoding architecture integrated has 8.39% ~ 22.62% decoding time saved with 8 iteration times at 83.33MHz working frequency.

碩士
國立中山大學
資訊工程學系研究所
92
Design of low power Turbo decoder is one of the key issues in many modern communication systems such as 3 GPP. For the Turbo decoder architecture, the memory for the storage of the branch metric and state metric represents a major part of the entire decoder no matter in silicon area or power dissipation. Therefore, instead of saving the computed branch memory, this thesis adopts an alternative approach by saving the input in order to generate the branch memory on line. Furthermore, a novel design of state metric unit is proposed such that the size of the total state metric can be effectively reduced by a half with slightly overhead of adders/subtractors. For non-recursive systematic encoding applications, the same design methodology can further reduce the number of arithmetic units required in the soft-output calculating module. Our preliminary experimental result shows that the proposed design methodology can achieve 40% and 13% reduction on the gate count and power dissipation respectively.

碩士
國立中山大學
通訊工程研究所
92
Because of the simple architecture and excellent error correcting capability, Turbo code has been adopted in many wireless communication standards, including the third generation wireless communication systems, 3GPP and 3GPP2. However, low power turbo decoder design would become the most important issue in mobile communication systems because of the limited battery life. In the thesis, we use the cyclic redundancy check (CRC) as the stopping criterion in the implementation of turbo decoder design to reduce the unnecessary power consumption. We use the MATLAB simulation and FPGA simulation to verify our design.

碩士
國立雲林科技大學
電子與資訊工程研究所碩士班
92
With the rapidly developing in communication systems, the turbo code is widely used in the third generation communication system owing to its excellent decoding performance. The turbo decoding architecture is composed of two component decoders, an interleaver and a deinterleaver. The component decoder is soft-input soft-output module which can be classified into two categories: one is the maximum a-posteriori (MAP) algorithm that exhibits excellent performance, but is too complex to implement; the other is the soft output Viterbi algorithm (SOVA) evolved from the Viterbi algorithm with the same axiom, as the turbo code is evolved from convolutional code. The thesis then implements the convolutional and SOVA-based turbo decoders with the Altera QuartusII on Stratix EP1S80 device.

碩士
國立交通大學
電子工程系所
97
In this thesis, a fully compliant and reconfigurable turbo decoder is presented to support all block lengths specified in 3GPP-LTE system. The contention-free quadratic permutation polynomial (QPP) interleaver is also introduced for parallel architecture of turbo codes. The parallel processing of iterative decoding is of interest for throughput increasing. The Max-Log MAP algorithm is used to reduce the hardware complexity with the minimized performance loss. Moreover, the reconfigurable 1/2/4/8-MAP decoders is proposed to decode the received codewords based on performance or throughput expected in different conditions. Based on QPP characteristic, the residue-only interleaver is adopted to reduce the memory storage. After implementation in a 90-nm 1P9M technology, the 130Mb/s data rate with 8 decoding iterations can be achieved in the 2.10 mm2 core area containing 602K gates. According to the post-layout simulation, the power consumption is 149.03mW worked at supply voltage 0.9V and clock rate 277MHz with block length 6144.

碩士
國立交通大學
電信工程系所
93
Turbo codes have become one of the necessary specifications for the state-of-the-art communication systems. The difficulties in implementing turbo decoder are the vast computational complexities and the request for a lot of memories. The most public method for decreasing the need of memories is sliding window method. But using sliding window method will increase the computational complexities. This thesis is purposed to propose a calculation efficient and memory saving turbo decoder. We use another memory saving algorithm – halfway algorithm, in our turbo decoder. This successfully decreases the computational complexities and the need of memory capacity. Besides, we adopt Max-Log-MAP algorithm in our design in order to simplify the hardware.

碩士
中原大學
電子工程研究所
99
In this paper, we study a turbo code decoder for 3GPP Long Term Evolution (LTE) system. We use Maximum A Posteriori Probability (MAP), Log-MAP and MAX-Log-MAP algorithm for turbo code decoding, under AWGN channel and fading channel. After channel decoding, we realize that MAP and Log-MAP has the same performance better than Max-Log-MAP, but Max-Log-MAP algorithm reduce more complexity than MAP and Log-MAP algorithm. If turbo code decoding cannot get SNR information, we use SNR estimation to solve SNR unknown. Furthermore, we consider if fading amplitude unknown, what situation will occur under fading channel.

博士
國立交通大學
電子研究所
99
This dissertation investigates the turbo decoders with parallel architecture and contention-free interleaver in pursuit of high throughput with reasonable cost. The benefits and disadvantages of conventional parallel schemes are examined; then the essential factors for throughput calculation are determined. Our discussions put emphasis on using multiple soft-in soft-out (SISO) decoders for single codeword. In addition to increasing the parallelism, the hybrid of parallel schemes is further applied for more speedup. However, the methodology leads to considerable complexity and inefficiency of processor. To reduce the complexity, we develop the multi-stage networks for the parallel data transmission in the turbo decoder. Two different types of apparatus are proposed for the designs using inter-block permutation (IBP) interleaver and quadratic permutation polynomial (QPP) interleaver, respectively. They can alleviate the routing congestion in the parallel design. To overcome the other difficulty, the processing schedule must be modified. We propose two different strategies to remove the data dependency and set their corresponding highefficiency schedules. One of them is aimed for general application, whereas the other is designed for specific case. The inactive periods within the decoding flow are greatly shortened in these schedules. Hence, the efficiency of the SISO decoder can increase. Four implemented works are presented in this dissertation. The multi-stage interconnection for IBP interleavers is applied to the first two parallel turbo decoders. Both the two designs contain multiple SISO decoders, each of which can process two or more symbols per cycle. One of them operates with the general high-efficiency schedule, and its idle time is completely removed. The third design exploits another interconnection for QPP interleavers. With such apparatus and appropriate control flow, it can use at most 8 SISO decoders to decodes all codeword blocks defined in the 3rd Generation Partnership Project Long Term Evolution standard. The remaining design also adopts QPP interleavers and the multi-stage network. It has higher parallelism than the other designs; moreover, its support of specific high-efficiency schedule results in the best efficiency. This design can achieve 1.4 Gb/s while decoding size-4096 blocks for 8 iterations. The implementation results reveal that the proposed methods work successfully in the parallel architecture and raise the throughput significantly.

碩士
國立交通大學
電子工程系所
95
In this thesis, two high-throughput decoder design about turbo code are presented. The first one is a Max-Log-MAP decoder applied for the soft-input and soft-output (SISO) trellis decoding in the turbo code. The high throughput is achieved with a two-dimensional ACS design on the radix-4x4 trellis structure, resulting in a highly parallel and area-efficient decoder. We further apply the retiming technique to reduce the critical path delay of ACS operation. After 0.13um 1P8M CMOS chip implementation, the decoder occupies 1.96 mm area containing 220K gates. The estimated timing under the 1.08V supply and the worst case corner shows that the test chip can achieve the maximum 952MS/s throughput. Since the turbo decoder is composed by two SISO maximum a posteriori (MAP) component decoders, a following high-throughput turbo decoder design will be proposed. Here we introduce a concept of the inter-block permutation to overcome the long decoding latency caused by the conventional block interleaver. Furthermore, instead of developing a complex control mechanism for the interleaver, we propose a butterfly network utilizing its hardware structure to implement the behavior of inter-block permutation. Based on the inter-block permutation interleaver, we utilize 32 Max-Log-MAP decoders as well as short block length to increase the decoding throughput considerably without suffering performance degradation. And each component decoder is structured by the retimed radix-2x2 ACS unit for a modest hardware cost consideration. After 0.13um 1P8M CMOS chip implementation, a 1.06 Gb/s throughput with 8 decoding iterations is achieved in the 17.81 mm silicon area containing 2.67 gates.

碩士
國立臺北科技大學
電腦通訊與控制研究所
92
In this thesis, we propose a new VLSI architecture for low-power turbo decoder. This architecture includes two parts to improve power dissipation properties. Firstly, we develop a new architecture for the soft-in-soft-out decoder which decreases the state storage memory space and power consumption. Secondly, we add a new stopping iteration algorithm in our turbo decoder that integrates two stop criteria to avoid unnecessary iterations, especially in low SNR channel. Finally, we have designed this new low-power turbo decoder by TSMC .35μm 2p4m process. With systematic bits and parity bits are both 4 bits, extrinsic information are 6 bits, and window size is 32, we get 25.3~39.8% memory size saving in our SISO decoder architecture in comparison with traditional decoder. When operation frequency is 25M Hz, the throughput of this decoder is 1.04M bits/sec, power consumption is 34.6 mW, and chip size including I/O pad is 2.92*2.92mm2.

碩士
元智大學
電機工程學系
105
As technology advances, we have growing requirement for transmission rate and power consumption, so the HomePlug is derived because of the request for the concept of smart home appliances. We want to design a turbo decoder applications in the HomePlug standard. HomePlug standard is divided into two major directions, the first main direction for the HomePlug GP is for the control of the Smart Grid, it control the power of home appliances which can use energy more effectively to control the electricity of household appliances. For the second direction, the HomePlug AV is mainly used for audio and video transmission. In order to achieve better transmission rate, the AV2 standard has been proposed, and the throughput of the AV2 is better than the AV. In addition, our turbo decoder added a stopping criterion which uses the window stopping technology for decoding. Also, the kernel stopping computation technology is added in the turbo decoder to detect whether the kernel is convergence. Finally, the decoder will stop the extra iterative operation by combining early termination technology, and the turbo decoder can achieve the best low-power effect. In this work, we use the CMOS process of TSMC 40nm to implement the hardware design, the operating frequency is 333 MHz, the throughput rate is more than 500Mbps and it achieve the target of HomePlug AV2standard.To be a flexible and scalable turbo decoder, our goal is not only to achieve three HomePlug standards but also be able to conform the three block sizes.

碩士
國立臺北科技大學
電腦與通訊研究所
97
Excellent error correction capability and near Shannon limiting performance make turbo code to be the most important error correcting code recently. However, turbo decoder uses enormous calculations and iterations, which is difficult to be implemented and has a long decoding latency. In this thesis, we focus on parallel turbo decoder algorithms and develop a new low complicated VLSI design method for turbo decoder. With limited dividable interleaver, the number of routing multiplexers and routing complexity can be reduced efficiency. This proposed architecture can realize high order parallel turbo decoder with low complexity of multiplexer wire connecting. To verify the proposed parallel turbo decoder, we have used the Xilinx Virtex-4 FPGA to emulate the hardware architecture, and we have designed this turbo decoder chip with TSMC 0.18μm 1P6M CMOS technology. This decoder chip uses 242,876 gate counts. Chip size including I/O pad is4.014x4.014mm^2,and operation frequency is 42M Hz .