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Journal articles on the topic 'Turbo decoder'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 July 2025

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1

Shafieipour, Mohammad, Heng-Siong Lim, and Teong-Chee Chuah. "Decoding of Turbo Codes in Symmetric Alpha-Stable Noise." ISRN Signal Processing 2011 (March 29, 2011): 1–7. http://dx.doi.org/10.5402/2011/683972.

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This paper investigates the decoding of turbo codes in impulsive symmetric α-stable (SαS) noise. Due to the nonexistence of a closed-form expression for the probability density function (pdf) of α-stable processes, numerical-based SαS pdf is used to derive branch transition probability (btp) for the maximum a posteriori turbo decoder. Results show that in Gaussian noise, the turbo decoder achieves similar performance using both the conventional and the proposed btps, but in impulsive channels, the turbo decoder with the proposed btp substantially outperforms the turbo decoder utilizing the con

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2

Boudaoud, A., M. El Haroussi, and E. Abdelmounim. "VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based on Majority Logic Codes." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 4 (2017): 1824. http://dx.doi.org/10.11591/ijece.v7i4.pp1824-1832.

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This paper presents the electronic synthesis, VHDL design and implementation on FPGA of turbo decoders for Difference Set Codes (DSC) decoded by the majority logic (ML). The VHDL design is based on the decoding equations that we have simplified, in order to reduce the complexity and is implemented on parallel process to increase the data rate. A co-simulation using the Dsp-Builder tool on a platform designed on Matlab/Simulink, allows the measurement of the performance in terms of BER (Bit Error Rate) as well as the decoder validation. These decoders can be a good choice for future digital tra

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3

A., Boudaoud, El Haroussi M., and Abdelmounim E. "VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based on Majority Logic Codes." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 4 (2017): 1824–32. https://doi.org/10.11591/ijece.v7i4.pp1824-1832.

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This paper presents the electronic synthesis, VHDL design and implementation on FPGA of turbo decoders for Difference Set Codes (DSC) decoded by the majority logic (ML). The VHDL design is based on the decoding Equations that we have simplified, in order to reduce the complexity and is implemented on parallel process to increase the data rate. A co-simulation using the Dsp-Builder tool on a platform designed on Matlab/Simulink, allows the measurement of the performance in terms of BER (Bit Error Rate) as well as the decoder validation. These decoders can be a good choice for future digital tra

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4

Krishna, T. Rama, T. Krishna Murthy, N. Vilasrao Sarode, P. Srilakshmi, and V. Geetha Sri. "Verilog HDL using LTE Implementation MAP Algorithm." International Journal of Innovative Research in Computer Science and Technology 10, no. 2 (2022): 611–14. http://dx.doi.org/10.55524/ijircst.2022.10.2.115.

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In many communication systems, turbo coding Techniques for Encoding and Decoding are employed to repair errors. As compared to other error correction codes, turbo codes provide great error correcting capabilities. For the implementation of the Turbo decoder, a Very Large Scale Integration (VLSI) architecture is suggested in this study. The Maximum-a-Posteriori (MAP) algorithm is employed at the decoder side, where soft-in-soft-out decoders, interleaves, and deinterleavers are all used. The usage of the MAP algorithm reduces the quantity of iterations necessary to decode the information bits be

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5

Islam, MS, MA Quaium, M. Morshed, and RC Roy. "Hardware implementation issues of turbo decoders." Bangladesh Journal of Scientific and Industrial Research 47, no. 3 (2012): 327–32. http://dx.doi.org/10.3329/bjsir.v47i3.13068.

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This paper gives a general overview of the implementation aspects of turbo decoders. Although the parallel architecture of the turbo code is emphasized, the serial concatenated convolutional codes for the turbo decoder are discussed too. Considering the general structure of iterative decoders, the main features of the soft input and soft output algorithm, which are the heart of a turbo decoder, are observed. The efficient parallel architectures of turbo decoders are shown which allow high speed implementation. Apart from these, implementation aspects like quantization issues and stopping rules

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6

Maity, Niladri Pratap, and Reshmi Maity. "Low Power Design of near Shannon Limit Coding: Turbo Codes." Advanced Materials Research 433-440 (January 2012): 7213–17. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.7213.

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In this paper secure channel coding schemes based on Turbo Codes are suggested and implemented. The design of encoder using Recursive Systematic Code (RSC) with puncturing techniques is presented. Component decoders are implemented by Log-Maximum-a-Posteriori (Log-MAP) algorithm and thereafter implementation of overall turbo decoder is illustrated in detail. Finally we have investigated low power design technique of the turbo decoder design with variable iteration techniques.

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7

Devrari, Aakanksha, and Adesh Kumar. "Turbo encoder and decoder chip design and FPGA device analysis for communication system." International Journal of Reconfigurable and Embedded Systems (IJRES) 12, no. 2 (2023): 174. http://dx.doi.org/10.11591/ijres.v12.i2.pp174-185.

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<p>Turbo codes are error-correcting codes with performance that is close to the Shannon theoretical limit (SHA). The motivation for using turbo codes is that the codes are an appealing mix of a random appearance on the channel and a physically realizable decoding structure. The communication systems have the problem of latency, fast switching, and reliable data transfer. The objective of the research paper is to design and turbo encoder and decoder hardware chip and analyze its performance. Two convolutional codes are concatenated concurrently and detached by an interleaver or permuter i

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Aakanksha, Devrari, and Kumar Adesh. "Turbo encoder and decoder chip design and FPGA device analysis for communication system." International Journal of Reconfigurable and Embedded Systems (IJRES) 12, no. 2 (2023): 174–85. https://doi.org/10.11591/ijres.v12.i2.pp174-185.

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Turbo codes are error-correcting codes with performance that is close to the Shannon theoretical limit (SHA). The motivation for using turbo codes is that the codes are an appealing mix of a random appearance on the channel and a physically realizable decoding structure. The communication systems have the problem of latency, fast switching, and reliable data transfer. The objective of the research paper is to design and turbo encoder and decoder hardware chip and analyze its performance. Two convolutional codes are concatenated concurrently and detached by an interleaver or permuter in the tur

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9

Wangrok Oh and Kyungwhoon Cheun. "Turbo decoder." IEEE Communications Letters 4, no. 8 (2000): 255–57. http://dx.doi.org/10.1109/4234.864186.

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V, S. Sneha, and Joe Nithin. "Implementation of Turbo Coder Using Verilog HDL for LTE." International Journal of Innovative Science and Research Technology 7, no. 7 (2022): 380–83. https://doi.org/10.5281/zenodo.6930806.

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In many communication systems, turbo codesare employed to repair errors. Turbo codes demonstrate high error correction when compared to other error correction methods. A Very Large Scale Integration is suggested in this study. VLSI architecture for the Turbo encoder implementation, Interleaves and de interleaves, and soft-in-soft-out decoders are employed. This study employs a technique that for the encoder portion, includes two recursive systematic convolutional (RSC) encoders , a Block interleaver and the decoder part involve Soft Output Virtebi Algorithm(SOVA) decoder. Aconvolutional code i

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11

Lehnigk-Emden, T., U. Wasenmüller, C. Gimmler, and N. Wehn. "Analysis of iteration control for turbo decoders in turbo synchronization applications." Advances in Radio Science 7 (May 18, 2009): 139–44. http://dx.doi.org/10.5194/ars-7-139-2009.

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Abstract. Wireless data transmission results in frequency and phase offsets of the signal in the receiver. In addition, the received symbols are corrupted by noise. Therefore, synchronization and channel coding are vital parts of each receiver in digital communication systems. By combining the phase and frequency synchronization with an advanced iterative channel decoder (inner loop) e.g. turbo codes in an iterative way (outer loop), the communications performance can be further increased. This principle is referred to as turbo synchronization. The energy consumption and the peak throughput of

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12

Salmela, Perttu, Harri Sorokin, and Jarmo Takala. "A Programmable Max-Log-MAP Turbo Decoder Implementation." VLSI Design 2008 (December 22, 2008): 1–17. http://dx.doi.org/10.1155/2008/319095.

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In the advent of very high data rates of the upcoming 3G long-term evolution telecommunication systems, there is a crucial need for efficient and flexible turbo decoder implementations. In this study, a max-log-MAP turbo decoder is implemented as an application-specific instruction-set processor. The processor is accompanied with accelerating computing units, which can be controlled in detail. With a novel memory interface, the dual-port memory for extrinsic information is avoided. As a result, processing one trellis stage with max-log-MAP algorithm takes only 1.02 clock cycles on average, whi

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MARTINA, MAURIZIO, MARIO NICOLA, and GUIDO MASERA. "VLSI IMPLEMENTATION OF WiMax CONVOLUTIONAL TURBO CODE ENCODER AND DECODER." Journal of Circuits, Systems and Computers 18, no. 03 (2009): 535–64. http://dx.doi.org/10.1142/s0218126609005241.

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A VLSI encoder and decoder implementation for the IEEE 802.16 WiMax convolutional turbo code is presented. Architectural choices employed to achieve high throughput, while granting a limited occupation of resources, are addressed both for the encoder and decoder side, including also the subblock interleaving and symbol selection functions specified in the standard. The complete encoder and decoder architectures, implemented on a 0.13 μm standard cell technology, sustain a decoded throughput of more than 90 Mb/s with a 200 MHz clock frequency. The encoder has the complexity of 9.2 kgate of logi

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Han, Jian Bing, Chen He, and Ran Zhen. "FPGA Implementation of High-Speed Memory Efficient Quasi-Cyclic LDPC Decoder." Applied Mechanics and Materials 380-384 (August 2013): 3328–31. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.3328.

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This paper introduces a new kind of decoder structure for FPGA implementation of high-speed memory efficient quasi-cyclic LDPC (QC-LDPC) decoder. The code structure, algorithm and hardware structure all adopt optimization design. The decoder adopts modified Turbo decoding algorithm and achieves a decoding throughput of 223 Mbps and frame size of 3,200 bits. The Xilinx Virtex-4 chip used by the decoder only takes up 71 KB memory and makes it exceeds other decoders in aspects of throughput and memory for FPGA implementation.

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15

Yang, Le, Tianchun Ye, Bin Wu, and Ruiqi Zhang. "LTE turbo decoder design." Journal of Semiconductors 36, no. 7 (2015): 075003. http://dx.doi.org/10.1088/1674-4926/36/7/075003.

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16

Salija, P. "An Efficient Early Iteration Termination for Turbo Decoder." Journal of Telecommunications and Information Technology, no. 2 (June 30, 2016): 113–22. http://dx.doi.org/10.26636/jtit.2016.2.729.

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Turbo code finds wide applications in mobile communication, deep space communication, satellite communication and short-range communication despite its high computational complexity and iterative nature. Realizing capacity approaching turbo code is a great achievement in the field of communication systems due to its efficient error correction capability. The high computational complexity associated with the iterative process of decoding turbo code consumes large power, introducing decoding delay, and reducing the throughput. Hence, efficient iteration control techniques are required to make th

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Suman, *. Sumit Dalal. "A NOVEL APPROACH FOR DESIGNING HYBRID TURBO CODES USING DOUBLE STAGE INTERLEAVER." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 5, no. 6 (2016): 298–307. https://doi.org/10.5281/zenodo.54794.

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Interleaver being an integral component of the communication system. The interleavers tend to avoid the burst errors by splitting the signals and the turbo codes are used to reduce the BER.The paper will describes a new approach to design a new class of turbo codes that would reduce the decoder complexity, such turbo codes will be known as modified turbo codes taking Decoder complexity as the main parameter consideration for the design of modified turbo codes. The author presents the design of two types of modified turbo codes, the one would be called as Low Complexity Hybrid turbo codes (LCHT

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18

Passas, Georgios, and Steven Freear. "VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders." Journal of Electrical and Computer Engineering 2012 (2012): 1–14. http://dx.doi.org/10.1155/2012/614259.

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The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO) unit, A-, B-, Γ-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-window-technique-based MAP decoder architectures and a proposed parameter set lead to defining equations

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Yang, Yarang, and Yunpeng Li. "Research and Implementation of Turbo Coding Technology in High-Speed Underwater Acoustic OFDM Communication." Journal of Robotics 2022 (March 15, 2022): 1–11. http://dx.doi.org/10.1155/2022/2576303.

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It is demonstrated that the fully parallel turbo decoding algorithm can achieve an approximate error correction decoding performance when 36 iterations are used and when the log-map algorithm with 6 iterations is used. By comparison, it is shown that it can achieve much higher decoding rates than the log-map algorithm for various frame lengths of LTE standard turbo codes at the cost of higher hardware resource requirements. According to the fully parallel turbo decoding algorithm, this paper proposes a scheme for implementing a fully parallel turbo decoder on FPGA, detailing the overall struct

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20

Elukuru, Sujatha, SUBHAS CHENNAPALLI, and GIRIPRASAD MAHENDRA NANJAPPA. "A New VLSI Architecture for High-Performance Parallel Turbo Decoder." IIUM Engineering Journal 23, no. 2 (2022): 125–37. http://dx.doi.org/10.31436/iiumej.v23i2.2272.

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Recent wireless communications demand maximum achievable data rates without intervention. The channel decoder in the physical layer would support such high data rates with a flexible hardware structure. The turbo channel decoder offers flexible hardware architecture and reliable decoding, but the turbo decoder design is complex and its hardware architecture consumes more power and area in a communication system. Hence, an optimized high-performance turbo decoder architecture with simplified QPP interleaver is needed for supporting various data rates. In this context, this article presents a ne

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Sokorynska, Natalia, Yurii Posternak, Liliia Zaitseva, and Oleksandr Rudenok. "THE METHOD OF ADAPTIVE SELECTION OF THE SIZE OF TURBO CODE STATE DIAGRAMS IN 5G AND IOT SYSTEMS." Technical Sciences and Technologies, no. 2(32) (2023): 249–60. http://dx.doi.org/10.25140/2411-5363-2023-2(32)-249-260.

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The article proposes a method for optimizing the operation of the turbocode encoder/decoder in 5G and IoT systems due to the adaptive selection of the state diagram size using the proposed decoding uncertainty indicator.The principles of forming state diagrams of the turbo code encoder and decoder are considered, and the uncertainty of data decoding is clarified. Using the a priori and a posteriori data of the turbo code decoder, an algorithm for changing the state diagram of the turbo code encoder/decoder is proposed.The essence of the method is to optimize the operation of the turbo code enc

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Michel, H., and N. Wehn. "Turbo-decoder quantization for UMTS." IEEE Communications Letters 5, no. 2 (2001): 55–57. http://dx.doi.org/10.1109/4234.905934.

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23

Papaharalabos, S., P. Sweeney, B. G. Evans, and P. T. Mathiopoulos. "Improved performance SOVA turbo decoder." IEE Proceedings - Communications 153, no. 5 (2006): 586. http://dx.doi.org/10.1049/ip-com:20050247.

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Babar, Zunaira, Hung Viet Nguyen, Panagiotis Botsinis, et al. "Fully-Parallel Quantum Turbo Decoder." IEEE Access 4 (2016): 6073–85. http://dx.doi.org/10.1109/access.2016.2581978.

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Buckley, M. E., and S. B. Wicker. "A neural network for predicting decoder error in turbo decoders." IEEE Communications Letters 3, no. 5 (1999): 145–47. http://dx.doi.org/10.1109/4234.766850.

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Kienle, F., H. Michel, F. Gilbert, and N. Wehn. "Efficient MAP-algorithm implementation on programmable architectures." Advances in Radio Science 1 (May 5, 2003): 259–63. http://dx.doi.org/10.5194/ars-1-259-2003.

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Abstract. Maximum-A-Posteriori (MAP) decoding algorithms are important HW/SW building blocks in advanced communication systems due to their ability to provide soft-output informations which can be efficiently exploited in iterative channel decoding schemes like Turbo-Codes. Multi-standards demand flexible implementations on programmable platforms. In this paper we analyze a quantized turbo-decoder based on a Max-Log-MAP algorithm with Extrinsic Scaling Factor (ESF). Its communication performance approximate to a Turbo-Decoder with a Log-MAP algorithm and is less sensitive to quantization effec

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Jeon, Jeongju, and Sunhee Kim. "Design and Implementation of Four-Parallel Turbo Decoder for HomePlug Green PHY." International Journal on Advanced Science, Engineering and Information Technology 15, no. 2 (2025): 464–70. https://doi.org/10.18517/ijaseit.15.2.12515.

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As electric vehicles are popularized, the importance of the safety of electric vehicle batteries has increased. Lithium-ion batteries, which are mainly used as batteries for electric vehicles, have the possibility of fire due to thermal factors, collisions, and overcharging. Recently, to prevent overcharging, battery information is exchanged between electric vehicle chargers and electric vehicle battery management systems using PLC. HomePlug Green Phy(HPGP) is a communication method for Smart Grid applications and EVs among PLCs. HPGP uses 3072-OFDM, and the number of available carriers varies

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Shrimali, Yanita, Janki Ballabh Sharma, and R. S. Meena. "VHDL Implementation of low power turbo coded OFDM physical layer for wireless communication." International Journal of Engineering & Technology 7, no. 4.5 (2018): 665. http://dx.doi.org/10.14419/ijet.v7i4.5.25054.

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Orthogonal Frequency Division Multiplexing (OFDM) is exceptionally favored system for rapid information transmission over remote channel. In this paper, VHDL implementation of low power turbo-coded OFDM (TCOFDM) Physical layer architecture is presented. In this architecture a low power memory-less pipelined FFT processor and Log-map turbo encoder/decoders are used to provide high throughput and lower complexity. Log-map turbo decoder provides high speed with good error correction capacity, while FFT/IFFT processor with single delay feedback (SDF) memory less architecture provide improved area

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Weithoffer, Stefan, and Norbert Wehn. "Where to go from here? New cross layer techniques for LTE Turbo-Code decoding at high code rates." Advances in Radio Science 16 (September 4, 2018): 77–87. http://dx.doi.org/10.5194/ars-16-77-2018.

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Abstract. The wide range of code rates and code block sizes supported by todays wireless communication standards, together with the requirement for a throughput in the order of Gbps, necessitates sophisticated and highly parallel channel decoder architectures. Code rates specified in the LTE standard, which uses Turbo-Codes, range up to r=0.94 to maximize the information throughput by transmitting only a minimum amount of parity information, which negatively impacts the error correcting performance. This especially holds for highly parallel hardware architectures. Therefore, the error correcti

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Bogawar, Mrs K. M., Ms Sharda Mungale, and Dr Manish Chavan. "Implementation of Turbo Encoder and Decoder." International Journal of Engineering Trends and Technology 8, no. 2 (2014): 73–76. http://dx.doi.org/10.14445/22315381/ijett-v8p214.

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Chuah, T. C., and C. H. Pu. "Serial turbo decoder for robust communication." Electronics Letters 41, no. 7 (2005): 427. http://dx.doi.org/10.1049/el:20057361.

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Sun, Yang, and Joseph R. Cavallaro. "A Flexible LDPC/Turbo Decoder Architecture." Journal of Signal Processing Systems 64, no. 1 (2010): 1–16. http://dx.doi.org/10.1007/s11265-010-0477-6.

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Obiedat, Esam A., and Lei Cao. "Turbo Decoder for Low-Power Ultrawideband Communication Systems." International Journal of Digital Multimedia Broadcasting 2008 (2008): 1–7. http://dx.doi.org/10.1155/2008/897069.

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A new method to reduce the computational complexity of the turbo decoding in ultrawideband (UWB) orthogonal frequency division multiplexing (OFDM) system is proposed. Existing stopping techniques for turbo decoding process using constrained decoding assume fixed signal-to-noise ratio (SNR) for all the OFDM symbol bits so they fail to yield an acceptable bit-error rate (BER) performance in multicarrier systems. In this paper, we propose a bit-level stopping technique for turbo decoding process based on the constrained decoding method. In this technique, we combine the cyclic redundancy check (C

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Sah, Dhaneshwar. "Iterative Decoding of Turbo Codes." Journal of Advanced College of Engineering and Management 3 (January 10, 2018): 15. http://dx.doi.org/10.3126/jacem.v3i0.18810.

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<p><strong> </strong>This paper presents a Thesis which consists of a study of turbo codes as an error-control Code and the software implementation of two different decoders, namely the Maximum a Posteriori (MAP), and soft- Output Viterbi Algorithm (SOVA) decoders. Turbo codes were introduced in 1993 by berrouet at [2] and are perhaps the most exciting and potentially important development in coding theory in recent years. They achieve near- Shannon-Limit error correction performance with relatively simple component codes and large interleavers. They can be constructed by con

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Peng, Cong, Lei Wang, Lerong Hong, Zehua Lin, and An Luo. "Turbo Equalization Based on a Virtual Decoder for Underwater Acoustic Communication." Journal of Marine Science and Engineering 13, no. 6 (2025): 1099. https://doi.org/10.3390/jmse13061099.

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By transferring external information between the equalizer and the decoder iteratively, the performance of turbo equalization is close to the channel capacity. Conventional turbo equalization (CTE) relies on channel coding, while the transmission of external information is a problem in an uncoded system, and turbo equalization without channel coding (TECC) remains unexplored. Therefore, this paper introduces a TECC framework with a virtual decoder constructed by bidirectional processing. The main innovation is that the existence of the virtual decoder enables the transmission of external infor

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Santhosh Kumar, K. B., B. R. Sujatha, N. Sushma, and Venkateswara Rao Kolli. "Smart and Sustainable Energy Systems: Enhanced Transmission of EEG Signals in Telemedicine Applications using Soft Output Viterbi Turbo Decoder." IOP Conference Series: Earth and Environmental Science 1375, no. 1 (2024): 012022. http://dx.doi.org/10.1088/1755-1315/1375/1/012022.

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Abstract In the era of telemedicine, where remote treatment is gaining traction, the reliable transmission of biomedical signals is paramount. Turbo Coding has emerged as a pivotal method due to its robust performance and quality of service. However, the inherent complexity of Turbo decoders presents a significant hurdle. This paper investigates the efficacy of Soft Output Viterbi Algorithm (SOVA), Logarithmic MAP (Log-MAP), and Maximum A posteriori Probability (MAP) decoding techniques within Turbo decoding, crucial for real-time telemedicine applications. Focusing specifically on EEG signal

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Alebady, Wallaa Yaseen, and Ahmed Abdulkadhim Hamad. "Turbo polar code based on soft-cancelation algorithm." Indonesian Journal of Electrical Engineering and Computer Science 26, no. 1 (2022): 521–30. https://doi.org/10.11591/ijeecs.v26.i1.pp521-530.

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Since the first polar code of Arikan, the research field of polar codes has been continuously active. Improving the performance of finite-code-length polar codes is the central point of this field. In this paper, the parallel concatenated systematic turbo polar code (PCSTPC) model has been proposed to improve the polar codes performance in a finite-length regime. On the encoder side, two systematic polar encoders are used as constituent encoders. While on the decoder side, two single iteration soft-cancelation (SCAN) decoders are used as soft-in-soft-out (SISO) algorithms inside the iterative

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Ni, Liangfang, Huijie Dai, Weixia Li, Kangbo Zhuo, and Chengchao Zhang. "An Iterative SISO Improved Complex Sphere Detection and Decoder for Turbo-MIMO Systems." International Journal of Sciences Volume 8, no. 2019-01 (2019): 60–71. https://doi.org/10.5281/zenodo.3350551.

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An iterative soft-input soft-output (SISO) improved complex sphere detection and decoder algorithm is proposed for signal detection in Turbo-MIMO system. It forms candidate points set Θ in terms of an accumulated cost function based on a search arc constrained by the received signals. Then, the candidate points subset, the lower cost bound of which is not smaller than upper bound, is fathomed and dropped from further consideration. Meanwhile, once a new feasible candidate point is turned up, the path closest to completion is casted upon to generate the set Θ with optimal candidate vectors, aim

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Souza, Ilan Schnitman, and V. T. Dos Reis. "A VLSI Design for the LTE Turbo Decoder." Journal of Integrated Circuits and Systems 7, no. 1 (2012): 16–22. http://dx.doi.org/10.29292/jics.v7i1.352.

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Due to the need of high performance, new wireless telecommunications standards such asWIMAX and LTE are using turbo-codes as a forward error correction (FEC) choice.This design targets either a self-contained IP (Intellectual Property) or integration into the physical layer project. This work presents all steps for the implementation of an LTE standard turbo decoder: from algorithm modeling in high level programming language to architecture using a sliding window approach seeking throughput needed, getting into physical implementation at TSMC 65nm. Each aspect of the specification and performa

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Dong, Jie, Yong Li, Rui Liu, Taolin Guo, and Francis C. M. Lau. "Efficient Decoder for Turbo Product Codes Based on Quadratic Residue Codes." Electronics 11, no. 21 (2022): 3598. http://dx.doi.org/10.3390/electronics11213598.

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In this letter, we study turbo product codes with quadratic residue codes (called QR-TPCs) as the component codes. We propose an efficient decoder based on Chase-II algorithm with two convergence conditions for the iterative decoding of QR-TPCs. For each row and column, the Chase-II decoder will stop immediately when one of the conditions is met. The simulation results show that the proposed algorithm has a lower computational complexity compared with existing decoding methods. Moreover, a comparison with 5G low-density parity-check codes shows that the proposed turbo product codes have better

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Al-Dweik, A., H. Mukhtar, E. Alsusa, and J. Dias. "Ultra-Light Decoder for Turbo Product Codes." IEEE Communications Letters 22, no. 3 (2018): 446–49. http://dx.doi.org/10.1109/lcomm.2017.2781223.

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42

Boyer, Pete, and Arthur Giordano. "Turbo decoder SNR estimation with RAKE reception." IEEE Transactions on Communications 57, no. 2 (2009): 430–39. http://dx.doi.org/10.1109/tcomm.2009.02.050081.

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Al-Dweik, A., S. Le Goff, and B. Sharif. "A Hybrid Decoder for Block Turbo Codes." IEEE Transactions on Communications 57, no. 5 (2009): 1229–32. http://dx.doi.org/10.1109/tcomm.2009.05.070107.

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Regalia, Phillip A., and John MacLaren Walsh. "Optimality and Duality of the Turbo Decoder." Proceedings of the IEEE 95, no. 6 (2007): 1362–77. http://dx.doi.org/10.1109/jproc.2007.896495.

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Jose A, Liji, and Sethu Raj. "Low Complexity Turbo Decoder with ACS Unit." International Journal of Engineering Trends and Technology 36, no. 8 (2016): 446–51. http://dx.doi.org/10.14445/22315381/ijett-v36p280.

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Martina, M., M. Nicola, and G. Masera. "A Flexible UMTS-WiMax Turbo Decoder Architecture." IEEE Transactions on Circuits and Systems II: Express Briefs 55, no. 4 (2008): 369–73. http://dx.doi.org/10.1109/tcsii.2008.919510.

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Karthik, K. V., and Naveen I.G. "Low Complexity Decoder for CCSDS Turbo codes." IOSR Journal of Electronics and Communication Engineering 9, no. 4 (2014): 19–23. http://dx.doi.org/10.9790/2834-09431923.

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Jung, P. "Novel low complexity decoder for turbo-codes." Electronics Letters 31, no. 2 (1995): 86–87. http://dx.doi.org/10.1049/el:19950069.

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Schurgers, C., F. Catthoor, and M. Engels. "Memory optimization of MAP turbo decoder algorithms." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9, no. 2 (2001): 305–12. http://dx.doi.org/10.1109/92.924051.

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Kwonhue Choi. "Residual Frequency Offset Compensation-Embedded Turbo Decoder." IEEE Transactions on Vehicular Technology 57, no. 5 (2008): 3211–17. http://dx.doi.org/10.1109/tvt.2007.914482.

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