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Dissertations / Theses on the topic 'Turbo decoder'

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Published: 4 June 2021
Last updated: 25 July 2025

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1

Allala, Prathyusha. "Genetic Optimization of Turbo Decoder." Ohio University / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1293681661.

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2

Padinjare, Sainath. "VLSI implementation of a turbo encoder/decoder /." Internet access available to MUN users only, 2003. http://collections.mun.ca/u?/theses,162832.

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3

Al-Mohandes, Ibrahim. "Energy-Efficient Turbo Decoder for 3G Wireless Terminals." Thesis, University of Waterloo, 2005. http://hdl.handle.net/10012/838.

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Since its introduction in 1993, the turbo coding error-correction technique has generated a tremendous interest due to its near Shannon-limit performance. Two key innovations of turbo codes are parallel concatenated encoding and iterative decoding. In its IMT-2000 initiative, the International Telecommunication Union (ITU) adopted turbo coding as a channel coding standard for Third-Generation (3G) wireless high-speed (up to 2 Mbps) data services (cdma2000 in North America and W-CDMA in Japan and Europe). For battery-powered hand-held wireless terminals, energy consumption is a major
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4

Fei, Jia. "On a turbo decoder design for low power dissipation." Thesis, Virginia Tech, 2000. http://hdl.handle.net/10919/34090.

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A new coding scheme called "turbo coding" has generated tremendous interest in channel coding of digital communication systems due to its high error correcting capability. Two key innovations in turbo coding are parallel concatenated encoding and iterative decoding. A soft-in soft-out component decoder can be implemented using the maximum a posteriori (MAP) or the maximum likelihood (ML) decoding algorithm. While the MAP algorithm offers better performance than the ML algorithm, the computation is complex and not suitable for hardware implementation. The log-MAP algorithm, which performs n
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5

Šedý, Jakub. "Turbo konvoluční a turbo blokové kódy." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-219287.

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The aim is to explain the Turbo convolutional and block turbo codes and decoding the secure message. The practical part focuses on the design of a demonstration program in Matlab. The work is divided into four parts. The first two deal with theoretical analysis of coding and decoding. The third section contains a description created a demonstration program that allows you to navigate the process of encoding and decoding. The fourth is devoted to simulation and performance of turbo codes.
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6

Lindblom, Johannes. "Turbo Decoding With Early State Decisions." Thesis, Linköping University, Department of Electrical Engineering, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-11694.

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<p>Turbo codes was first presented in 1993 by C. Berrou, A. Glavieux and P. Thitimajshima. Since then this class of error correcting codes has become one of the most popular, because of its good properties. The turbo codes are able to come very close to theoretical limit, the Shannon limit. Turbo codes are for example used in the third generation of mobile phone (3G) and in the standard IEEE 802.16 (WiMAX).</p><p>There are some drawbacks with the algorithm for decoding turbo codes. The deocoder uses a Maximum A Posteriori (MAP) algorithm, which is a complex algorith. Because of the use of many
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7

Ahlqvist, Johan. "Evaluation of the Turbo-decoder Coprocessor on a TMS320C64x Digital Signal Processor." Thesis, Linköpings universitet, Kommunikationssystem, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-71656.

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One technique that is used to reduce the errors brought upon signals, when transmitted over noisy channels, is error control coding. One type of such coding, which has a good performance, is turbo coding. In some of the TMS320C64xTM digital signal processors there is a built in coprocessor that performs turbo decoding. This thesis is performed on the account of Communication Developments, within Saab AB and presents an evaluation of this coprocessor. The evaluation deals with both the memory consumption as well as the data rate. The result is also compared to an implementation of turbo coding
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8

Hess, Jason Richard. "Implementation of a Turbo Decoder on a Configurable Computing Platform." Thesis, Virginia Tech, 1999. http://hdl.handle.net/10919/35131.

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Turbo codes are a new class of codes that can achieve exceptional error performance and energy efficiency at low signal-to-noise ratios. Decoding turbo codes is a complicated procedure that often requires custom hardware if it is to be performed at acceptable speeds. Configurable computing machines are able to provide the performance advantages of custom hardware while maintaining the flexibility of general-purpose microprocessors and DSPs. This thesis presents an implementation of a turbo decoder on an FPGA-based configurable computing platform. Portability and flexibility are emphasize
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9

Han, Jong Hun. "Turbo decoder VLSI implementations for multi-standards wireless communication systems." Thesis, University of Edinburgh, 2006. http://hdl.handle.net/1842/14977.

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This thesis presents high performance turbo decoder architecture for VLSI implementation in terms of area, power and critical path delay. A Max-Log-MAP (MLMAP) algorithm is used to implement the turbo decoder with sliding window (SW) method to reduce the latency. Low power and area efficient turbo decoder implementation is achieved by reducing memory blocks required to control the SW method and to store the branch metrics used for computing log-likelihood-ratio (LLR). Retiming and reordering method is applied to implementing the units needed to calculate the LLR and the state metrics, to save
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10

Hussein, Ahmed Refaey Ahmed. "Universal Decoder for Low Density Parity Check, Turbo and Convolutional Codes." Thesis, Université Laval, 2011. http://www.theses.ulaval.ca/2011/28154/28154.pdf.

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11

Chowdhari, Vikram. "Performance of a Low Rate Duo - Binary Turbo Decoder With Genetic Optimization." Ohio University / OhioLINK, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1244495510.

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12

Ploštica, Stanislav. "Turbo kódy a jejich aplikace." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-218201.

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This Diploma thesis aims to explain the data coding using turbo codes. These codes belong to the group of error correction codes. We can reach the high efficiency using these codes. The first part describes process of encoding and decoding. There are describes parts of encoder and decoder. Principle of encoding and decoding demonstrate a simple example. The end of this part contains description of two most frequently used decoding algorithms (SOVA and MAP). The second part contains description of computer program that was made for using as teaching aid. This program was created in Matlab GUI.
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13

Puckett, W. Bruce. "Implementation and Performance of an Improved Turbo Decoder on a Configurable Computing Machine." Thesis, Virginia Tech, 2000. http://hdl.handle.net/10919/34038.

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Turbo codes are a recently discovered class of error correction codes that achieve near-Shannon limit performance. Because of their complexity and highly parallel nature, turbo-coded applications are well suited for configurable computing. Field-programmable gate arrays (FPGAs), which are the main building blocks of configurable computing machines (CCMs), allow users to design flexible hardware that is optimized for performance, speed, power consumption, and chip-area. This thesis presents the implementation and performance of an improved turbo decoder on a configurable computing platform.
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14

Lapôtre, Vianney. "Toward dynamically reconfigurable high throughput multiprocessor Turbo decoder in a multi-mode and multi-standard context." Lorient, 2013. http://www.theses.fr/2013LORIS305.

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Recent years have seen a huge evolution of wireless communication standards in the domains of mobile phone, local and wide area networks and video broadcasting. These evolutions aim at increasing the requirements in terms of throughput, robustness against destructive channel effects and convergence of services in a smart terminal. As an example, the fourth generation (4G) of cellular wireless standards aims at providing mobile broadband solution to laptop computer wireless modems, smartphones, and other mobile devices. Diverse features such as ultra-broadband Internet access, IP telephony, gam
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15

Barbero, Liñan Luis G. "Rapid prototyping of a fixed-complexity sphere decoder and its application to iterative decoding of turbo-MIMO systems." Thesis, University of Edinburgh, 2007. http://hdl.handle.net/1842/11903.

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This thesis concentrates on the analysis of the sphere decoder (SD) for MIMO detection. It provides optimal maximum likelihood (ML) performance with reduced complexity compared to the maximum likelihood detector (MLD). However, a field-programmable gate array (FPGA) implementation of the algorithm presents several disadvantages due to its variable complexity and the sequential nature of its tree search. This research proposes a fixed-complexity sphere decoder (FSD) to overcome the drawbacks of the SD. It provides a fixed complexity and achieves quasi-maximum likelihood (ML) performance, combin
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CONDO, CARLO. "VLSI decoding architectures: flexibility, robustness and performance." Doctoral thesis, Politecnico di Torino, 2014. http://hdl.handle.net/11583/2544356.

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Stemming from previous studies on flexible LDPC decoders, this thesis work has been mainly focused on the development of flexible turbo and LDPC decoder designs, and on the narrowing of the power, area and speed gap they might present with respect to dedicated solutions. Additional studies have been carried out within the field of increased code performance and of decoder resiliency to hardware errors. The first chapter regroups several main contributions in the design and implementation of flexible channel decoders. The first part concerns the design of a Network-on-Chip (NoC) serving as an
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Gorthy, Anantha Surya Raghu. "A Study on the Effects of Decoder Quantization of Digital Video Broadcasting - Return Channel over Satellite (DVB-RCS) Turbo Codes." Ohio University / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1226965326.

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18

Loo, Kok Keong. "A novel parallelised turbo decoder design technique for wireless mobile communications : the impact of work stressors and other predictors." Thesis, University of Hertfordshire, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.269427.

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19

Wu, Jung-Hsuan, and 吳榮軒. "Dual Mode Viterbi/Turbo-Code Decoder." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/28131710053774907615.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>100<br>The next-generation communication system, long term evolution (LTE), is currently the most popular mobile wireless technology in the market. LTE allows wireless service providers to improve the economics of deploying mobile broadband networks. The performance of LTE is better than the today’s 3G or 3.5G wireless network. LTE has already been the new standard of a next-generation communication system announced by the third generation partnership project (3GPP). Compared to the 3G and 3.5G communication systems, the obvious advantage of LTE is its high data rat
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Lin, Chu-Yi, and 林鉅翊. "High Radix Turbo Decoder for 3GPP." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/82586064118172453469.

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碩士<br>國立清華大學<br>電機工程學系<br>97<br>For the 3rd Generation Partnership Project(3GPP) specification, the turbo code is applied in the transmitted data because the data needs a better error correction capability. With the increase of the utilization of the turbo decoder in the next generation system, decoding speed for the MAP decoder has become more and more critical. Hence, the target of this thesis is to design a high throughput MAP decoder for the turbo decoder. We propose a radix-16 MAP algorithm to reduce the decoding cycle, and a modified term method to improve the decoding performance. Then,
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Hu, Jyun-Ming, and 胡峻銘. "Parallelization of Turbo Decoder on GPU." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/w9d6a7.

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Hsueh, Nai-Hsuan, and 薛乃軒. "Low power Turbo decoder for communication system." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/65858756492959214033.

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碩士<br>國立中央大學<br>電機工程研究所<br>90<br>Turbo codes, proposed by Berrou et al. in 1993, which are parallel concatenated convolution codes joined through interleavers. Iterative decoding techniques are used for decoding. It has been shown that any decoder that accepts soft inputs (include a priori values) and generates soft outputs can be used for iterative decoding. Turbo code can achieve almost near Shannon limit error correction performance, its powerful error correcting capability is very attractive for mobile wireless applications to combat channel fading. Turbo code has been adopted as the chann
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Ko, Meng-chang, and 柯孟昌. "Implementation of Turbo Code Decoder IP Builder." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/63886996069473835550.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>92<br>Turbo Code, due to its excellent error correction capability, has been widely used in many modern wireless digital communication systems as well as data storage systems in recent years. However, because the decoding of the Turbo Code involves finding all the state probability and transition sequence, its hardware implementation is not straightforward as it requires a lot of memory and memory operation. In this thesis, a design of Turbo Code decoder IP (Intellectual Property) is proposed which can be parameterized with different word-lengths and code rates.
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24

Liao, Ying-Chao, and 廖盈超. "A Radix-4 Turbo Decoder for 3GPP." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/34790722653000235531.

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碩士<br>國立交通大學<br>電機與控制工程系所<br>97<br>Turbo code has been widely used in communication systems, because of its outstanding error correction performance. To increase throughput and decrease the required memory. Radix-4 architecture for Turbo decoder was studied. However, the critical path of the recursive architecture in Radix-4 turbo decoder is long, As a result conventional Radix-4 architecture [15] cannot achieve twice throughput over the conventional Radix-2 architecture. In this thesis, we proposed a Look-Up Table scheme for the recursive architecture and the throughput increases up to 62%. T
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25

Huang, Hung-bin, and 黃宏斌. "IRA-based turbo-like Raptor code decoder." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/57361339381664251027.

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碩士<br>國立中正大學<br>通訊工程研究所<br>97<br>The Raptor codes – the best approximation to a digital fountain. These codes are rateless. We use IRA code for pre-coder of Raptor code for encoder, and use the turbo-like structure to our joint Raptor decoder. The turbo-like structure is 2-stage BP algorithm cascade structure. Two decoders exchange the soft information each iteration, which is similar to the series-turbo code. We also design the IRA permutation to help us find out the permutation matrix more efficient. Extending recent works on distributed source coding, this paper considers distributed sourc
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Tseng, Kai-Hsin, and 曾凱信. "Contention Free Algorithm for Parallel Turbo Decoder." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/53841169447611790406.

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碩士<br>國立交通大學<br>電信工程系所<br>97<br>In this thesis, a contention free algorithm for solving memory collision problem of parallel Turbo decoder architecture using the simulated annealing algorithm is presented. Furthermore, we proposed two area-efficient extrinsic memory schemes based on the parallel contention free Turbo decoder. One of the proposed schemes employs only multiple single port memories with one temporary buffer instead of the original dual port or two port memories. And the other scheme further employs an additional non-linear
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Yeh, Chien-Liang, and 葉建良. "The SIP Generator Design for Turbo Decoder." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/4tfd69.

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碩士<br>國立臺北科技大學<br>電腦與通訊研究所<br>93<br>In communication system, turbo decoder is widely used nowaday. However, the specifications of turbo decoders are difference in various communication applications. It will cost lot of time and labor to design turbo decoder with traditional methods, which does not meet Time to Market requirement. In this thesis, we propose a De-interleaver free table turbo decoder SIP generator. This IP generator not only provides IC designer to generate a turbo decoder with configurable parameter but also the automatic performance simulation which produces the SNR and BER re
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Yen, Ling-Fan, and 葉凌帆. "Dummy-Beta-Latency-Free Turbo Decoder Design." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/w7zuys.

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碩士<br>國立臺北科技大學<br>電腦與通訊研究所<br>94<br>Turbo code is a forward error correct code which has good error correction capability and near Shannon limiting performance. Traditional turbo decoder needs large memory size and has long decoding latency for implementation. This paper presents a dummy-beta-latency-free algorithm which can reduce the decoding latency of sliding window from 4L to 1L. In hardware implementation, we can use a dummy-beta memory unit to replace one backward calculation unit and two SISO sub-memories. Experimental results show that our architecture can save 27%~45% memory bit and
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Hong, Wei-Song, and 洪維崧. "FPGA Implementation of LTE Turbo code Decoder." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/j4j9z3.

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碩士<br>國立中央大學<br>通訊工程學系<br>106<br>In the LTE uplink, tail biting convolutional coding and trubo coding are used in the channel coding, this paper follow 3GPP TS 36.212 to design turbo code decoder. We separate this paper into two parts. In first part, the algorithm which is used in the decoder will be introduced. The maximum a posterior probability (MAP) algorithm is too complex for the hardware, so the Max-Log-MAP algorithm which is next only to MAP is used. We use AWGN(Additive white Gaussian noise) channel as the simulation environment, and follow the algorithm simulation to decide the fixed
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Chen, Chiu-Yuan, and 陳秋源. "The research and hardware design of Turbo decoder." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/59359578747429114332.

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碩士<br>國立雲林科技大學<br>電機工程系碩士班<br>93<br>Turbo code, which has closely approached the Shannon Limit Theorem, was first proposed by Berrou, Glavieux and Thitimajashima in 1993. Because the turbo code exhibits very small average probability of error at low signal-to-noise ratio, it has attracted a lot of research interest and has been widely applied to many wireless communication systems. In this thesis, we mainly focus on the investigation of the S-random interleaver in a turbo code. The major drawback of the traditional S-random interleaver is its slow generation of the interleaved sequence. A nove
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張閔盛, Min-Sheng Chang, and 張閔盛. "VLSI Architecture Design of Parallel Phase Turbo Decoder." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/9w5pyu.

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碩士<br>國立臺北科技大學<br>電腦與通訊研究所<br>98<br>In this thesis, we proposed a novel parallel phase turbo decoding algorithm for VLSI architecture. Traditional sliding window turbo algorithm exchanges extrinsic information phase by phase, it will induce a long decoding latency. The proposed algorithm exchanges extrinsic information as soon as it had been calculated half the frame size, thus, it can not only eliminate (De-)Interleaver delay but also save the storage space. Besides, we modify the received data RAM to reduce the decoding time. By using this method, the decoder can reduce half frame decoding l
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Chen, Yi-Cheng, and 陳義城. "Chip Design of Dual Phase Parallel Turbo Decoder." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/ewqy5t.

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碩士<br>國立臺北科技大學<br>電腦與通訊研究所<br>99<br>Turbo codes use an iterative algorithm that allows the BER performance to achieve the Shannon limit to carry out decoding. Relative literatures and developments have been researched over decades. One of the requirements of communication standard is throughput which can be satisfied by using parallel or high radix architecture. However, both methods would cause the degradation of the BER performance because they shorten the interleaver length. Hence, we propose a dual phase decoding architecture for two SISO decoders based on different decoding phase. Compare
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Wang, Chin Tai, and 王璟玳. "A Novel Hybrid Decoder for Block Turbo Codes." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/02803500974514200902.

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碩士<br>長庚大學<br>電機工程學系<br>98<br>This thesis proposes extrinsic-information-based decoding algorithms for original block turbo codes (BTCs) and hybrid block turbo codes. Since the number of algebraic decodings dominates the complexity of BTC decoding, it is important for BTC research to reduce the number of algebraic decodings without noticeable loss of bit-error rate performance. In each iterative decoding process, the algorithm compares the extrinsic information of the mth iteration and the (m-1)th iteration to determine when the HIHO decoding starts. Additionally, in BTC decoding, the decoder
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Lyu, Hsueh-Cheng, and 呂學承. "Normalization of Output Informations for a Turbo Decoder." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/49839624918115574705.

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碩士<br>明志科技大學<br>機電工程研究所<br>96<br>In recent years, considerable interest has been devoted to turbo codes that achieve near-Shannon limit performance. At the receiver, decoding can be done in an iterative way either using the maximum a-posteriori (MAP) algorithm or the soft-output Viterbi algorithm (SOVA). The SOVA is less complex, but has a performance degradation of about 0.7 dB compared to the MAP. Instead of using the MAP algorithm, decoding turbo codes with the max-log-MAP algorithm is a good compromise between performance and complexity. However, it has been found that the output informati
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Lee, Ming-Chang, and 李明昌. "Chip Design for a High Speed Turbo Decoder." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/38443606247585605090.

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碩士<br>國立臺北科技大學<br>電腦通訊與控制研究所<br>92<br>Excellent error correction capability and near Shannon limiting performance make turbo code to be the most important error correcting code recently. However, turbo decoder uses enormous calculations and iterations, which is difficult to be implemented and has a long decoding latency. In this thesis, we focus on turbo code algorithms and develop a new VLSI architecture for high-speed turbo decoder. Firstly, we have proposed a new low-latency-normalization method in our design, which can speed up the decoder throughput about 18%~34% and reduce chip area of s
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Wang, Tz-Jang, and 王子健. "Design & Implementation of a Fast Turbo Decoder." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/26479097691144593940.

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碩士<br>國立清華大學<br>電機工程學系<br>91<br>Turbo codes, due to its excellent capability of maintaining low bit error rate (BER) under high transmission speed and low SNR environment, are adopted in various 3GPP standards for mobile communication systems, such as CDMA 2000, WCDMA, .., etc. Recently, many research efforts have been directed toward developing efficient algorithms, architectures, and VLSI circuits for implementing the much more complicated turbo code decoder. Among many decoding algorithms, the MAP (maximum a posteriori probability) algorithm is the one with the lowest bit-error-rate and als
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Lin, Chen-Yang, and 林振揚. "A Turbo Decoder Design Using Reciprocal Dual Trellis." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/04978298534734383089.

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Lin, Chen-Yang, and 林振暘. "VLSI Architecture Design of Low Latency Turbo Decoder." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/r9rw93.

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碩士<br>國立臺北科技大學<br>電腦與通訊研究所<br>96<br>In this thesis, we present two low latency decoding methods for VLSI Turbo decoder. In our design, we propose a novel sliding window operating flow, called Decoding Phase Overlapping method. It can improve the hardware efficiency and reduce the decoding delay of Turbo decoder. With this improved methodology, we have four decoding windows latency can be saved in comparison with traditional decoders. Besides, we also propose a novel Synchronous Decoding architecture, that modifies the data received buffer to reduce the decoding time. Finally we have integrated
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LIN, CHANG HUI, and 林昌輝. "An Investigation and Hardware Architectural Implementation of Turbo Decoder." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/20103446892538534122.

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40

Wu, Sung-han, and 吳松翰. "Design and Implementation of Low Power Turbo Code Decoder." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/17990388696162978770.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>92<br>Design of low power Turbo decoder is one of the key issues in many modern communication systems such as 3 GPP. For the Turbo decoder architecture, the memory for the storage of the branch metric and state metric represents a major part of the entire decoder no matter in silicon area or power dissipation. Therefore, instead of saving the computed branch memory, this thesis adopts an alternative approach by saving the input in order to generate the branch memory on line. Furthermore, a novel design of state metric unit is proposed such that the size of the t
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Cheng, Chin-ren, and 鄭欽仁. "An Implementation of Low-Power Turbo Decoder for 3GPP." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/59436004811596052123.

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碩士<br>國立中山大學<br>通訊工程研究所<br>92<br>Because of the simple architecture and excellent error correcting capability, Turbo code has been adopted in many wireless communication standards, including the third generation wireless communication systems, 3GPP and 3GPP2. However, low power turbo decoder design would become the most important issue in mobile communication systems because of the limited battery life. In the thesis, we use the cyclic redundancy check (CRC) as the stopping criterion in the implementation of turbo decoder design to reduce the unnecessary power consumption. We use the MATLA
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Wu, Kang-Shuo, and 吳康碩. "FPGA Implementation of Convolutional and SOVA-Based Turbo Decoder." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/99985528289113096048.

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碩士<br>國立雲林科技大學<br>電子與資訊工程研究所碩士班<br>92<br>With the rapidly developing in communication systems, the turbo code is widely used in the third generation communication system owing to its excellent decoding performance. The turbo decoding architecture is composed of two component decoders, an interleaver and a deinterleaver. The component decoder is soft-input soft-output module which can be classified into two categories: one is the maximum a-posteriori (MAP) algorithm that exhibits excellent performance, but is too complex to implement; the other is the soft output Viterbi algorithm (SOVA) evolve
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43

Lee, Yung-Yu, and 李永裕. "Research on Reconfigurable Turbo Decoder for 3GPP-LTE Applications." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/23869524991071425537.

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碩士<br>國立交通大學<br>電子工程系所<br>97<br>In this thesis, a fully compliant and reconfigurable turbo decoder is presented to support all block lengths specified in 3GPP-LTE system. The contention-free quadratic permutation polynomial (QPP) interleaver is also introduced for parallel architecture of turbo codes. The parallel processing of iterative decoding is of interest for throughput increasing. The Max-Log MAP algorithm is used to reduce the hardware complexity with the minimized performance loss. Moreover, the reconfigurable 1/2/4/8-MAP decoders is proposed to decode the received codewords based on
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44

Chong, Wen-Choung, and 鍾文狀. "Calculation Efficient and Memory Saving Turbo Decoder for 3GPP." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/wmr5fe.

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碩士<br>國立交通大學<br>電信工程系所<br>93<br>Turbo codes have become one of the necessary specifications for the state-of-the-art communication systems. The difficulties in implementing turbo decoder are the vast computational complexities and the request for a lot of memories. The most public method for decreasing the need of memories is sliding window method. But using sliding window method will increase the computational complexities. This thesis is purposed to propose a calculation efficient and memory saving turbo decoder. We use another memory saving algorithm – halfway algorithm, in our turbo decode
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45

Wei, Chi-Yang, and 魏啟洋. "Study of Turbo Code Decoder for 3GPP LTE System." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/by92h2.

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碩士<br>中原大學<br>電子工程研究所<br>99<br>In this paper, we study a turbo code decoder for 3GPP Long Term Evolution (LTE) system. We use Maximum A Posteriori Probability (MAP), Log-MAP and MAX-Log-MAP algorithm for turbo code decoding, under AWGN channel and fading channel. After channel decoding, we realize that MAP and Log-MAP has the same performance better than Max-Log-MAP, but Max-Log-MAP algorithm reduce more complexity than MAP and Log-MAP algorithm. If turbo code decoding cannot get SNR information, we use SNR estimation to solve SNR unknown. Furthermore, we consider if fading amplitude unknown,
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Wong, Cheng-Chi, and 翁政吉. "Turbo Decoder with Parallel Architecture and Contention-Free Interleaver." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/26347910110023998827.

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博士<br>國立交通大學<br>電子研究所<br>99<br>This dissertation investigates the turbo decoders with parallel architecture and contention-free interleaver in pursuit of high throughput with reasonable cost. The benefits and disadvantages of conventional parallel schemes are examined; then the essential factors for throughput calculation are determined. Our discussions put emphasis on using multiple soft-in soft-out (SISO) decoders for single codeword. In addition to increasing the parallelism, the hybrid of parallel schemes is further applied for more speedup. However, the methodology leads to considerable c
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47

Tang, Cheng-Hao, and 唐正浩. "Design and Implementation for high-throughput Turbo Decoder Chip." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/30771714806504875000.

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碩士<br>國立交通大學<br>電子工程系所<br>95<br>In this thesis, two high-throughput decoder design about turbo code are presented. The first one is a Max-Log-MAP decoder applied for the soft-input and soft-output (SISO) trellis decoding in the turbo code. The high throughput is achieved with a two-dimensional ACS design on the radix-4x4 trellis structure, resulting in a highly parallel and area-efficient decoder. We further apply the retiming technique to reduce the critical path delay of ACS operation. After 0.13um 1P8M CMOS chip implementation, the decoder occupies 1.96 mm area containing 220K gates. The es
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48

Lin, San-Ho, and 林山賀. "IC design of a new low-power turbo decoder." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/88091083895425401882.

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碩士<br>國立臺北科技大學<br>電腦通訊與控制研究所<br>92<br>In this thesis, we propose a new VLSI architecture for low-power turbo decoder. This architecture includes two parts to improve power dissipation properties. Firstly, we develop a new architecture for the soft-in-soft-out decoder which decreases the state storage memory space and power consumption. Secondly, we add a new stopping iteration algorithm in our turbo decoder that integrates two stop criteria to avoid unnecessary iterations, especially in low SNR channel. Finally, we have designed this new low-power turbo decoder by TSMC .35μm 2p4m pr
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49

Chang, Kai-Chun, and 張凱鈞. "Flexible Turbo Decoder Design and Implementation for HomePlug Standards." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/94327486619299428938.

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碩士<br>元智大學<br>電機工程學系<br>105<br>As technology advances, we have growing requirement for transmission rate and power consumption, so the HomePlug is derived because of the request for the concept of smart home appliances. We want to design a turbo decoder applications in the HomePlug standard. HomePlug standard is divided into two major directions, the first main direction for the HomePlug GP is for the control of the Smart Grid, it control the power of home appliances which can use energy more effectively to control the electricity of household appliances. For the second direction, the HomePlug
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Lu, Kuan-Ying, and 盧冠穎. "VLSI Architecture Design of Low Complicated Parallel Turbo Decoder." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/c4w626.

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碩士<br>國立臺北科技大學<br>電腦與通訊研究所<br>97<br>Excellent error correction capability and near Shannon limiting performance make turbo code to be the most important error correcting code recently. However, turbo decoder uses enormous calculations and iterations, which is difficult to be implemented and has a long decoding latency. In this thesis, we focus on parallel turbo decoder algorithms and develop a new low complicated VLSI design method for turbo decoder. With limited dividable interleaver, the number of routing multiplexers and routing complexity can be reduced efficiency. This proposed architectu
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