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Journal articles on the topic 'Turbo decoder'

Author: Grafiati

Published: 4 June 2021

Last updated: 14 March 2023

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1

Shafieipour, Mohammad, Heng-Siong Lim, and Teong-Chee Chuah. "Decoding of Turbo Codes in Symmetric Alpha-Stable Noise." ISRN Signal Processing 2011 (March 29, 2011): 1–7. http://dx.doi.org/10.5402/2011/683972.

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This paper investigates the decoding of turbo codes in impulsive symmetric α-stable (SαS) noise. Due to the nonexistence of a closed-form expression for the probability density function (pdf) of α-stable processes, numerical-based SαS pdf is used to derive branch transition probability (btp) for the maximum a posteriori turbo decoder. Results show that in Gaussian noise, the turbo decoder achieves similar performance using both the conventional and the proposed btps, but in impulsive channels, the turbo decoder with the proposed btp substantially outperforms the turbo decoder utilizing the conventional btp. Results also confirm that the turbo decoder incorporating the proposed btp outperforms the existing Cauchy-based turbo decoder in non-Cauchy impulsive noise, while the two decoders accomplish similar performance in Cauchy noise.

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2

Boudaoud, A., M. El Haroussi, and E. Abdelmounim. "VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based on Majority Logic Codes." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 4 (August 1, 2017): 1824. http://dx.doi.org/10.11591/ijece.v7i4.pp1824-1832.

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This paper presents the electronic synthesis, VHDL design and implementation on FPGA of turbo decoders for Difference Set Codes (DSC) decoded by the majority logic (ML). The VHDL design is based on the decoding equations that we have simplified, in order to reduce the complexity and is implemented on parallel process to increase the data rate. A co-simulation using the Dsp-Builder tool on a platform designed on Matlab/Simulink, allows the measurement of the performance in terms of BER (Bit Error Rate) as well as the decoder validation. These decoders can be a good choice for future digital transmission chains. For example, for the Turbo decoder based on the product code DSC (21.11)² with a quantization of 5 bits and for one complete iteration, the results show the possibility of integration of our entire turbo decoder on a single chip, with lower latency at 0.23 microseconds and data rate greater than 500 Mb/s.

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3

Islam, MS, MA Quaium, M. Morshed, and RC Roy. "Hardware implementation issues of turbo decoders." Bangladesh Journal of Scientific and Industrial Research 47, no. 3 (December 21, 2012): 327–32. http://dx.doi.org/10.3329/bjsir.v47i3.13068.

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This paper gives a general overview of the implementation aspects of turbo decoders. Although the parallel architecture of the turbo code is emphasized, the serial concatenated convolutional codes for the turbo decoder are discussed too. Considering the general structure of iterative decoders, the main features of the soft input and soft output algorithm, which are the heart of a turbo decoder, are observed. The efficient parallel architectures of turbo decoders are shown which allow high speed implementation. Apart from these, implementation aspects like quantization issues and stopping rules to increase the throughput as well as an evaluation of the various turbo decoders are discussed. Finally, we suggest a number of solutions to overcome the implementation issues as well as the complexities without affecting the high throughput rate. DOI: http://dx.doi.org/10.3329/bjsir.v47i3.13068 Bangladesh J. Sci. Ind. Res. 47(3), 327-332 2012

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4

Wangrok Oh and Kyungwhoon Cheun. "Turbo decoder." IEEE Communications Letters 4, no. 8 (August 2000): 255–57. http://dx.doi.org/10.1109/4234.864186.

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5

Maity, Niladri Pratap, and Reshmi Maity. "Low Power Design of near Shannon Limit Coding: Turbo Codes." Advanced Materials Research 433-440 (January 2012): 7213–17. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.7213.

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In this paper secure channel coding schemes based on Turbo Codes are suggested and implemented. The design of encoder using Recursive Systematic Code (RSC) with puncturing techniques is presented. Component decoders are implemented by Log-Maximum-a-Posteriori (Log-MAP) algorithm and thereafter implementation of overall turbo decoder is illustrated in detail. Finally we have investigated low power design technique of the turbo decoder design with variable iteration techniques.

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6

Lehnigk-Emden, T., U. Wasenmüller, C. Gimmler, and N. Wehn. "Analysis of iteration control for turbo decoders in turbo synchronization applications." Advances in Radio Science 7 (May 18, 2009): 139–44. http://dx.doi.org/10.5194/ars-7-139-2009.

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Abstract. Wireless data transmission results in frequency and phase offsets of the signal in the receiver. In addition, the received symbols are corrupted by noise. Therefore, synchronization and channel coding are vital parts of each receiver in digital communication systems. By combining the phase and frequency synchronization with an advanced iterative channel decoder (inner loop) e.g. turbo codes in an iterative way (outer loop), the communications performance can be further increased. This principle is referred to as turbo synchronization. The energy consumption and the peak throughput of the system depend on the number of iterations for both loops. An advanced iteration control can decrease the mean number of needed iterations by detecting correctly decoded blocks. This leads to a dramatic energy saving or to an increase of throughput. In this paper we present a new stopping criterion for decodable blocks for turbo decoding in interrelation with turbo synchronization. Furthermore the implementation complexity of the turbo decoder is shown on a Xilinx FPGA.

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7

Salmela, Perttu, Harri Sorokin, and Jarmo Takala. "A Programmable Max-Log-MAP Turbo Decoder Implementation." VLSI Design 2008 (December 22, 2008): 1–17. http://dx.doi.org/10.1155/2008/319095.

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In the advent of very high data rates of the upcoming 3G long-term evolution telecommunication systems, there is a crucial need for efficient and flexible turbo decoder implementations. In this study, a max-log-MAP turbo decoder is implemented as an application-specific instruction-set processor. The processor is accompanied with accelerating computing units, which can be controlled in detail. With a novel memory interface, the dual-port memory for extrinsic information is avoided. As a result, processing one trellis stage with max-log-MAP algorithm takes only 1.02 clock cycles on average, which is comparable to pure hardware decoders. With six turbo iterations and 277 MHz clock frequency 22.7 Mbps, decoding speed is achieved on 130 nm technology.

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8

MARTINA, MAURIZIO, MARIO NICOLA, and GUIDO MASERA. "VLSI IMPLEMENTATION OF WiMax CONVOLUTIONAL TURBO CODE ENCODER AND DECODER." Journal of Circuits, Systems and Computers 18, no. 03 (May 2009): 535–64. http://dx.doi.org/10.1142/s0218126609005241.

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A VLSI encoder and decoder implementation for the IEEE 802.16 WiMax convolutional turbo code is presented. Architectural choices employed to achieve high throughput, while granting a limited occupation of resources, are addressed both for the encoder and decoder side, including also the subblock interleaving and symbol selection functions specified in the standard. The complete encoder and decoder architectures, implemented on a 0.13 μm standard cell technology, sustain a decoded throughput of more than 90 Mb/s with a 200 MHz clock frequency. The encoder has the complexity of 9.2 kgate of logic and 187.2 kbit of memory, whereas the complete decoder requires 167.7 kgate and 1163 kbit.

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9

Yang, Le, Tianchun Ye, Bin Wu, and Ruiqi Zhang. "LTE turbo decoder design." Journal of Semiconductors 36, no. 7 (July 2015): 075003. http://dx.doi.org/10.1088/1674-4926/36/7/075003.

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10

Han, Jian Bing, Chen He, and Ran Zhen. "FPGA Implementation of High-Speed Memory Efficient Quasi-Cyclic LDPC Decoder." Applied Mechanics and Materials 380-384 (August 2013): 3328–31. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.3328.

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This paper introduces a new kind of decoder structure for FPGA implementation of high-speed memory efficient quasi-cyclic LDPC (QC-LDPC) decoder. The code structure, algorithm and hardware structure all adopt optimization design. The decoder adopts modified Turbo decoding algorithm and achieves a decoding throughput of 223 Mbps and frame size of 3,200 bits. The Xilinx Virtex-4 chip used by the decoder only takes up 71 KB memory and makes it exceeds other decoders in aspects of throughput and memory for FPGA implementation.

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11

Passas, Georgios, and Steven Freear. "VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders." Journal of Electrical and Computer Engineering 2012 (2012): 1–14. http://dx.doi.org/10.1155/2012/614259.

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The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO) unit, A-, B-, Γ-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-window-technique-based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures.

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12

Michel, H., and N. Wehn. "Turbo-decoder quantization for UMTS." IEEE Communications Letters 5, no. 2 (2001): 55–57. http://dx.doi.org/10.1109/4234.905934.

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13

Papaharalabos, S., P. Sweeney, B. G. Evans, and P. T. Mathiopoulos. "Improved performance SOVA turbo decoder." IEE Proceedings - Communications 153, no. 5 (2006): 586. http://dx.doi.org/10.1049/ip-com:20050247.

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14

Babar, Zunaira, Hung Viet Nguyen, Panagiotis Botsinis, Dimitrios Alanis, Daryus Chandra, Soon Xin Ng, Robert G. Maunder, and Lajos Hanzo. "Fully-Parallel Quantum Turbo Decoder." IEEE Access 4 (2016): 6073–85. http://dx.doi.org/10.1109/access.2016.2581978.

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15

Yang, Yarang, and Yunpeng Li. "Research and Implementation of Turbo Coding Technology in High-Speed Underwater Acoustic OFDM Communication." Journal of Robotics 2022 (March 15, 2022): 1–11. http://dx.doi.org/10.1155/2022/2576303.

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It is demonstrated that the fully parallel turbo decoding algorithm can achieve an approximate error correction decoding performance when 36 iterations are used and when the log-map algorithm with 6 iterations is used. By comparison, it is shown that it can achieve much higher decoding rates than the log-map algorithm for various frame lengths of LTE standard turbo codes at the cost of higher hardware resource requirements. According to the fully parallel turbo decoding algorithm, this paper proposes a scheme for implementing a fully parallel turbo decoder on FPGA, detailing the overall structure and processing of the decoder hardware implementation, the design of the algorithm block processing unit, and the interleaving module. The performance of the decoder is tested by fixed-point simulation for different frame lengths of turbo coding in LTE standard, and it is proved that the fully parallel turbo decoder can be applied to turbo coding of various frame lengths. Both simulation and experimental results show that the distributed cancellation method and the joint estimation cancellation method have good results for both time-domain impulse noise and large-amplitude single frequency noise cancellation, while the joint estimation cancellation method of large-amplitude single frequency noise cancellation first has better performance.

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16

Buckley, M. E., and S. B. Wicker. "A neural network for predicting decoder error in turbo decoders." IEEE Communications Letters 3, no. 5 (May 1999): 145–47. http://dx.doi.org/10.1109/4234.766850.

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17

Elukuru, Sujatha, SUBHAS CHENNAPALLI, and GIRIPRASAD MAHENDRA NANJAPPA. "A New VLSI Architecture for High-Performance Parallel Turbo Decoder." IIUM Engineering Journal 23, no. 2 (July 4, 2022): 125–37. http://dx.doi.org/10.31436/iiumej.v23i2.2272.

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Recent wireless communications demand maximum achievable data rates without intervention. The channel decoder in the physical layer would support such high data rates with a flexible hardware structure. The turbo channel decoder offers flexible hardware architecture and reliable decoding, but the turbo decoder design is complex and its hardware architecture consumes more power and area in a communication system. Hence, an optimized high-performance turbo decoder architecture with simplified QPP interleaver is needed for supporting various data rates. In this context, this article presents a new hardware architecture with a three-stage pipeline parallel turbo decoding process and each MAP decoder in the proposed parallel turbo decoder with a three-stage micro pipeline processing is presented. The proposed structure optimized the circuit complexity and improved the throughput through parallel pipeline decoding. Also, this article presents a simplified semi-recursive QPP interleaver, which avoids complex ‘mod‘ operations for a high-performance turbo decoder. The performance analysis has been done using Model sim, Xilinx Vivado design suite, and estimated performance analysis was observed on various 28 nm CMOS technology FPGAs and compared with the conventional designs. Analysis of the proposed design showed improvement in throughput up to 55.6% and a reduction in the power consumption up to 43% as compared to the recently reported architectures. ABSTRAK: Komunikasi tanpa wayar terkini menuntut kadar data maksimum yang boleh dicapai tanpa intervensi. Penyahkod saluran dalam lapisan fizikal akan menyokong kadar data yang tinggi dengan struktur perkakasan fleksibel. Penyahkod saluran turbo menawarkan seni bina perkakasan fleksibel dan penyahkodan yang boleh dipercayai. Tetapi, penyahkod turbo merupakan blok yang kompleks, lebih berkuasa dan menggunakan kawasan yang luas dalam sistem komunikasi. Oleh itu, seni bina penyahkod turbo optimum berprestasi tinggi dengan antara lembar QPP yang mudah diperlukan bagi menyokong pelbagai kadar data. Dalam konteks ini, kajian ini merupakan seni bina perkakas baru dengan proses penyahkod turbo selari bersama salur paip tiga peringkat dan setiap penyahkod MAP yang dicadangkan dalam penyahkod turbo selari bersama proses saluran paip mikro tiga peringkat dibentangkan. Struktur yang dicadangkan dapat mengurangkan kerumitan litar dan meningkatkan daya pemprosesan melalui penyahkodan saluran paip selari. Selain itu, kajian ini merupakan antara lembar mudah QPP rekursif, yang dapat mengelakkan operasi 'mod' yang kompleks bagi penyahkod turbo berprestasi tinggi. Analisis prestasi telah dilakukan menggunakan sim Model, reka bentuk suit Xilinx Vivado, dan analisis prestasi anggaran telah diperhatikan pada pelbagai teknologi FPGA CMOS 28 nm dan dibandingkan dengan reka bentuk konvensional. Analisis reka bentuk yang dicadangkan menunjukkan peningkatan sepanjang 55.6% dan pengurangan penggunaan kuasa sehingga 43% berbanding seni bina laporan terkini.

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18

Kienle, F., H. Michel, F. Gilbert, and N. Wehn. "Efficient MAP-algorithm implementation on programmable architectures." Advances in Radio Science 1 (May 5, 2003): 259–63. http://dx.doi.org/10.5194/ars-1-259-2003.

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Abstract. Maximum-A-Posteriori (MAP) decoding algorithms are important HW/SW building blocks in advanced communication systems due to their ability to provide soft-output informations which can be efficiently exploited in iterative channel decoding schemes like Turbo-Codes. Multi-standards demand flexible implementations on programmable platforms. In this paper we analyze a quantized turbo-decoder based on a Max-Log-MAP algorithm with Extrinsic Scaling Factor (ESF). Its communication performance approximate to a Turbo-Decoder with a Log-MAP algorithm and is less sensitive to quantization effects. We present Turbo-Decoder implementations on state-of-the-art DSPs and show that only a Max-Log-MAP implementation fulfills a throughput requirement of ~2 Mbit/s. The negligible overhead for the ESF implementation strengthen the use of Max-Log-MAP with ESF implementation on programmable platforms.

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19

Bogawar, Mrs K. M., Ms Sharda Mungale, and Dr Manish Chavan. "Implementation of Turbo Encoder and Decoder." International Journal of Engineering Trends and Technology 8, no. 2 (February 25, 2014): 73–76. http://dx.doi.org/10.14445/22315381/ijett-v8p214.

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20

Chuah, T. C., and C. H. Pu. "Serial turbo decoder for robust communication." Electronics Letters 41, no. 7 (2005): 427. http://dx.doi.org/10.1049/el:20057361.

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21

Sun, Yang, and Joseph R. Cavallaro. "A Flexible LDPC/Turbo Decoder Architecture." Journal of Signal Processing Systems 64, no. 1 (April 9, 2010): 1–16. http://dx.doi.org/10.1007/s11265-010-0477-6.

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22

Shrimali, Yanita, Janki Ballabh Sharma, and R. S. Meena. "VHDL Implementation of low power turbo coded OFDM physical layer for wireless communication." International Journal of Engineering & Technology 7, no. 4.5 (September 22, 2018): 665. http://dx.doi.org/10.14419/ijet.v7i4.5.25054.

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Orthogonal Frequency Division Multiplexing (OFDM) is exceptionally favored system for rapid information transmission over remote channel. In this paper, VHDL implementation of low power turbo-coded OFDM (TCOFDM) Physical layer architecture is presented. In this architecture a low power memory-less pipelined FFT processor and Log-map turbo encoder/decoders are used to provide high throughput and lower complexity. Log-map turbo decoder provides high speed with good error correction capacity, while FFT/IFFT processor with single delay feedback (SDF) memory less architecture provide improved area and power efficiency. Proposed TCOFDM system is implemented using Xilinx ISE Design suite in the simulation results shows that the proposed scheme is having low power, high speed, high throughput and smaller area in comparison to other schemes.

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23

Weithoffer, Stefan, and Norbert Wehn. "Where to go from here? New cross layer techniques for LTE Turbo-Code decoding at high code rates." Advances in Radio Science 16 (September 4, 2018): 77–87. http://dx.doi.org/10.5194/ars-16-77-2018.

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Abstract. The wide range of code rates and code block sizes supported by todays wireless communication standards, together with the requirement for a throughput in the order of Gbps, necessitates sophisticated and highly parallel channel decoder architectures. Code rates specified in the LTE standard, which uses Turbo-Codes, range up to r=0.94 to maximize the information throughput by transmitting only a minimum amount of parity information, which negatively impacts the error correcting performance. This especially holds for highly parallel hardware architectures. Therefore, the error correcting performance must be traded-off against the degree of parallel processing. State-of-the-art Turbo-Code decoder hardware architectures are optimized on code block level to alleviate this trade-off. In this paper, we follow a cross-layer approach by combining system level knowledge about the rate-matching and the transport block structure in LTE with the bit-level technique of on-the-fly CRC calculation. Thereby, our proposed Turbo-Code decoder hardware architecture achieves coding gains of 0.4–1.8 dB compared to state-of-the-art accross a wide range of code block sizes. For the fully LTE compatible Turbo-Code decoder, we demonstrate a negligible hardware overhead and a resulting high area and energy efficiency and give post place and route synthesis numbers.

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24

Obiedat, Esam A., and Lei Cao. "Turbo Decoder for Low-Power Ultrawideband Communication Systems." International Journal of Digital Multimedia Broadcasting 2008 (2008): 1–7. http://dx.doi.org/10.1155/2008/897069.

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A new method to reduce the computational complexity of the turbo decoding in ultrawideband (UWB) orthogonal frequency division multiplexing (OFDM) system is proposed. Existing stopping techniques for turbo decoding process using constrained decoding assume fixed signal-to-noise ratio (SNR) for all the OFDM symbol bits so they fail to yield an acceptable bit-error rate (BER) performance in multicarrier systems. In this paper, we propose a bit-level stopping technique for turbo decoding process based on the constrained decoding method. In this technique, we combine the cyclic redundancy check (CRC) with an adaptive threshold on the log likelihood ratio (LLR) on each subcarrier to detect for convergence. The threshold is adaptive in the sense that the threshold on the LLR of a bit is determined by the average SNR of the OFDM symbol and the channel gain of the transmission subcarrier. Results show that when the channel state information (CSI) is used to determine the threshold on LLR, the stopping technique can reduce the computational complexity by about 0.5–2.5 equivalent iterations compared to GENIE turbo without degradation in the BER performance.

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25

Sah, Dhaneshwar. "Iterative Decoding of Turbo Codes." Journal of Advanced College of Engineering and Management 3 (January 10, 2018): 15. http://dx.doi.org/10.3126/jacem.v3i0.18810.

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<p><strong> </strong>This paper presents a Thesis which consists of a study of turbo codes as an error-control Code and the software implementation of two different decoders, namely the Maximum a Posteriori (MAP), and soft- Output Viterbi Algorithm (SOVA) decoders. Turbo codes were introduced in 1993 by berrouet at [2] and are perhaps the most exciting and potentially important development in coding theory in recent years. They achieve near- Shannon-Limit error correction performance with relatively simple component codes and large interleavers. They can be constructed by concatenating at least two component codes in a parallel fashion, separated by an interleaver. The convolutional codes can achieve very good results. In order of a concatenated scheme such as a turbo codes to work properly, the decoding algorithm must affect an exchange of soft information between component decoders. The concept behind turbo decoding is to pass soft information from the output of one decoder to the input of the succeeding one, and to iterate this process several times to produce better decisions. Turbo codes are still in the process of standardization but future applications will include mobile communication systems, deep space communications, telemetry and multimedia. Finally, we will compare these two algorithms which have less complexity and which can produce better performance.</p><p><strong>Journal of Advanced College of Engineering and Management</strong>, Vol.3, 2017, Page: 15-30</p>

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26

Al-Dweik, A., H. Mukhtar, E. Alsusa, and J. Dias. "Ultra-Light Decoder for Turbo Product Codes." IEEE Communications Letters 22, no. 3 (March 2018): 446–49. http://dx.doi.org/10.1109/lcomm.2017.2781223.

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27

Boyer, Pete, and Arthur Giordano. "Turbo decoder SNR estimation with RAKE reception." IEEE Transactions on Communications 57, no. 2 (February 2009): 430–39. http://dx.doi.org/10.1109/tcomm.2009.02.050081.

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28

Al-Dweik, A., S. Le Goff, and B. Sharif. "A Hybrid Decoder for Block Turbo Codes." IEEE Transactions on Communications 57, no. 5 (May 2009): 1229–32. http://dx.doi.org/10.1109/tcomm.2009.05.070107.

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29

Regalia, Phillip A., and John MacLaren Walsh. "Optimality and Duality of the Turbo Decoder." Proceedings of the IEEE 95, no. 6 (June 2007): 1362–77. http://dx.doi.org/10.1109/jproc.2007.896495.

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30

Jose A, Liji, and Sethu Raj. "Low Complexity Turbo Decoder with ACS Unit." International Journal of Engineering Trends and Technology 36, no. 8 (June 25, 2016): 446–51. http://dx.doi.org/10.14445/22315381/ijett-v36p280.

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31

Martina, M., M. Nicola, and G. Masera. "A Flexible UMTS-WiMax Turbo Decoder Architecture." IEEE Transactions on Circuits and Systems II: Express Briefs 55, no. 4 (April 2008): 369–73. http://dx.doi.org/10.1109/tcsii.2008.919510.

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32

Karthik, K. V., and Naveen I.G. "Low Complexity Decoder for CCSDS Turbo codes." IOSR Journal of Electronics and Communication Engineering 9, no. 4 (2014): 19–23. http://dx.doi.org/10.9790/2834-09431923.

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33

Jung, P. "Novel low complexity decoder for turbo-codes." Electronics Letters 31, no. 2 (January 19, 1995): 86–87. http://dx.doi.org/10.1049/el:19950069.

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34

Schurgers, C., F. Catthoor, and M. Engels. "Memory optimization of MAP turbo decoder algorithms." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9, no. 2 (April 2001): 305–12. http://dx.doi.org/10.1109/92.924051.

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35

Kwonhue Choi. "Residual Frequency Offset Compensation-Embedded Turbo Decoder." IEEE Transactions on Vehicular Technology 57, no. 5 (September 2008): 3211–17. http://dx.doi.org/10.1109/tvt.2007.914482.

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36

Vogt, J., and A. Finger. "Improving the max-log-MAP turbo decoder." Electronics Letters 36, no. 23 (2000): 1937. http://dx.doi.org/10.1049/el:20001357.

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37

Souza, Ilan Schnitman, and V. T. Dos Reis. "A VLSI Design for the LTE Turbo Decoder." Journal of Integrated Circuits and Systems 7, no. 1 (December 27, 2012): 16–22. http://dx.doi.org/10.29292/jics.v7i1.352.

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Due to the need of high performance, new wireless telecommunications standards such asWIMAX and LTE are using turbo-codes as a forward error correction (FEC) choice.This design targets either a self-contained IP (Intellectual Property) or integration into the physical layer project. This work presents all steps for the implementation of an LTE standard turbo decoder: from algorithm modeling in high level programming language to architecture using a sliding window approach seeking throughput needed, getting into physical implementation at TSMC 65nm. Each aspect of the specification and performance were analyzed in their proper stages.

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38

Kim, Jung-Woo, and Won-Sik Yoon. "Turbo code with iterative channel estimator using soft-output of turbo decoder." Electronics Letters 36, no. 18 (2000): 1560. http://dx.doi.org/10.1049/el:20001081.

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39

Dong, Jie, Yong Li, Rui Liu, Taolin Guo, and Francis C. M. Lau. "Efficient Decoder for Turbo Product Codes Based on Quadratic Residue Codes." Electronics 11, no. 21 (November 3, 2022): 3598. http://dx.doi.org/10.3390/electronics11213598.

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In this letter, we study turbo product codes with quadratic residue codes (called QR-TPCs) as the component codes. We propose an efficient decoder based on Chase-II algorithm with two convergence conditions for the iterative decoding of QR-TPCs. For each row and column, the Chase-II decoder will stop immediately when one of the conditions is met. The simulation results show that the proposed algorithm has a lower computational complexity compared with existing decoding methods. Moreover, a comparison with 5G low-density parity-check codes shows that the proposed turbo product codes have better performance for short code lengths.

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40

Alebady, Wallaa Yaseen, and Ahmed Abdulkadhim Hamad. "Turbo polar code based on soft-cancelation algorithm." Indonesian Journal of Electrical Engineering and Computer Science 26, no. 1 (April 1, 2022): 521. http://dx.doi.org/10.11591/ijeecs.v26.i1.pp521-530.

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Since the first polar code of Arikan, <span>the research field of polar codes has been continuously active. Improving the performance of finite-code-length polar codes is the central point of this field. In this paper, the parallel concatenated systematic turbo polar code (PCSTPC) model has been proposed to improve the polar codes performance in a finite-length regime. On the encoder side, two systematic polar encoders are used as constituent encoders. While on the decoder side, two single iteration soft-cancelation (SCAN) decoders are used as soft-in-soft-out (SISO) algorithms inside the iterative decoding algorithm of the parallel concatenated systematic turbo polar code (PCSTPC). As compared to the optimized turbo polar code with SCAN and BP decoders, the proposed model has about 0.2 dB and 0.48 dB gains at BER=10<sup>(-4)</sup>, respectively, in addition to 0.1 dB, 0.31 dB, and 0.72 dB gains over the TPC-SSCL32, TPC-SSCL16, and TPC-SSCL8 models, respectively. Moreover, the proposed model offers less complexity in comparison with other models, therefore requiring less memory and time resources.</span>

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41

Adamu, Mohammed Jajere, Li Qiang, Rabiu Sale Zakariyya, Charles Okanda Nyatega, Halima Bello Kawuwa, and Ayesha Younis. "An Efficient Turbo Decoding and Frequency Domain Turbo Equalization for LTE Based Narrowband Internet of Things (NB-IoT) Systems." Sensors 21, no. 16 (August 8, 2021): 5351. http://dx.doi.org/10.3390/s21165351.

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This paper addresses the main crucial aspects of physical (PHY) layer channel coding in uplink NB-IoT systems. In uplink NB-IoT systems, various channel coding algorithms are deployed due to the nature of the adopted Long-Term Evolution (LTE) channel coding which presents a great challenge at the expense of high decoding complexity, power consumption, error floor phenomena, while experiencing performance degradation for short block lengths. For this reason, such a design considerably increases the overall system complexity, which is difficult to implement. Therefore, the existing LTE turbo codes are not recommended in NB-IoT systems and, hence, new channel coding algorithms need to be employed for LPWA specifications. First, LTE-based turbo decoding and frequency-domain turbo equalization algorithms are proposed, modifying the simplified maximum a posteriori probability (MAP) decoder and minimum mean square error (MMSE) Turbo equalization algorithms were appended to different Narrowband Physical Uplink Shared Channel (NPUSCH) subcarriers for interference cancellation. These proposed methods aim to minimize the complexity of realizing the traditional MAP turbo decoder and MMSE estimators in the newly NB-IoT PHY layer features. We compare the system performance in terms of block error rate (BLER) and computational complexity.

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Lee, Won-Ho, Heemin Park, and Chong S. Rim. "Design of a High Throughput Parallel Turbo Decoder." Journal of the Institute of Electronics Engineers of Korea 50, no. 11 (November 25, 2013): 50–57. http://dx.doi.org/10.5573/ieek.2013.50.11.050.

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Kadage, Anushka, and Priyatam Kumar. "Turbo Decoder Performance Analysis in Multiuser LTE+ Systems." Journal of Communication Engineering and Its Innovations 7, no. 1 (March 16, 2021): 25–33. http://dx.doi.org/10.46610/jocei.2021.v07i01.005.

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Kim, Young-Sup, and Sung-Woong Ra. "A Simple Efficient Stopping Criterion for Turbo Decoder." ETRI Journal 28, no. 6 (December 7, 2006): 790–92. http://dx.doi.org/10.4218/etrij.06.0206.0113.

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Kalyani, K., A. Sakthi Amutha Var, and S. Rajaram. "FPGA Implementation of Turbo Decoder for LTE Standard." Journal of Artificial Intelligence 6, no. 1 (December 15, 2012): 22–32. http://dx.doi.org/10.3923/jai.2013.22.32.

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Zeng, Jianmin, Chubin Wu, Zhang Zhang, Xin Cheng, Guangjun Xie, Jun Han, Xiaoyang Zeng, and Zhiyi Yu. "A multi-core-based heterogeneous parallel turbo decoder." IEICE Electronics Express 14, no. 18 (2017): 20170768. http://dx.doi.org/10.1587/elex.14.20170768.

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Liu, Wei, Shuming Chen, Hu Chen, Yaohua Wang, Sheng Liu, Kai Zhang, and Xi Ning. "A novel QPP interleaver for parallel turbo decoder." IEICE Electronics Express 10, no. 8 (2013): 20120795. http://dx.doi.org/10.1587/elex.10.20120795.

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Howlader, M. M. K., and B. D. Woerner. "Decoder-assisted frame synchronisation for turbo-coded systems." Electronics Letters 37, no. 6 (2001): 362. http://dx.doi.org/10.1049/el:20010237.

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Vishvaksen, Kuttathatti Srinivas, R. Seshasayan, and D. V. Hariprasad. "FPGA Implementation of Turbo Decoder for IDMA Scheme." Research Journal of Information Technology 3, no. 2 (February 1, 2011): 104–13. http://dx.doi.org/10.3923/rjit.2011.104.113.

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El Gamal, H., and A. R. Hammons. "Analyzing the turbo decoder using the Gaussian approximation." IEEE Transactions on Information Theory 47, no. 2 (2001): 671–86. http://dx.doi.org/10.1109/18.910581.

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