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Journal articles on the topic 'Wafer manufacturing process'

Author: Grafiati

Published: 4 June 2021

Last updated: 6 February 2022

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1

Lee, Seungchul, and Jun Ni. "Genetic Algorithm for Job Scheduling with Maintenance Consideration in Semiconductor Manufacturing Process." Mathematical Problems in Engineering 2012 (2012): 1–16. http://dx.doi.org/10.1155/2012/875641.

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This paper presents wafer sequencing problems considering perceived chamber conditions and maintenance activities in a single cluster tool through the simulation-based optimization method. We develop optimization methods which would lead to the best wafer release policy in the chamber tool to maximize the overall yield of the wafers in semiconductor manufacturing system. Since chamber degradation will jeopardize wafer yields, chamber maintenance is taken into account for the wafer sequence decision-making process. Furthermore, genetic algorithm is modified for solving the scheduling problems i

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2

Hagimoto, Yoshiya, Hayato Iwamoto, Yasushi Honbe, Takuro Fukunaga, and Hitoshi Abe. "Defects of Silicon Substrates Caused by Electro-Static Discharge in Single Wafer Cleaning Process." Solid State Phenomena 145-146 (January 2009): 185–88. http://dx.doi.org/10.4028/www.scientific.net/ssp.145-146.185.

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While batch wafer cleaning processes have been conventionally used in the semiconductor manufacturing for many years, the use of single wafer cleaning processes in the manufacturing has recently become increasingly widespread. Single wafer cleaning processes have the advantages of reducing particle and metal contamination, however, electric charge or electrostatic discharge phenomena occurring in these processes causes serious problems such as device destruction through insulation failure and circuit disconnection [1,2]. Well-known examples are the breakdown of the ultra-thin gate oxide and th

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3

KANNO, Itaru. "Clean Technology Supporting Semiconductor Manufacturing Process. Wafer Cleaning Technology." Journal of the Surface Finishing Society of Japan 50, no. 10 (1999): 861–66. http://dx.doi.org/10.4139/sfj.50.861.

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Strothmann, Tom, Damien Pricolo, Seung Wook Yoon, and Yaojian Lin. "A Flexible Manufacturing Method for Wafer Level Packages." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, DPC (2014): 000815–29. http://dx.doi.org/10.4071/2014dpc-tp21.

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The demand for Wafer Level Chip Scale Packages (WLCSP) has experienced tremendous growth due to the surge in demand for advanced mobile products. The increased demand is seen for both 200mm wafers and 300mm wafers, however a significant segment of the market continues to be driven by 200mm designs. The infrastructure capacity supporting 200mm WLCSP has been stressed as a result of the mature status of 200mm technology and the rate of conversion of alternative package formats to WLCSP. This creates a dilemma for WLP service providers because adding 200mm capacity continues to require a signific

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Tian, Y. B., Li Bo Zhou, Jun Shimizu, H. Sato, and Ren Ke Kang. "A Novel Single Step Thinning Process for Extremely Thin Si Wafers." Advanced Materials Research 76-78 (June 2009): 434–39. http://dx.doi.org/10.4028/www.scientific.net/amr.76-78.434.

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The demand for extremely-thin Si wafers is expanding. Current manufacturing technologies are meeting great challenges with the continuous decrease in Si wafer thickness. In this study, a novel single step thinning process for extremely thin Si wafers was put forward by use of an integrated cup grinding wheel (ICGW) in which diamond segments and chemo-mechanical grinding (CMG) segments are alternately allocated along the wheel periphery. The basic machining principle and key technologies were introduced in detail. Grinding experiments were performed on 8-in. Si wafers with a developed ICGW to e

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Saidin, Mohd Hazmuni, and Norlena Hasnan. "HUMAN ERROR REDUCTION PROGRAM THROUGH CANONICAL ACTION RESEARCH (CAR) IN WAFER FABRICATION MANUFACTURING FACILITY." Journal of Technology and Operations Management 14, Number 1 (2019): 8–18. http://dx.doi.org/10.32890/jtom.14.1.2.

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In a wafer fabrication manufacturing facility, thousands of wafers are being processed daily. To manufacture the product, the wafers need to go thru hundreds of steps according to the technologies required. The cycle time to complete a standard product ranges from few weeks to few months, depends on the complexity of the technologies. Due to the difficulty and the complexity of the product, Computer Integrated Manufacturing system (CIM), is widely used as a manufacturing platform. As such, all the processes, equipment and wafers are fully integrated. Nevertheless, not all processes could be pr

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7

Shelton, Doug. "Advanced Manufacturing Technology for Fan-Out Wafer Level Packaging." International Symposium on Microelectronics 2015, no. 1 (2015): 000251–55. http://dx.doi.org/10.4071/isom-2015-wa34.

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Advanced process technology is required to develop and enable mass production of Fan-Out Wafer-Level Packaging (FOWLP) solutions for high-density 3D and 2.5D packaging. Canon has identified key challenges that must be solved for successful implementation of high-density integration technologies and has developed key technology for Canon Litho Systems to support the most challenging processes. In this paper, Canon will present process optimization results for high-resolution patterning of wafers across large topography as well as solutions that enable litho systems to compensate for FOWLP grid

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8

Hünten, Martin, Daniel Hollstegge, and Fritz Klocke. "Wafer Level Glass Molding." Key Engineering Materials 523-524 (November 2012): 1001–5. http://dx.doi.org/10.4028/www.scientific.net/kem.523-524.1001.

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Manufacturing of micro optical components is approached with many different technologies. In this paper it is presented how the precision glass molding process is enabled to manufacture micro optical components made out of glass. In comparison to the existing glass molding technology the new approach aims for molding entire glass wafers including multiple micro optical components. It is explained which developments in the filed of simulation, mold manufacturing and molding were accomplished in order to enable the precision glass molding on wafer scale.

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9

KIM, Jongwon. "New Wafer Alignment Process Using Multiple Vision Method for Industrial Manufacturing." Electronics 7, no. 3 (2018): 39. http://dx.doi.org/10.3390/electronics7030039.

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10

Tuck-Boon Chan, A. Pant, Lerong Cheng, and P. Gupta. "Design-Dependent Process Monitoring for Wafer Manufacturing and Test Cost Reduction." IEEE Transactions on Semiconductor Manufacturing 25, no. 3 (2012): 447–59. http://dx.doi.org/10.1109/tsm.2012.2196709.

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11

Hwang, Sung Chul, Jong Koo Won, Jung Taik Lee, and Eun Sang Lee. "A Study on Statistical Analysis of Si-Wafer Polishing Process for the Optimum Polishing Condition." Key Engineering Materials 389-390 (September 2008): 493–97. http://dx.doi.org/10.4028/www.scientific.net/kem.389-390.493.

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As the level of Si-wafer surface directly affects device line-width capability, process latitude, yield, and throughput in fabrication of microchips, it needs to have ultra precision surface and flatness. Polishing is one of the important processing having influence on the surface roughness in manufacturing of Si-wafers. The surface roughness in wafer polishing is mainly affected by the many process parameters. For decreasing the surface roughness, the control of polishing parameters is very important. In this paper, the optimum condition selection of ultra precision wafer polishing and the ef

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12

Turner, K. T., and S. M. Spearing. "Mechanics of direct wafer bonding." Proceedings of the Royal Society A: Mathematical, Physical and Engineering Sciences 462, no. 2065 (2005): 171–88. http://dx.doi.org/10.1098/rspa.2005.1571.

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Direct wafer bonding is a manufacturing process that is used in the fabrication of electronic, optical and mechanical microsystems. The initial step in the process requires that the wafers are sufficiently smooth, flat and compliant such that short-range surface forces can elastically deform the wafers and bring the surfaces into complete contact. Analytical and computational mechanics models of this adhesion process as well as experiments that validate these models are presented in this work. An energy-based analysis is used to develop the models that allow acceptable limits of wafer-scale fl

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13

Teixeira, Jorge, and Mário Ribeiro. "Method to measure wafer stiffness in Fan-Out Wafer Level Package." International Symposium on Microelectronics 2012, no. 1 (2012): 000720–28. http://dx.doi.org/10.4071/isom-2012-wa62.

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Wafer level packaging is an important development trend for IC package design. One of the emerging variants is the fan-out wafer level package (FO-WLP), namely Embedded Wafer Level Ball Array (eWLB) [1]. In the eWLB process, singulated known good dies are placed into a “reconstituted wafer” with enough space around each chip to accommodate second-level connections. Space between dies is filled with molding compound, this construction results in a plurality of microelectronic elements triggering a particular mechanical behavior.[1]. Two of the main characteristics associated to the handling and

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14

Weng, Chun Jen. "Etching Effects of Nanotechnology Fabrication on CMOS Transistor Gate Wafer Manufacturing Process Integration." Advanced Materials Research 154-155 (October 2010): 938–41. http://dx.doi.org/10.4028/www.scientific.net/amr.154-155.938.

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As wafer nanotechnology gate is scaling down, the fabrication technology of gate spacer for transistor becomes more critical in manufacturing processes. Because wafer fabrication technologies, sidewall spacers play an important role in the control of short channel effects by offsetting ion implantation profiles from the edge of the gate. The present study is to overcome the fabrication processes limitations and proposed modified feasible etching processes integration on the formation processing for complementary metal oxide semiconductor nanofabrication process of gate spacer technology and el

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15

Ko, Po Sheng, and Cheng Chung Wu. "Manufacturing Process Planning to Evaluation on Failure Causes for Lithography Machine: Analytic Hierarchy Process." Advanced Materials Research 213 (February 2011): 450–53. http://dx.doi.org/10.4028/www.scientific.net/amr.213.450.

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This study conducted hierarchical analysis on the evaluation item of the stability index of the lithography machine, and established a set of evaluation mechanism for failure prediction, in order to provide references and indicators of troubleshooting for lithography machine. The results showed, when the lithography machine is out of order, the possible failure causes are mainly be found based on the past experiences. Moreover, engineers’ skills in maintenance of lithography machine should be also considered. It is clear that, technology-centered is the current trend in today's semiconductor t

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Pabo, Eric F., Garrett Oakes, Ron Miller, et al. "Enabling Wafer Level Processes for CIS Manufacturing." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, DPC (2010): 002393–413. http://dx.doi.org/10.4071/2010dpc-tha36.

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CMOS (Complimentary Metal Oxide Semiconductor) Image Sensors have become ubiquitous, appearing in cars, cell phones, toys and many other devices used in every day life. The primary reason for this increasing presence of CIS (CMOS Image Sensors) is the continual improvement of the performance to cost ratio of these devices. The drivers behind this are the advancements of CMOS image sensor technology such as improved signal to noise ratio as well as advancements in wafer level processing technology related to 3D packaging. Numerous process developments related to both the electrical and optical

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17

Kim, Sung Hyun, Sang Gyun Lee, Seung Gun Choi, et al. "A Study on the Characteristics of a Wafer Final Polishing Process at Various Machining and Temperature Variation." Advanced Materials Research 565 (September 2012): 296–301. http://dx.doi.org/10.4028/www.scientific.net/amr.565.296.

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The polishing is one of the important methods in manufacturing of silicon wafer and in thinning of completed device wafer. Generally, getting a flat surface such as a mirror is the purpose of the process. The wafer surface roughness is affected by many variables such as the characteristics of the carrier head unit, operation, speed, the pad and slurry temperature. Optimum process conditions for experimental temperature, down-force, slurry ratio are investigated, time is used as a fixed factor. This study will report the evaluation on surface of wafer by dependent of varying platen, chuck rpm,

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18

HATTORI, Hisashi. "Clean Technology Supporting Semiconductor Manufacturing Process. Defect Inspection System of Wafer Surface." Journal of the Surface Finishing Society of Japan 50, no. 10 (1999): 879–86. http://dx.doi.org/10.4139/sfj.50.879.

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19

Chen, Po-Ying, Ming-Hsing Tsai, Wen-Kuan Yeh, Ming-Haw Jing, and Yukon Chang. "Relationship between wafer fracture reduction and controlling during the edge manufacturing process." Microelectronic Engineering 87, no. 10 (2010): 1809–15. http://dx.doi.org/10.1016/j.mee.2009.08.019.

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20

Tay, Francis E. H., Loo Hay Lee, and Lixin Wang. "Production scheduling of a MEMS manufacturing system with a wafer bonding process." Journal of Manufacturing Systems 21, no. 4 (2002): 287–301. http://dx.doi.org/10.1016/s0278-6125(02)80168-6.

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21

Yang, Xu, Xiaozhe Yang, Kentaro Kawai, Kenta Arima, and Kazuya Yamamura. "Novel SiC wafer manufacturing process employing three-step slurryless electrochemical mechanical polishing." Journal of Manufacturing Processes 70 (October 2021): 350–60. http://dx.doi.org/10.1016/j.jmapro.2021.08.059.

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22

Hornung, Michael. "Lithography for Wafer Level Packaging for LED Manufacturing." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, DPC (2013): 001253–76. http://dx.doi.org/10.4071/2013dpc-wa33.

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Since LED became an attractive alternative for general lighting, the market demand for higher brightness, higher efficiency and lower costs was the motivation for improving the LED technology. Locking in on the LED manufacturing process, most steps are on die-level after chip singularizing and therefore the costs are dominated by the huge number of dies which could often reach several thousand dies on one wafer. It's obvious that WLP has a clear benefit for LED packaging and it is also the path to success for LED manufacturing. Moreover, it also allows the implementation and integration of add

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23

Martins, Alberto, Nelson Pinho, and Harald Meixner. "SYSTEMATIC FEEDBACK LOOP FOR SILICON DIE PICK&PLACE PROCESS IN RECONSTITUTED FAN-OUT EWLB WAFERS IN HIGH VOLUME PRODUCTION." International Symposium on Microelectronics 2012, no. 1 (2012): 000201–8. http://dx.doi.org/10.4071/isom-2012-ta63.

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NANIUM S.A. Portugal recently started producing eWLB fan-out [1][2] wafer level packaging technology on 300mm reconstituted wafers. Initial setup of this process demonstrated that the stable die Pick&Place accuracy plays a key role for product feasibility. In the subsequent volume production ramp-up it became apparent that the dynamic expansion of molded eWLB wafers, caused by thermal stress and CTE mismatch throughout the thin film redistribution and passivation layer up to bumping and reflow manufacturing processes requires a very tight die position monitoring over the complete wafer dia

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24

Li, Wei, Cheng Jin, and Xiao Zhen Hu. "A Study on Pressure Stability in Double-Sided Polishing Process." Advanced Materials Research 126-128 (August 2010): 64–69. http://dx.doi.org/10.4028/www.scientific.net/amr.126-128.64.

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How to achieve the precision double-sided polishing process is a important issue for wafer manufacturing, it depends on machining condition such as machining environment, polishing speed, polishing operation mode, polishing pressure, polishing fluid etc. The key factor to the wafer surface quality is the stability of the polishing pressure. This paper analyzes the impact of double-sided polishing pressure in polishing process, using AMESim software to simulate the pressure standard deviation’s changes under diffrent polishing pressures, and carries out some experiments to identify the impact o

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Kozaczek, Kris J. "Texture Control in Manufacturing of ULSI Devices." Solid State Phenomena 105 (July 2005): 101–6. http://dx.doi.org/10.4028/www.scientific.net/ssp.105.101.

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The rapid adoption of damascene copper processing has brought about an increased need to understand and control microstructure in the barrier, seed and electroplated copper layers during manufacture. We will discuss an in-line, x-ray diffraction based metrology for rapidly characterizing thin film polycrystalline microstructures on 300 mm silicon wafers in terms of crystallographic texture, phase composition, and film thickness. The microstructure control plays an increasingly important role in improving the performance and reliability of ULSI devices that use the damascene copper technology a

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26

Zhou, Bing Hai. "Elman Neural Network–Based Dynamic Scheduling of Wafer Photolithography Process." Advanced Materials Research 186 (January 2011): 36–40. http://dx.doi.org/10.4028/www.scientific.net/amr.186.36.

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Photolithography area is usually a bottleneck area in a semiconductor wafer manufacturing system (SWMS). It is difficult to schedule photolithography area on real-time optimally. Here, an Elman neural network (ENN)-based dynamic scheduling method is proposed. An ENN-based sample learning algorithm is proposed for selecting best combination of scheduling rules. To illustrate the feasibility and practicality of the presented method, the simulation experiment is developed. A numerical example is use to evaluate the proposed method. Results of simulation experiments show that the proposed method i

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Chung, Chunhui, and Chien-Hong Lin. "Study on the performance of nanocomposite wire guides in wire sawing process." International Journal of Modern Physics B 32, no. 19 (2018): 1840077. http://dx.doi.org/10.1142/s0217979218400775.

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In semiconductor wafer manufacturing, wire sawing is the first machining process to slice an ingot into hundreds of wafers. The cutting tool is a tiny wire which is wound on the wire guides. The material of the wire guides is essential to stabilize the process and to control the wafer thickness. However, there are few studies on the materials and the properties of the wire guides. In order to enhance the performance of wire sawing, this study investigated wire sawing process with the guides made of polyurethane reinforced by nanoTiO2 (PU/TiO2) and nanographite (PU/graphite). The results show t

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Park, Heakyoung. "Sealing dispensing requirements to meet MEMS packaging and throughput impact." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, DPC (2013): 000535–70. http://dx.doi.org/10.4071/2013dpc-ta33.

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The MEMS industry has gained big momentum recently with significant unit growth, especially in the consumer market. While traditional MEMS devices like automotive accelerators have established high-volume manufacturing processes and packages with high reliability, most MEMS devices have been fragmented in packaging because of their unique requirements and small volumes, resulting in high packaging costs. In the cost-sensitive consumer market, devices such as MEMS microphones, accelerometers, and gyroscopes in mobile devices have rapidly increased their production volume and chased lower packag

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Zhu, Hanxiang, Jun Li, Liqiang Cao, Jia Cao, and Pengwei Chen. "Si-based Ka-band SIW band-pass filter using wafer level manufacturing process." IEICE Electronics Express 18, no. 1 (2021): 20200414. http://dx.doi.org/10.1587/elex.17.20200414.

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Roy, Rajiv, and Matt Wilson. "Solution for HVM TSV Etch Process." International Symposium on Microelectronics 2012, no. 1 (2012): 000844–47. http://dx.doi.org/10.4071/isom-2012-wp26.

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As the industry is getting their hands around processes critical to cost-effective and reliable TSV manufacturing a key enabler is process control through inspection and metrology. In working with the industry, Rudolph has developed a suite of solutions that incorporate inspection, metrology and software enabling rapid yield ramp. The solution set apply all the way from via etch to CMP, RLD, micro-bumping and all the way to Chip on Wafer mount and post-saw. Within the TSV process a challenging inspection is that of detecting defects after CMP and nail reveal. The bonded wafers are warped, ther

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Kim, Bong Ho, and Jin Goo Park. "Effect of FOUP Atmosphere Control on Process Wafer Integrity in Sub20 nm Device Fabrication." Solid State Phenomena 219 (September 2014): 256–59. http://dx.doi.org/10.4028/www.scientific.net/ssp.219.256.

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Defects could be generated on the wafers by the particle contamination, formation of organic residue, corrosion, native oxide growth on the surface and airborne molecular contaminants (AMC) [1] etc. These problems hinder the device performance and also can decrease the yield and productivity in the semiconductor manufacturing process. It could be resolved by various cleaning methods [2]. However, the results such as corrosion, native oxide growth on wafer and AMC deposition should be handled properly by N2 gas purge prevention method during the process or standby [3,4]. It should be implemente

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32

Tu, Ying Mei. "Throughput Estimation Model of Cluster Tool in Semiconductor Manufacturing." Key Engineering Materials 814 (July 2019): 196–202. http://dx.doi.org/10.4028/www.scientific.net/kem.814.196.

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Semiconductor manufacturing management system was developed and grown up over the past decades. In order to increase the product yield and enhance the production productivity, cluster tools became the main stream in modern wafer fabrication factories which occupies over 50% of production equipment. Generally, cluster tools are integrated by several components including robots, vacuum chambers (Load locks) and single-wafer process chambers in a module and can be treated as a small factory. The throughput estimation before recipe release is very difficult. However, it is necessary and important

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Li, Zhaozhi, Brian J. Lewis, Paul N. Houston, et al. "Wafer Level Assembly Technique Development for Fine Pitch Flip Chip 3D Die-to-Wafer Integration." International Symposium on Microelectronics 2010, no. 1 (2010): 000548–53. http://dx.doi.org/10.4071/isom-2010-wp1-paper3.

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Three Dimensional (3D) Packaging has become an industry obsession as the market demand continues to grow toward higher packaging densities and smaller form factor. In the meanwhile, the 3D die-to-wafer (D2W) packaging structure is gaining popularity due to its high manufacturing throughput and low cost per package. In this paper, the development of the assembly process for a 3D die-to-wafer packaging technology, that leverages the wafer level assembly technique and flip chip process, is introduced. Research efforts were focused on the high-density flip chip wafer level assembly techniques, as

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Couderc, Pascal. "Application of 3D PLUS WDoD technology for the manufacturing of electronic modules in implantable medical products." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, DPC (2017): 1–30. http://dx.doi.org/10.4071/2017dpc-ta2_presentation4.

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3D PLUS has patented an innovative 3D technology based on the stacking of Know Good Rebuilt Wafers with only Know Good Dies, named WDoDTM. The first 2D steps are those used by the manufacturers of Rebuilt Wafers with well-known eWLBTM technology:- Pick-Flip and Place of KGD from the die wafer on an thermal-release tape on a silicon carrier ( 300 or 200 mm diameter)- Compression molding with epoxy resin with silica fillers- Know Good Rebuilt Wafer grinding in order to decrease total thickness to 250 Âμm or less- Fan-out built-up with Redistribution layer process- This last step can be replaced

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KIM, SOOYOUNG, SEUNG-HEE YEA, and BOKANG KIM. "Shift scheduling for steppers in the semiconductor wafer fabrication process." IIE Transactions 34, no. 2 (2002): 167–77. http://dx.doi.org/10.1080/07408170208928859.

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Brandl, Elisabeth, Karine Abadie, Markus Wimplinger, et al. "Critical Process Parameters And Failure Analysis For Temporary Bonded Wafer Stacks." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, DPC (2016): 001255–76. http://dx.doi.org/10.4071/2016dpc-wp14.

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Temporary bonding is a ley process for almost any 3D integration scheme. It offers not only more stability during the thinning process but also allows handling for backside processing of thin wafers like interposers during subsequent process steps [1–2]. Although the temporary bonding technology is already used in high volume manufacturing and has proven high yield process, nevertheless, some limitation appears for some specific applications [3-4-5]. One critical failure origin is delamination, which can lead to wafer breakage and therefore yield loss. This separation of the device wafer and t

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Bao, Juncheng, Tomislav Markovic, Luigi Brancato, et al. "Novel Fabrication Process for Integration of Microwave Sensors in Microfluidic Channels." Micromachines 11, no. 3 (2020): 320. http://dx.doi.org/10.3390/mi11030320.

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This paper presents a novel fabrication process that allows integration of polydimethylsiloxane (PDMS)-based microfluidic channels and metal electrodes on a wafer with a micrometer-range alignment accuracy. This high level of alignment accuracy enables integration of microwave and microfluidic technologies, and furthermore accurate microwave dielectric characterization of biological liquids and chemical compounds on a nanoliter scale. The microfluidic interface between the pump feed lines and the fluidic channels was obtained using magnets fluidic connection. The tube-channel interference and

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XIANGDONG, WANG, and WANG SHOUJUE. "THE APPLICATION OF FEEDFORWARD NEURAL NETWORKS IN VLSI FABRICATION PROCESS OPTIMIZATION." International Journal of Computational Intelligence and Applications 01, no. 01 (2001): 83–90. http://dx.doi.org/10.1142/s1469026801000032.

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In this paper, we present a neural-based manufacturing process control system for semiconductor factories to improve the die yield. A model based on neural networks is proposed to simulate Very Large-Scale Integrated (VLSI) manufacturing process. Learning from the historical processing lists with Radial Basis Function (RBF), we simulate the functional relationship between the wafer probing parameters and the die yield. Then we use a gradient-descent method to search a set of 'optimal' parameters that lead to the maximum yield of the model. At last, we adjust the specification in the practical

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Seo, Kwang Min, Dae Heon Kim, Yu Jin Cho, and Tae Hyung Kim. "Effect of Nozzle Distance and Fluid Flow Rate in Jet Spray Wafer Cleaning Process." Solid State Phenomena 219 (September 2014): 128–30. http://dx.doi.org/10.4028/www.scientific.net/ssp.219.128.

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Recently the reduction of the devise sizes causing the semiconductor processes more complicated and becoming more and more sensitive to the particle contamination [1]. Numerous studies have been carried out to improve the device yield with high particle removal efficiency (PRE) and Wet cleaning process along with megasonic is one of the well-established techniques used for particle removal in the semiconductor industry [1, 2]. However as the pattern size is reduced bellow 60 nm this method is not effective to improve the PRE. Recently, two-flow jet spray cleaning process became popular in semi

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Strandjord, Andrew, Thorsten Teutsch, Axel Scheffler, et al. "Wafer Level Packaging of Compound Semiconductors." Journal of Microelectronics and Electronic Packaging 7, no. 3 (2010): 152–59. http://dx.doi.org/10.4071/imaps.263.

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The microelectronics industry has implemented a number of different wafer level packaging (WLP) technologies for high volume manufacturing, including: UBM deposition, solder bumping, wafer thinning, and dicing. These technologies were successfully developed and implemented at a number of contract manufacturing companies, and then licensed to many of the semiconductor manufacturers and foundries. The largest production volumes for these technologies are for silicon-based semiconductors. Continuous improvements and modifications to these WLP processes have made them compatible with the changes o

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OKUBO, Hitomi, Libo ZHOU, Jun SHIMIZU, and Hiroshi EDA. "Simulation on Planarization Process of Patterned Si Wafer : Improvements in accuracy of simulation model(M^4 processes and micro-manufacturing for science)." Proceedings of International Conference on Leading Edge Manufacturing in 21st century : LEM21 2005.2 (2005): 883–88. http://dx.doi.org/10.1299/jsmelem.2005.2.883.

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42

Kumar, Niranjan. "Electrical characterization of TSVs with varying process knobs and temporary bond/adhesive system robustness studies for 2.5D/3D manufacturing." International Symposium on Microelectronics 2013, no. 1 (2013): 000233. http://dx.doi.org/10.4071/isom-2013-tp14.

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TSVs are used to carry power/ground and signals straight to the heart of the logic/memory devices where all the intricate and busy architectures lie. I consider it like the downtown area inside a city where the real estate is more expensive and requires intricate design and execution. As a result in case of the TSVs, there is no room for electrical degradation and stress interaction with transistor devices (keep out zone). The Cu protrusion, it's interaction with the intricate local interconnects (M1 and below structures), the current leakage, capacitance, reliability, become highly critical t

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Kim, Tae Hong, Jung Chul Kim, Seung Ho Kim, and Ho Young Kim. "Effects of Substrate Temperature on the Leaning of Micropatterns during Rinse-Dry Process." Solid State Phenomena 195 (December 2012): 247–51. http://dx.doi.org/10.4028/www.scientific.net/ssp.195.247.

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The spin drying, in which a rinsing liquid deposited on a wafer is rapidly dried by wafer spinning, is an essential step in semiconductor manufacturing process. While the liquid evaporates, its meniscus straddles neighboring submicron-size patterns. Then the capillary effects that pull the patterns together may lead to direct contact of the patterns, which is referred to as pattern leaning, a problem becoming more and more serious as the pattern size shrinks and the aspect ratio of the patterns increases. The interaction between elastic structures and capillary forces, orelasto-capillarity[1,

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Shetty, Kishan, Yudhbir Kaushal, D. S. Murthy, and Chandra Mauli Kumar. "Advanced fine line double printing process for manufacturing high efficiency silicon wafer solar cells." Solar Energy 180 (March 2019): 301–6. http://dx.doi.org/10.1016/j.solener.2019.01.020.

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Jung, W. G., G. S. Back, F. T. Johra, J. H. Kim, Y. C. Chang, and S. J. Yoo. "Preliminary reduction of chromium ore using Si sludge generated in silicon wafer manufacturing process." Journal of Mining and Metallurgy, Section B: Metallurgy 54, no. 1 (2018): 29–37. http://dx.doi.org/10.2298/jmmb170520054j.

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In order to promote the recycling of by-product from Si wafer manufacturing process and to develop environment-friend and low cost process for ferrochrome alloy production, a basic study was performed on the preliminary reduction reaction between chromium ore and the Si sludge, comprised of SiC and Si particles, which is recovered from the Si wafer manufacturing process for the semiconductor and solar cell industries. Pellets were first made by mixing chromium ore, Si sludge, and some binders in the designed mixing ratios and were then treated at different temperatures in the 1116?C?1388?C ran

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Vasilache, D., S. Colpo, F. Giacomozzi, et al. "Through wafer via holes manufacturing by variable isotropy Deep RIE process for RF applications." Microsystem Technologies 18, no. 7-8 (2012): 1057–63. http://dx.doi.org/10.1007/s00542-012-1438-8.

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Han, Hyeon Joon, Hunhee Lee, Charles Kim, et al. "Ultrafine Particle Removal in the Wafer Cleaning Process Using an Aqueous Solution with a High Concentration of Dissolved O₃ and HF." Solid State Phenomena 314 (February 2021): 214–17. http://dx.doi.org/10.4028/www.scientific.net/ssp.314.214.

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Sulfuric Peroxide Mixture (SPM, H2SO4 + H2O2) has been widely used in semiconductor manufacturing processes due to its high reactivity and attractive price. However, SPM releases SO42- ions that can be high impact on the environmental contaminations. Therefore, the SPM process requires a high cost wastewater treatment. So, the development of alternative chemicals has been becoming an important task in the semiconductor manufacturing process. In this paper, we evaluated the feasibility of replacing SPM with dissolved ozone water (DIO3) in the wafer cleaning process, and confirmed that the Parti

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Boumsellek, S., and R. Ferran. "Miniature Quadrupole Arrays for Residual and Process Gas Analysis." Journal of the IEST 42, no. 1 (1999): 27–31. http://dx.doi.org/10.17764/jiet.42.1.p57381407j7677u0.

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This paper includes computer simulations based on ray tracing to aid in the design of miniature quadrupoles. These quadrupoles are then assembled in a matrix-like pattern to operate in parallel. The tradeoffs between sensitivity and resolution for different mechanical and electrical configurations are examined using real-time trajectories of ions. The dependence of resolution versus sensitivity is computed and compared with experimental results. The pressure dependence of the sensitivity is simulated near the upper limit (mtorr range) of the operating pressure. Space charge effects at the inle

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Elliott, David J., Victoria M. Chaplick, Eugene Degenkolb, Kenneth Harte, and Ronald P. Millman Jr. "Wafer Edge Bead Cleaning with Laser Radiation and Reactive Gas." Solid State Phenomena 187 (April 2012): 117–20. http://dx.doi.org/10.4028/www.scientific.net/ssp.187.117.

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The purpose of this study is to investigate and optimize the process parameters for cleaning the top, bottom, and apex edges of silicon wafers using laser radiation and reactive gas. A secondary purpose is to conduct photoresist edge bead and post-etch polymer film removal (EBR) experiments to determine the minimum controllable edge exclusion in EBR processing to improve die yield. [ An overall purpose is to identify a robust and environmentally sound process for wafer edge cleaning and a hardware configuration (stand alone or track integrated) that can be cost effectively produced for device

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Che, Fa Xing. "Dynamic Stress Modeling on Wafer Thinning Process and Reliability Analysis for TSV Wafer." IEEE Transactions on Components, Packaging and Manufacturing Technology 4, no. 9 (2014): 1432–40. http://dx.doi.org/10.1109/tcpmt.2014.2339871.

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