Relevant bibliographies by topics / Central Processing Unit (CPU)

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Central Processing Unit (CPU)'

Author: Grafiati
Published: 4 June 2021
Last updated: 25 July 2025

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Journal articles on the topic "Central Processing Unit (CPU)"

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Rai, Ankush, and Jagadeesh Kannan R. "CENTRAL PROCESSING UNIT-GRAPHICS PROCESSING UNIT COMPUTING SCHEME FOR MULTI-OBJECT TRACKING IN SURVEILLANCE." Asian Journal of Pharmaceutical and Clinical Research 10, no. 13 (2017): 251. http://dx.doi.org/10.22159/ajpcr.2017.v10s1.19651.

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This research work presents a novel central processing unit-graphics processing unit (CPU-GPU) computing scheme for multiple object trackingduring a surveillance operation. This facilitates nonlinear computational jobs to avail completion of computation in minimal processing time for tracking function. The work is divided into two essential objectives. First is to dynamically divide the processing operations into parallel units, and second is to reduce the communication between CPU-GPU processing units.
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Bhadrayya, Sowmya Kandiga, and Vishwas Bangalore Ravishankar. "Central processing unit load reduction through application code optimization and memory management." International Journal of Reconfigurable and Embedded Systems (IJRES) 14, no. 1 (2025): 79. https://doi.org/10.11591/ijres.v14.i1.pp79-88.

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Central processing unit (CPU) loading refers to the amount of processing power a CPU uses to execute a given set of commands or perform an exact task. Higher CPU load can lead to slower, sluggish performance, reduced lifespan, and reduced system stability. Using the CPU Load trace results, the performance bottlenecks can be identified and suitable methods can be adopted to reduce the load on the CPU. For an ideal embedded system, the CPU should be in idle state for around 70% of CPU usage time. In this paper, three types of optimization techniques are implemented, which include application cod
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Kandiga, Bhadrayya Sowmya, and Ravishankar Vishwas Bangalore. "Central processing unit load reduction through application code optimization and memory management." International Journal of Reconfigurable and Embedded Systems (IJRES) 14, no. 1 (2025): 79–88. https://doi.org/10.11591/ijres.v14.i1.pp79-88.

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Central processing unit (CPU) loading refers to the amount of processing power a CPU uses to execute a given set of commands or perform an exact task. Higher CPU load can lead to slower, sluggish performance, reduced lifespan, and reduced system stability. Using the CPU Load trace results, the performance bottlenecks can be identified and suitable methods can be adopted to reduce the load on the CPU. For an ideal embedded system, the CPU should be in idle state for around 70% of CPU usage time. In this paper, three types of optimization techniques are implemented, which include application cod
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Ayush, Bhardwaj, and B. Ramesh K. "Designing a Graphics Processing Unit with advanced Arithmetic Logic Unit Resulting Improved Performance." Research and Applications: Emerging Technologies 6, no. 3 (2024): 38–46. https://doi.org/10.5281/zenodo.12720907.

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<em>This paper explores microprocessor intricacies, particularly the central processing unit (CPU) and the graphics processing unit (GPU). The CPU, dubbed a computer's brain, features critical components like the Control Unit (CU), Arithmetic Logic Unit (ALU), and Memory Unit (MU), orchestrating instruction execution and system resource management. Contrarily, GPUs, initially for graphics rendering, now excel in parallel processing, aiding tasks beyond graphics. It compares CPU and GPU architectures, emphasizing their parallel processing and memory hierarchy. The graphics rendering pipeline's
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Yang, Min Kyu, and Jae-Seung Jeong. "Optimized Hybrid Central Processing Unit–Graphics Processing Unit Workflow for Accelerating Advanced Encryption Standard Encryption: Performance Evaluation and Computational Modeling." Applied Sciences 15, no. 7 (2025): 3863. https://doi.org/10.3390/app15073863.

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This study addresses the growing demand for scalable data encryption by evaluating the performance of AES (Advanced Encryption Standard) encryption and decryption using CBC (Cipher Block Chaining) and CTR (Counter Mode) modes across various CPU (Central Processing Unit) and GPU (Graphics Processing Unit) hardware models. The objective is to highlight GPU acceleration benefits and propose an optimized hybrid CPU–GPU workflow for large-scale data security. Methods include benchmarking encryption performance with provided data, mathematical models, and computational analysis. The results indicate
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A. Mohamad Alshiha, Abeer, Mohammed Wajid Al-Neama, and Abdalrahman R. Qubaa. "Biometric face recognition method using graphics processing unit system." Indonesian Journal of Electrical Engineering and Computer Science 30, no. 1 (2023): 183. http://dx.doi.org/10.11591/ijeecs.v30.i1.pp183-191.

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The expansion of biometric applications and databases is worrying. Processing extensive or sophisticated biometric data results in longer wait times, which might restrict application usefulness. This work focuses on accelerating the processing of biometric data and proposes a parallel method of data processing that exceeds the capabilities of a central processing unit (CPU). The combination of the graphics processing unit (GPU) and compute unified device architecture (CUDA) results in at least three times the processing speed of a published accurate and secure multimodal biometric system. The
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Abeer, A. Mohamad Alshiha, Wajid Al-Neama Mohammed, and R. Qubaa Abdalrahman. "Biometric face recognition method using graphics processing unit system." Biometric face recognition method using graphics processing unit system 30, no. 1 (2023): 183–91. https://doi.org/10.11591/ijeecs.v30.i1.pp183-191.

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The expansion of biometric applications and databases is worrying. Processing extensive or sophisticated biometric data results in longer wait times, which might restrict application usefulness. This work focuses on accelerating the processing of biometric data and proposes a parallel method of data processing that exceeds the capabilities of a central processing unit (CPU). The combination of the graphics processing unit (GPU) and compute unified device architecture (CUDA) results in at least three times the processing speed of a published accurate and secure multimodal biometric system. The
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Keluskar, Yugesh C., Megha M. Navada, Chaitanya S. Jage, and Navin G. Singhaniya. "Implementation of Airy function using Graphics Processing Unit (GPU)." ITM Web of Conferences 32 (2020): 03052. http://dx.doi.org/10.1051/itmconf/20203203052.

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Special mathematical functions are an integral part of Fractional Calculus, one of them is the Airy function. But it’s a gruelling task for the processor as well as system that is constructed around the function when it comes to evaluating the special mathematical functions on an ordinary Central Processing Unit (CPU). The Parallel processing capabilities of a Graphics processing Unit (GPU) hence is used. In this paper GPU is used to get a speedup in time required, with respect to CPU time for evaluating the Airy function on its real domain. The objective of this paper is to provide a platform
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Sembodo, Budi Prijo. "Ampere Meter DC Menggunakan ADC 0804 Sebagai Interface Pada Central Processing Unit (CPU) Komputer." WAKTU: Jurnal Teknik UNIPA 9, no. 1 (2011): 8–15. http://dx.doi.org/10.36456/waktu.v9i1.898.

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World Science and Technology especially at for computer have giving many amenity all area because it’s operation very practical, efficient and easily. In this research of the peripheral of computer used as by media depicting the level of value measurement of direct current from an external electronics network which interfaced to computer pass to port of parallel. Expected with ampere meter of dc use ADC 0804 as interface at central processing unit (CPU) can assist process read of measurement value and can be used also by other consumer in the world of education. The method which is used in t
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Abdul Razak, Angger, Adharul Muttaqin, and Muhammad Aswin. "Evaluasi Efisiensi Energi Komputasi FDTD Menggunakan Graphics Processing Unit." Jurnal EECCIS (Electrics, Electronics, Communications, Controls, Informatics, Systems) 13, no. 1 (2019): 1–5. https://doi.org/10.21776/jeeccis.v13i1.557.

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Finite Difference Time Domain (FDTD) merupakan salah satu metode yang banyak digunakan untuk mengevaluasi dan mensimulasi gelombang elektromagnetik beserta interaksinya dengan material sekitarnya. Namun, FDTD juga dikenal dengan kebutuhan sumber daya komputer yang besar. Pada paper ini, FDTD yang pada umumnya dijalankan menggunakan komputasi Central Processing unit (CPU) akan dijalankan menggunakan komputasi Graphics Processing Unit (GPU) dan dievaluasi kelayakannya. Selain itu, perbandingan energi yang digunakan pada kedua metode kalkulasi tersebut juga akan dibandingkan sebagai target utama
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Dissertations / Theses on the topic "Central Processing Unit (CPU)"

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Gibson, Michael John. "Genetic programming and cellular automata for fast flood modelling on multi-core CPU and many-core GPU computers." Thesis, University of Exeter, 2015. http://hdl.handle.net/10871/20364.

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Many complex systems in nature are governed by simple local interactions, although a number are also described by global interactions. For example, within the field of hydraulics the Navier-Stokes equations describe free-surface water flow, through means of the global preservation of water volume, momentum and energy. However, solving such partial differential equations (PDEs) is computationally expensive when applied to large 2D flow problems. An alternative which reduces the computational complexity, is to use a local derivative to approximate the PDEs, such as finite difference methods, or
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Månsson, Jakob. "Comparative Study of CPU and GPGPU Implementations of the Sievesof Eratosthenes, Sundaram and Atkin." Thesis, Blekinge Tekniska Högskola, Institutionen för datavetenskap, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-21111.

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Background. Prime numbers are integers divisible only on 1 and themselves, and one of the oldest methods of finding them is through a process known as sieving. A prime number sieving algorithm produces every prime number in a span, usually from the number 2 up to a given number n. In this thesis, we will cover the three sieves of Eratosthenes, Sundaram, and Atkin. Objectives. We shall compare their sequential CPU implementations to their parallel GPGPU (General Purpose Graphics Processing Unit) counterparts on the matter of performance, accuracy, and suitability. GPGPU is a method in which one
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Jowkar, Saeid. "The Application of Programmable Logic Controller (PLC) to Control Temperature in Cold-room Based on TIA PORTAL Software." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2020.

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A temperature sensor is a device to measure the temperature through an electrical signal. It requires a thermocouple or resistance temperature detectors (RTD) and will interface with a programmable logic controller (PLC). A temperature transmitter is a device that connects to a temperature sensor to transmit the signal elsewhere for monitoring and control purposes that its role is to convert the temperature sensor's signal to a 0-10V DC voltage in the PLC. The PLC voltage signal setting is compared to the temperature deviation after the Proportional Integral Derivative (PID) operation. Then, t
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Rego, Paulo Antonio Leal. "FairCPU: Uma Arquitetura para Provisionamento de MÃquinas Virtuais Utilizando CaracterÃsticas de Processamento." Universidade Federal do CearÃ, 2012. http://www.teses.ufc.br/tde_busca/arquivo.php?codArquivo=7653.

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FundaÃÃo Cearense de Apoio ao Desenvolvimento Cientifico e TecnolÃgico<br>O escalonamento de recursos à um processo chave para a plataforma de ComputaÃÃo em Nuvem, que geralmente utiliza mÃquinas virtuais (MVs) como unidades de escalonamento. O uso de tÃcnicas de virtualizaÃÃo fornece grande flexibilidade com a habilidade de instanciar vÃrias MVs em uma mesma mÃquina fÃsica (MF), modificar a capacidade das MVs e migrÃ-las entre as MFs. As tÃcnicas de consolidaÃÃo e alocaÃÃo dinÃmica de MVs tÃm tratado o impacto da sua utilizaÃÃo como uma medida independente de localizaÃÃo. à geralmente aceito
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Scarlato, Michele. "Sicurezza di rete, analisi del traffico e monitoraggio." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2012. http://amslaurea.unibo.it/3223/.

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Il lavoro è stato suddiviso in tre macro-aree. Una prima riguardante un'analisi teorica di come funzionano le intrusioni, di quali software vengono utilizzati per compierle, e di come proteggersi (usando i dispositivi che in termine generico si possono riconoscere come i firewall). Una seconda macro-area che analizza un'intrusione avvenuta dall'esterno verso dei server sensibili di una rete LAN. Questa analisi viene condotta sui file catturati dalle due interfacce di rete configurate in modalità promiscua su una sonda presente nella LAN. Le interfacce sono due per potersi interfacciar
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Κάτσενος, Χρήστος. "Ανάπτυξη διαδικτυακής εφαρμογής για την εξομοίωση της λειτουργίας ενός επεξεργαστή με διευρυμένο ρεπερτόριο εντολών". Thesis, 2012. http://hdl.handle.net/10889/5402.

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Αντικείμενο της παρούσας εργασίας είναι η εξομοίωση της λειτουργίας ενός επεξεργαστή με διευρυμένο ρεπερτόριο εντολών μέσω του διαδικτύου. Αναλυτικότερα αναπτύχθηκε ένα διαδικτυακό εργαλείο που δέχεται την αλληλουχία των εντολών και στην συνέχεια αφού εκτελέσει έλεγχο αυτών, συμβολομεταφράζει και αποθηκεύει τον κώδικα που προκύπτει στην μνήμη της εφαρμογής. Αφού όλα τα παραπάνω έχουν ολοκληρωθεί και το πρόγραμμα έχει ελεγχθεί και αποθηκευθεί στην μνήμη τότε το γραφικό τμήμα της εφαρμογής αναλαμβάνει να εξομοιώσει την λειτουργία του επεξεργαστή, προβάλλοντας τις τιμές που παίρνουν οι καταχω
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Γαλετάκης, Εμμανουήλ. "Σχεδίαση & υλοποίηση ενός μικροϋπολογιστικού συστήματος βασισμένου σε μια επαυξημένη σχετικά απλή CPU". Thesis, 2012. http://hdl.handle.net/10889/5401.

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Η παρούσα ειδική ερευνητική εργασία εκπονήθηκε στα πλαίσια του Διατμηματικού Προγράμματος Μεταπτυχιακών Σπουδών Ειδίκευσης στην “Ηλεκτρονική και Επεξεργασία της Πληροφορίας” στο Τμήμα Φυσικής του Πανεπιστημίου Πατρών. Αντικείμενο της παρούσας εργασίας είναι η σχεδίαση και ανάπτυξη ενός βασικού μικροϋπολογιστικού συστήματος με τη χρήση της VHDL και FPGAs. Το σύστημα βασίζεται σε μία επαυξημένη, σε δυνατότητες, εκδοχή της σχετικά απλής cpu του Carpinelli και ενσωματώνει τη δυνατότητα παράλληλης διασύνδεσης μίας σειράς περιφερειακών διατάξεων και υποκυκλωμάτων. Στο πρώτο κεφάλαιο παρουσιάζε
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Mishra, Ashirbad. "Efficient betweenness Centrality Computations on Hybrid CPU-GPU Systems." Thesis, 2016. http://etd.iisc.ac.in/handle/2005/2718.

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Analysis of networks is quite interesting, because they can be interpreted for several purposes. Various features require different metrics to measure and interpret them. Measuring the relative importance of each vertex in a network is one of the most fundamental building blocks in network analysis. Between’s Centrality (BC) is one such metric that plays a key role in many real world applications. BC is an important graph analytics application for large-scale graphs. However it is one of the most computationally intensive kernels to execute, and measuring centrality in billion-scale graphs is
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Mishra, Ashirbad. "Efficient betweenness Centrality Computations on Hybrid CPU-GPU Systems." Thesis, 2016. http://hdl.handle.net/2005/2718.

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Analysis of networks is quite interesting, because they can be interpreted for several purposes. Various features require different metrics to measure and interpret them. Measuring the relative importance of each vertex in a network is one of the most fundamental building blocks in network analysis. Between’s Centrality (BC) is one such metric that plays a key role in many real world applications. BC is an important graph analytics application for large-scale graphs. However it is one of the most computationally intensive kernels to execute, and measuring centrality in billion-scale graphs is
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Pandit, Prasanna Vasant. "Cooperative Execution of Opencl Programs on Multiple Heterogeneous Devices." Thesis, 2013. http://etd.iisc.ac.in/handle/2005/3468.

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Computing systems have become heterogeneous with the increasing prevalence of multi-core CPUs, Graphics Processing Units (GPU) and other accelerators in them. OpenCL has emerged as an attractive programming framework for heterogeneous systems. However, utilizing mul- tiple devices in OpenCL is a challenge as it requires the programmer to explicitly map data and computation to each device. Utilizing multiple devices simultaneously to speed up execu- tion of a kernel is even more complex, as the relative execution time of the kernel on different devices can vary significantly. Also, after each ke
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Books on the topic "Central Processing Unit (CPU)"

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Zilog. Z80 CPU central processing unit technical manual. Zilog, 1987.

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Center, Langley Research, ed. CPU timing routines for a CONVEX C220 computer system. National Aeronautics and Space Administration, Langley Research Center, 1989.

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N, Levitt Karl, Cohen G. C, and Langley Research Center, eds. Toward a formal verification of a floating-point coprocessor and its composition with a central processing unit. National Aeronautics and Space Administration, Langley Research Center, 1991.

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Parker, Philip M. The World Market for Digital Automatic Data Processing Machines Containing in the Same Housing a Central Processing Unit and an Input and Output Unit: A 2007 Global Trade Perspective. ICON Group International, Inc., 2006.

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The World Market for Digital Automatic Data Processing Machines Containing in the Same Housing a Central Processing Unit and an Input and Output Unit: A 2004 Global Trade Perspective. Icon Group International, Inc., 2005.

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Lee, Seung Min. Design and simulation of a simple digital computer central processing unit using computer-aided design software on a personal computer. 1988.

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Book chapters on the topic "Central Processing Unit (CPU)"

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Chinazzo, André, Christian De Schryver, Katharina Zweig, and Norbert Wehn. "A Custom Hardware Architecture for the Link Assessment Problem." In Lecture Notes in Computer Science. Springer Nature Switzerland, 2022. http://dx.doi.org/10.1007/978-3-031-21534-6_4.

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AbstractHeterogeneous accelerator enhanced computing architectures are a common solution in embedded computing, mainly due to the constraints in energy and power efficiency. Such accelerator enhanced systems dispatch data- and computing-intensive tasks to specialized, optimized and thus efficient hardware units, leaving most control flow tasks for the more generic but less efficient central processing units (CPUs). Nowadays, also high-performance computing (HPC) systems are becoming more heterogeneous by incorporating accelerators into the computing nodes.In this chapter, we introduce the conc
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Bindal, Ahmet. "Central Processing Unit." In Fundamentals of Computer Architecture and Design. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-25811-9_6.

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Bindal, Ahmet. "Central Processing Unit." In Fundamentals of Computer Architecture and Design. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-00223-7_6.

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Wang, Shuangbao Paul. "Central Processing Unit." In Computer Architecture and Organization. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-5662-0_6.

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Bräunl, Thomas. "Central Processing Unit." In Embedded Robotics. Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-0804-9_2.

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Bradley, D. A., D. Dawson, N. C. Burd, and A. J. Loader. "The central processing unit." In Mechatronics. Springer US, 1991. http://dx.doi.org/10.1007/978-1-4615-3068-8_11.

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Kida, Hiroyuki, Mitsuru Watabe, Tetsuaki Nakamikawa, Shigeki Morinaga, Shumpei Kawasaki, and Hideo Inayoshi. "A Floating Point Processing Unit for the Gmicro CPU." In TRON Project 1988. Springer Japan, 1988. http://dx.doi.org/10.1007/978-4-431-68081-9_21.

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Lawson, Harold. "The Datasaab Flexible Central Processing Unit." In IFIP International Federation for Information Processing. Springer US, 2005. http://dx.doi.org/10.1007/0-387-24168-x_17.

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Bauer, Lars, Hongyan Zhang, Michael A. Kochte, Eric Schneider, Hans-Joachim Wunderlich, and Jörg Henkel. "Online Test Strategies and Optimizations for Reliable Reconfigurable Architectures." In Dependable Embedded Systems. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_12.

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AbstractRuntime/reconfigurable architectures based on Field-Programmable Gate Arrays (FPGAs) are a promising augment to conventional processor architectures such as Central Processing Units (CPUs) and Graphic Processing Units (GPUs). Since the reconfigurable parts are typically manufactured in the latest technology, they may suffer from aging and environmentally induced dependability threats. In this chapter, strategic online test methods for dependable runtime-reconfigurable architectures as well as cross-layer optimizations for high reliability and lifetime are developed. Firstly, two orthog
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Ahmad, Tanvir, and Yinglong Ma. "Performance Evaluation of Faster R-CNN for On-Road Object Detection on Graphical Processing Unit and Central Processing Unit." In Intelligent Computing Methodologies. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-26766-7_10.

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Conference papers on the topic "Central Processing Unit (CPU)"

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Cornelius, Jason, Zachary Miles, Anthony Comer, et al. "Long-Range Mars Rotorcraft Design Optimization using Machine Learning." In Vertical Flight Society 81st Annual Forum and Technology Display. The Vertical Flight Society, 2025. https://doi.org/10.4050/f-0081-2025-364.

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Simulation data consisting of multiple fidelity levels were generated using Graphical Processing Unit (GPU) resources on the NASA supercomputers. First, two large aerodynamic simulation databases were generated for geometric perturbations over a range of flight conditions for a hex-rotor bi-plane tailsitter aircraft. Results were visualized using the NASA Advanced Supercomputing Division's Hyperwall to improve the geometric design constraints. More than 3,000 full aircraft aerodynamic simulations were run using GPU enabled OVERFLOW with an actuator disk model to generate the airframe aerodynam
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Al-Jumaah, Muntathir M., Faisal M. Al-Mutahhar, and Muhammad A. Sherwani. "Corrosion Management Review of Sour Gas Pipeline – a Case Study." In CONFERENCE 2023. AMPP, 2023. https://doi.org/10.5006/c2023-18855.

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Abstract A comprehensive corrosion management review was conducted for a 38-inch diameter pipeline transporting dehydrated sour gas from Central Processing Facility (CPF) to downstream Gas Plant. The pipeline, which has been in service for more than ten (10) years, was constructed of bare carbon steel and equipped with a scraping facility and corrosion inhibitor injection skid that is operated by the CPF only during Tri-Ethylene Glycol (TEG) Dehydration Unit upset or off-spec conditions. After two (2) years of operations, an in-line inspection (ILI) was conducted which provided an early indica
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Keyanfar, Alireza, Reza Ghaderi, and Soheila Nazari. "FPGA based designing Central processing unit of Implantable Cardiac Defibrillators with low energy consumption by using CNN deep neural network." In 2024 9th International Conference on Technology and Energy Management (ICTEM). IEEE, 2024. http://dx.doi.org/10.1109/ictem60690.2024.10632014.

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Bae, Jeong-Hyo, Jae-Duck Lee, Tae-Hyun Ha, Yoon-Cheol Ha, Hyun-Goo Lee, and Dae-Kyeong Kim. "Remote Corrosion Monitoring System for Buried Pipeline Using Trunked Radio System and Permanent Reference Electrode." In CORROSION 2005. NACE International, 2005. https://doi.org/10.5006/c2005-05376.

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Abstract The owner of underground metallic structures (gas pipeline, oil pipeline, water pipeline, etc) has a burden of responsibility for the corrosion protection in order to prevent the big a accident such as gas explosion, soil pollution, leakage and so on. So far, cathodic protection technology have been implemented for protection of underground systems. Here it is essential to measure and analyze the data about P/S(Pipe to Soil) potential. Until now, they have been spent lot of the money and the time in corrosion monitoring and analysis of the measured data manually. In this aspect, KERI(
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Lemon, Christopher, Hui Cao, Matthew Szyndel, and Eduard Khramchenkov. "An Adaptive Coloring Scheme for Graphics Processing Unit Preconditioners." In SPE Reservoir Simulation Conference. SPE, 2023. http://dx.doi.org/10.2118/212248-ms.

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Abstract A single modern graphics processing unit (GPU) typically has the memory bandwidth equivalent to many central processing unit (CPU) nodes. This makes GPU hardware appealing for linear solvers that tend to require high memory bandwidth and fast inter-core communication. Reservoir simulators are designed to handle a wide range of simulation models, and to obtain peak performance the linear solver must be well suited to the resulting linear systems. This fact can lead to disappointing performance when shifting the linear solver from CPU to GPU. To fully utilize the capabilities of the lat
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Tene, Matei, Michael Sekachev, Daniel de Brito Dias, and Matthew D. E. Szyndel. "Graphics Processing Unit Performance Scalability Study on a Commercial Black-Oil Reservoir Simulator." In SPE Reservoir Simulation Conference. SPE, 2023. http://dx.doi.org/10.2118/212183-ms.

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Abstract Commercial reservoir simulators have traditionally been optimized for distributed parallel execution on Central Processing Units (CPUs). Recent advances in Graphics Processing Units (GPUs) have led to the development of GPU-native simulators and triggered a shift towards a hardware-agnostic design in existing CPU solutions. For the latter, the suite of algorithms and data structures employed for a given computation are implemented for each target device. This results in a hybrid approach, where some simulator components inherently expose enough instruction parallelism or memory bandwi
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Mitrović, Stefan, Snežana Brković, Mina Seović, et al. "SUSTAINABLE METAL RECOVERY: CPU RECYCLING FOR ENHANCED HYDROGEN EVOLUTION REACTION." In 17th International Conference on Fundamental and Applied Aspects of Physical Chemistry. Society of Physical Chemists of Serbia, 2024. https://doi.org/10.46793/phys.chem24i.191m.

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This paper explores the feasibility and efficacy of employing whole CPU (Central Processing Unit) recycling as a sustainable source of metals for catalyst coatings in the Hydrogen Evolution Reaction (HER). With the escalating global issue of electronic waste (e-waste), repurposing discarded CPUs offers a promising avenue for metal recovery and utilization. Through systematic experimentation, CPU preparation technique was evaluated for formation of electrode catalytic layer and the kinetics of HER in alkaline media. The resulting electrodeposited cathode was assessed for electrocatalytic effici
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Dominico, Simone, Marco Antonio Zanata Alves, and Eduardo Cunha de Almeida. "Comparação de desempenho do processamento paralelo de consultas de banco de dados em CPUs multi-core e GPUs." In Escola Regional de Alto Desempenho da Região Sul. Sociedade Brasileira de Computação - SBC, 2022. http://dx.doi.org/10.5753/eradrs.2022.19184.

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O processamento paralelo é uma solução para melhorar o desempenho de consultas de banco de dados, reduzindo o tempo de resposta, e aumentando a vazão no processamento de consultas. Com a evolução de hardware surgiram novas tecnologias para o paralelismo. Uma delas é o uso de GPUs (Graphics Processing Units) para processamento de propósito geral. A GPU é uma unidade de processamento massivamente paralela com um número maior de núcleos executando em uma frequência menor comparado a CPU (Central Processing Unit). Neste contexto, este artigo apresenta um estudo comparativo do processamento de uma
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Karthik, Victor U., Sivamayam Sivasuthan, Arunasalam Rahunanthan, Paramsothy Jayakumar, Ravi S. Thyagarajan, and S. Ratnajeevan H. Hoole. "FINITE ELEMENT OPTIMIZATION FOR NONDESTRUCTIVE EVALUATION ON A GRAPHICS PROCESSING UNIT FOR GROUND VEHICLE HULL INSPECTION." In 2024 NDIA Michigan Chapter Ground Vehicle Systems Engineering and Technology Symposium. National Defense Industrial Association, 2024. http://dx.doi.org/10.4271/2024-01-3430.

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&lt;title&gt;ABSTRACT&lt;/title&gt; &lt;p&gt;Shape reconstruction for nondestructive evaluation (NDE) of internal defects in ground vehicle hulls using eddy current probes provides a rationale for determination of when to withdraw vehicles from deployment. This process requires detailed finite element optimization and is computationally intensive. Traditional shared memory parallel systems, however, are prohibitively expensive and have limited central processing units (CPUs), making speedup limited. So parallelization has never been done. However, a CPU that is connected to graphics processing
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Kollam, Manoj, and Ajay Joshi. "A MACHINE LEARNING MODEL FOR AN EARTHQUAKE FORECASTING USING PARALLEL PROCESSING." In International Conference on Emerging Trends in Engineering & Technology (IConETech-2020). Faculty of Engineering, The University of the West Indies, St. Augustine, 2020. http://dx.doi.org/10.47412/dhhv5862.

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Earthquake is a devastating natural hazard which has a capability to wipe out thousands of lives and cause economic loss to the geographical location. Seismic stations continuously gather data without the necessity of the occurrence of an event. The gathered data is processed by the model to forecast the occurrence of earthquakes. This paper presents a model to forecast earthquakes using Parallel processing. Machine Learning is rapidly taking over a variety of aspects in our daily lives. Even though Machine Learning methods can be used for analyzing data, in the scenario of event forecasts lik
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Reports on the topic "Central Processing Unit (CPU)"

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Lunn, Pete, Marek Bohacek, Jason Somerville, Áine Ní Choisdealbha, and Féidhlim McGowan. PRICE Lab: An Investigation of Consumers’ Capabilities with Complex Products. ESRI, 2016. https://doi.org/10.26504/bkmnext306.

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Executive Summary This report describes a series of experiments carried out by PRICE Lab, a research programme at the Economic and Social Research Institute (ESRI) jointly funded by the Central Bank of Ireland, the Commission for Energy Regulation, the Competition and Consumer Protection Commission and the Commission for Communications Regulation. The experiments were conducted with samples of Irish consumers aged 18-70 years and were designed to answer the following general research question: At what point do products become too complex for consumers to choose accurately between the good ones
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