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Journal articles on the topic 'Circuit optimization'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 July 2025

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1

Liu, Manqi. "Current Status, Development, And Application of Optimization Methods for Analog Circuits." Highlights in Science, Engineering and Technology 81 (January 26, 2024): 438–43. http://dx.doi.org/10.54097/j4vjfn83.

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The optimization of analog circuits has always relied on the experience and intuition of engineers to find suitable parameters to meet the requirements of the circuit, which is time-consuming and costly. This paper outlines and analyzes the optimization methods for analog circuits in recent years, and draws some summaries that can be used as references for subsequent optimization circuits. The optimization of analog circuits is mainly divided into the optimization of the performance of the hardware in the circuit and the optimization of the circuit structure. Hardware optimization, this paper

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2

Jim, Ho Joon, and Fazida Hanim Hashim. "An improved ant colony optimization algorithm for wire optimization." Bulletin of Electrical Engineering and Informatics 9, no. 5 (2020): 2170–77. http://dx.doi.org/10.11591/eei.v9i5.2268.

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Wire optimization has become one of the greatest challenges in today’s circuit design. This paper presents a method for wire optimization in circuit routing using an improved ant colony optimization with Steiner nodes (ACOSN) algorithm. Circuit delay and power dissipation are primarily affected by the length of the routed wire. Thus, the main goal of this proposed algorithm is to find the shortest route from one point to another using an algorithm that relies on the artificial behavior of ants. The algorithm is implemented in the JAVA programming language. The proposed ACOSN algorithm is compa

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Ho, Joon Jim, and Hanim Hashim Fazida. "An improved ant colony optimization algorithm for wire optimization." Bulletin of Electrical Engineering and Informatics 9, no. 5 (2020): 2170–77. https://doi.org/10.11591/eei.v9i5.2268.

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Wire optimization has become one of the greatest challenges in today’s circuit design. This paper presents a method for wire optimization in circuit routing using an improved ant colony optimization with Steiner nodes (ACOSN) algorithm. Circuit delay and power dissipation are primarily affected by the length of the routed wire. Thus, the main goal of this proposed algorithm is to find the shortest route from one point to another using an algorithm that relies on the artificial behavior of ants. The algorithm is implemented in the JAVA programming language. The proposed ACOSN algorithm is

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Deng, Jingxi. "Systematic Analysis and Research on Integrated Circuit Design Optimization." Highlights in Science, Engineering and Technology 81 (January 26, 2024): 197–201. http://dx.doi.org/10.54097/q42hbs73.

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After decades of development of integrated circuits, there has been great progress in all aspects. These advances are reflected in the optimization of manufacturing processes and circuits. When designing a circuit, considering the production cost and the performance of the circuit, the optimal design of the circuit is always a very important link. In this paper, two kinds of optimization ideas are introduced. One is from the point of view of the physical design of the circuit, two methods are introduced, which are adjusting the input power and reducing the circuit device. The other is to optim

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Amy, Matthew, and Joseph Lunderville. "Linear and Non-linear Relational Analyses for Quantum Program Optimization." Proceedings of the ACM on Programming Languages 9, POPL (2025): 1072–103. https://doi.org/10.1145/3704873.

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The phase folding optimization is a circuit optimization used in many quantum compilers as a fast and effective way of reducing the number of high-cost gates in a quantum circuit. However, existing formulations of the optimization rely on an exact, linear algebraic representation of the circuit, restricting the optimization to being performed on straightline quantum circuits or basic blocks in a larger quantum program. We show that the phase folding optimization can be re-cast as an affine relation analysis , which allows the direct application of classical techniques for affine relations to e

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Barra, Samir. "Intelligent Optimization of CMOS Operational Amplifier Using 3D Ant Colony Optimization." Electronics ETF 27, no. 2 (2023): 35–42. http://dx.doi.org/10.53314/els2327035b.

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This paper presents the use of an artificial intelligence (AI) tool based on ant colony behavior to design an operational amplifier circuit. The ant colony optimization (ACO) is implemented in a hybrid evolutionary sizing method to automate analog circuit design. This new meta-heuristic approach that combines the artificial intelligence of an ant colony and the 3D matrix method is developed to determine the optimal dimensions and the main influencing performances of fundamental analog circuits and, including operational amplifiers (op-amps). The proposed methodology uses ACO and Cadence Spectr

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7

Hsiao, Michael S. "Genetic Spot Optimization for Peak Power Estimation in Large VLSI Circuits." VLSI Design 15, no. 1 (2002): 407–16. http://dx.doi.org/10.1080/1065514021000012020.

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Estimating peak power involves optimization of the circuit's switching function. The switching of a given gate is not only dependent on the output capacitance of the node, but also heavily dependent on the gate delays in the circuit, since multiple switching events can result from uneven circuit delay paths in the circuit. Genetic spot expansion and optimization are proposed in this paper to estimate tight peak power bounds for large sequential circuits. The optimization spot shifts and expands dynamically based on the maximum power potential (MPP) of the nodes under optimization. Four genetic

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Aizik, Yoni, and Avinoam Kolodny. "Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints." VLSI Design 2011 (April 7, 2011): 1–13. http://dx.doi.org/10.1155/2011/845957.

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A design scenario examined in this paper assumes that a circuit has been designed initially for high speed, and it is redesigned for low power by downsizing of the gates. In recent years, as power consumption has become a dominant issue, new optimizations of circuits are required for saving energy. This is done by trading off some speed in exchange for reduced power. For each feasible speed, an optimization problem is solved in this paper, finding new sizes for the gates such that the circuit satisfies the speed goal while dissipating minimal power. Energy/delay gain (EDG) is defined as a metr

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Purushottam Kumar Maurya. "Smart Circuit Design Machine Learning-Driven Optimization for Enhanced Performance in Electronics and Computer Engineering." Tuijin Jishu/Journal of Propulsion Technology 45, no. 02 (2024): 2794–805. http://dx.doi.org/10.52783/tjjpt.v45.i02.6339.

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In the realm of Electronics and Computer engineering, achieving optimal performance of circuits amidst escalating complexity poses significant challenges. Traditional manual optimization techniques are often inadequate to navigate the intricacies of modern electronic systems. This paper advocates for the adoption of machine learning-driven optimization as a transformative approach to smart circuit design. By leveraging machine learning algorithms, engineers can systematically explore the expansive design space, discern complex relationships between circuit parameters and performance metrics, a

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10

He, Xinyu. "Design of CMOS circuits through transistor sizing techniques." Applied and Computational Engineering 12, no. 1 (2023): 1–12. http://dx.doi.org/10.54254/2755-2721/12/20230279.

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With the increasingly diverse functional requirements of contemporary electronic products, the complexity of CMOS circuits often used in chips becomes higher and the number of transistors used increases. To solve the resulting performance problems of CMOS circuits, researchers have searched for many transistor sizing technologies. This paper summarizes three methods of CMOS circuit optimization. The paper introduces these three methods in terms of principle, effect, and application scenarios, and compares them respectively. Through analysis and simulation, it can be found that the use of these

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Li, Zikun, Jinjun Peng, Yixuan Mei, et al. "Quarl: A Learning-Based Quantum Circuit Optimizer." Proceedings of the ACM on Programming Languages 8, OOPSLA1 (2024): 555–82. http://dx.doi.org/10.1145/3649831.

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Optimizing quantum circuits is challenging due to the very large search space of functionally equivalent circuits and the necessity of applying transformations that temporarily decrease performance to achieve a final performance improvement. This paper presents Quarl, a learning-based quantum circuit optimizer. Applying reinforcement learning (RL) to quantum circuit optimization raises two main challenges: the large and varying action space and the non-uniform state representation. Quarl addresses these issues with a novel neural architecture and RL-training procedure. Our neural architecture

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Zargarani, Anahita, and S. Nima Mahmoodi. "Circuit Optimization for Enhancing the Output Power of a Piezoelectric Energy Harvester." International Journal of Applied Science 1, no. 2 (2018): p6. http://dx.doi.org/10.30560/ijas.v1n2p6.

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In this paper, a new method is proposed for improving a piezoelectric energy harvester’s output power. A piezoelectric vibration energy harvester has an inherent internal capacitance. The new approach adopts inductance to reduce the reactance of the internal capacitance and enhance the output power. To show the practicality of this method, four electrical circuits are investigated numerically and experimentally for a piezoelectric beam energy harvester: Simple Resistive Load, Inductive Load, standard AC-DC, and Inductive AC-DC circuits. An Inductive Load circuit is built by adding an inductor

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Iten, Raban, Romain Moyard, Tony Metger, David Sutter, and Stefan Woerner. "Exact and Practical Pattern Matching for Quantum Circuit Optimization." ACM Transactions on Quantum Computing 3, no. 1 (2022): 1–41. http://dx.doi.org/10.1145/3498325.

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Quantum computations are typically performed as a sequence of basic operations, called quantum gates. Different gate sequences, called quantum circuits, can implement the same overall quantum computation. Since every additional quantum gate takes time and introduces noise into the system, it is important to find the smallest possible quantum circuit that implements a given computation, especially for near-term quantum devices that can execute only a limited number of quantum gates before noise renders the computation useless. An important building block for many quantum circuit optimization te

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Bundalo, Dusanka, Zlatko Bundalo, and Branimir Ðordjevic. "Design of quaternary logic systems and circuits." Facta universitatis - series: Electronics and Energetics 18, no. 1 (2005): 45–56. http://dx.doi.org/10.2298/fuee0501045b.

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The principles and possibilities of design of fully quaternary multiple valued combinational logic systems and circuits are described and proposed in the paper. Different ways of design of fully quaternary combinational logic systems and circuits are considered and described first. Then algorithm for automated computerized design of such systems and circuits is considered and proposed. The algorithm gives possibility for synthesis and optimization of quaternary logic systems and circuits. It is applied on design of CMOS quaternary multiple valued logic systems and circuits. The algorithm inclu

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Jin, Haokang. "Consumption Analysis and Optimization Strategies for Four-Bit Absolute-Value Detectors." Highlights in Science, Engineering and Technology 71 (November 28, 2023): 284–91. http://dx.doi.org/10.54097/hset.v71i.13047.

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As embedded systems, communication systems, and neurology research continue to advance, the demand for high-performance components in digital circuits has risen. Simultaneously, there is a growing need for low-energy consumption. In this paper, Four-Bit Absolute-Value Detectors, as crucial components in digital circuits, have garnered significant attention for their role in achieving energy efficiency. This paper embarks on a comprehensive exploration, commencing with the fundamentals of circuit theory, circuit topologies, and circuit styles. Through extensive calculations and comparative stud

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Tang, Haotian, Fei Ding, Xueyun Cheng, Shuxian Zhao, and Zhijin Guan. "Width Optimization of Quantum Circuit Based on Reuse-Aimed Quantum Circuit Transformation." Quantum Information & Computation 25, no. 3 (2025): 216–31. https://doi.org/10.2478/qic-2025-0011.

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Abstract Due to constraints in current quantum hardware manufacturing, the number of available qubits remains limited. This limitation poses significant challenges to the feasibility of quantum computation. Qubit reuse, supported by the hardware-enabled dynamic quantum circuit, has emerged as a promising method for optimizing the width of quantum circuits. However, enabling width optimization through qubit reuse for circuits that lack qubit reuse opportunities remains a challenging problem. This paper aims to address this challenge by introducing RaQCT (Reuseaimed Quantum Circuit Transformatio

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17

Lee, John, and Puneet Gupta. "Discrete Circuit Optimization." Foundations and Trends® in Electronic Design Automation 6, no. 1 (2012): 1–120. http://dx.doi.org/10.1561/1000000019.

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18

Yan, Ran. "Design and optimization of CMOS based 4-bit comparator." Applied and Computational Engineering 41, no. 1 (2024): 29–42. http://dx.doi.org/10.54254/2755-2721/41/20230707.

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The paper primarily focuses on optimizing circuit delay and energy consumption, specifically in gate-level circuits. Three methods are employed for circuit optimization. The first method aims to minimize transistor usage to reduce both delay and energy consumption. The second method involves prioritizing logic gates based on underlying hardware, favoring simpler circuit structures whenever possible, given that our design primarily revolves around logic gates. The third method entails adjusting the number of stages to enhance delay optimization. To validate these rules, three distinct circuits

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19

Zhou, Yuhao, Zhenxue He, Yan Zhang, et al. "Power Optimization for Mixed Polarity Reed–Muller Circuits Based on Multilevel Adaptive Memetic Algorithm." International Journal of Intelligent Systems 2023 (March 6, 2023): 1–18. http://dx.doi.org/10.1155/2023/3510001.

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Power optimization can reduce heat dissipation costs and has become an important step of circuit logic synthesis. Because the power optimization for mixed polarity Reed–Muller (MPRM) circuits is a combinatorial optimization problem, in this paper, we first propose a multilevel adaptive memetic algorithm (MAMA), which includes global exploration optimizer, local heuristic optimizer, and initial population optimizer. We use the proposed differential evolution optimization, simulated annealing optimization, and data matching algorithm to make the population evolve. Moreover, based on the proposed

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20

Song, Gyeongju, Siwoo Eum, Hyeokdong Kwon, Minjoo Sim, Minwoo Lee, and Hwajeong Seo. "Optimized Quantum Circuit for Quantum Security Strength Analysis of Argon2." Electronics 12, no. 21 (2023): 4485. http://dx.doi.org/10.3390/electronics12214485.

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This paper explores the optimization of quantum circuits for Argon2, a memory-hard function used in password hashing applications. With the rise of quantum computers, the security of classical cryptographic systems is at risk. This paper emphasizes the need to accurately measure the quantum security strength of cryptographic schemes through highly optimized quantum circuits for the target cryptography algorithm. The proposed method focuses on two perspectives: qubit reduction (qubit-optimized quantum circuit) and depth reduction (depth-optimized quantum circuit). The qubit-optimized quantum ci

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21

Gao, Xiaofeng, Zhijin Guan, Shiguang Feng, and Yibo Jiang. "Quantum Circuit Template Matching Optimization Method for Constrained Connectivity." Axioms 12, no. 7 (2023): 687. http://dx.doi.org/10.3390/axioms12070687.

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The execution of quantum algorithms requires two key considerations. On the one hand, it should meet the connectivity constraint requirements of quantum circuit mapping for quantum architectures, and on the other hand, it needs to consider reducing the probability of errors in the execution of quantum circuits as much as possible. This paper proposes a novel optimization technique based on template matching that to satisfy both requirements. The template matching optimization method can significantly reduce the number of gates in a quantum circuit and further enhance its practicality. It stand

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22

Aminu, M., M. Abana, S. W. Pallam, and P. K. Ainah. "Nonintrusive Method for Induction Motor Equivalent Circuit Parameter Estimation using Chicken Swarm Optimization (CSO) Algorithm." Nigerian Journal of Technological Development 18, no. 1 (2021): 21–29. http://dx.doi.org/10.4314/njtd.v18i1.4.

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This paper presents a nonintrusive method for estimating the parameters of an Induction Motor (IM) without the need for the conventional no-load and locked rotor tests. The method is based on a relatively new swarm-based algorithm called the Chicken Swarm Optimization (CSO). Two different equivalent circuits implementations have been considered for the parameter estimation scheme (one with parallel and the other with series magnetization circuit). The proposed parameter estimation method was validated experimentally on a standard 7.5 kW induction motor and the results were compared to those ob

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23

Prajapati, Pankaj P., Anilkumar J. Kshatriya, Dhavalkumar N. Patel, Sima K. Gonsai, Hardik B. Tank, and Kinjal R. Sheth. "Comparative analysis of meta heuristics algorithm for differential amplifier design." Bulletin of Electrical Engineering and Informatics 12, no. 6 (2023): 3395–401. http://dx.doi.org/10.11591/eei.v12i6.6153.

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The design of analog circuits is very essential for the development of system design based on electronics as the world is analog in nature. Furthermore, performance of emerging products depends on analog circuits for reduction of power dissipation and improvement of speed. Though in the system on chip (SoC) analog circuit consumes less, it is more complex to design it due to the analog circuit nature complexity. The job of the evolutionary algorithm (EA) in the process of optimization of an analog circuit based on complementary metal oxide semiconductor (CMOS) is to get the appropriate values

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Mahnoor Maghroori and Mehdi Dolatshahi. "Design of low-power CMOS VLSI circuits using multi-objective optimization in genetic algorithms." World Journal of Advanced Research and Reviews 12, no. 1 (2021): 215–24. http://dx.doi.org/10.30574/wjarr.2021.12.1.0427.

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This paper presents a design CAD tool for automated design of digital CMOS VLSI circuits. In order to fit the circuit performance into desired specifications, a multi-objective optimization approach based on genetic algorithms (GA) is proposed and the transistor sizes are calculated based on the analytical equations describing the behavior of the circuit. The optimization algorithm is developed in MATLAB and the performance of the designed circuit is verified using HSPICE simulations based on 0.18µm CMOS technology parameters. Different digital integrated circuits were successfully designed an

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Mahnoor, Maghroori, and Dolatshahi Mehdi. "Design of low-power CMOS VLSI circuits using multi-objective optimization in genetic algorithms." World Journal of Advanced Research and Reviews 12, no. 1 (2021): 215–24. https://doi.org/10.5281/zenodo.5594256.

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This paper presents a design CAD tool for automated design of digital CMOS VLSI circuits. In order to fit the circuit performance into desired specifications, a multi-objective optimization approach based on genetic algorithms (GA) is proposed and the transistor sizes are calculated based on the analytical equations describing the behavior of the circuit. The optimization algorithm is developed in MATLAB and the performance of the designed circuit is verified using HSPICE simulations based on 0.18µm CMOS technology parameters. Different digital integrated circuits were successfully desig

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Dieste-Velasco, M. Isabel. "Application of a Fuzzy Inference System for Optimization of an Amplifier Design." Mathematics 9, no. 17 (2021): 2168. http://dx.doi.org/10.3390/math9172168.

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Simulation programs are widely used in the design of analog electronic circuits to analyze their behavior and to predict the response of a circuit to variations in the circuit components. A fuzzy inference system (FIS) in combination with these simulation tools can be applied to identify both the main and interaction effects of circuit parameters on the response variables, which can help to optimize them. This paper describes an application of fuzzy inference systems to modeling the behavior of analog electronic circuits for further optimization. First, a Monte Carlo analysis, generated from t

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Li, Ruotong. "Analysis of Delay Limitation and Circuit Power Balance Optimisation for CMOS Based Circuits." Transactions on Computer Science and Intelligent Systems Research 5 (August 12, 2024): 355–60. http://dx.doi.org/10.62051/505v3198.

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As integrated circuits and technology have advanced, people's requirements for integrated circuits are getting higher and higher, and integrated circuits with high performance, low latency and low power consumption characteristics are needed to satisfy all kinds of human needs. However, meeting these needs requires a balanced optimization of circuit delay and energy consumption. The gate size and voltage need to be varied simultaneously, and the most suitable voltage and gate are found by combining the gate size and voltage ratio using a linear programming solver. This method can find the opti

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BŰRMEN, ÁRPÁD, TADEJ TUMA, and IZTOK FAJFAR. "A COMBINED SIMPLEX–TRUST-REGION METHOD FOR ANALOG CIRCUIT OPTIMIZATION." Journal of Circuits, Systems and Computers 17, no. 01 (2008): 123–40. http://dx.doi.org/10.1142/s0218126608004125.

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The analog-integrated circuits industry is exerting increasing pressure to shorten the analog circuit design time. This pressure is put primarily on the analog circuit designers that in turn demand automated circuit design tools evermore vigorously. Such tools already exist in the form of circuit optimization software packages but they all suffer a common ailment — slow convergence. Even taking into account the increasing computational power of modern computers the convergence times of such optimization tools can range from a few days to even weeks. Different authors have tried diverse approac

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Lima, Evelyn Cristina de Oliveira, André Borges Cavalcante, and João Viana Da Fonseca Neto. "Optimization of amplifier circuits by using gradient boosted trees and probability annealing policy." Journal of Integrated Circuits and Systems 15, no. 3 (2020): 1–5. http://dx.doi.org/10.29292/jics.v15i3.184.

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One important step of the optimization of analog circuits is to properly size circuit components. Since the quantities that define specification may compete for different circuit parameter values, the optimization of analog circuits befits a hard and costly optimization problem. In this work, we propose two contributions to design automation methodologies based on machine learning. Firstly, we propose a probability annealing policy to boost early data collection and restrict electronic simulations later on in the optimization. Secondly, we employ multiple gradient boosted trees to predict desi

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КИРИЛОВ, ІВАН, та ВІКТОР ШЕВЧЕНКО. "АНАЛІЗ МЕТОДІВ ОПТИМІЗАЦІЇ ГЛИБИНИ КВАНТОВОЇ СХЕМИ". Herald of Khmelnytskyi National University. Technical sciences 337, № 3(2) (2024): 334–40. http://dx.doi.org/10.31891/2307-5732-2024-337-3-50.

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This work reviews methods for optimizing quantum circuit depth, encompassing theoretical techniques, algorithmic innovations, and practical applications. Recent advancements demonstrate substantial improvements in circuit depth optimization, yet the issue of scalability remains unresolved. Key research contributions, such as the advanced exact synthesis of Clifford+T circuits, have shown promising results in reducing the number of T-gates, thus enhancing computational efficiency. However, the practical implementation of these methods in real-world noisy environments has yet to be fully evaluat

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Qian, Yang, Zhijin Guan, Shenggen Zheng, and Shiguang Feng. "A Method Based on Timing Weight Priority and Distance Optimization for Quantum Circuit Transformation." Entropy 25, no. 3 (2023): 465. http://dx.doi.org/10.3390/e25030465.

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In order to implement a quantum circuit on an NISQ device, it must be transformed into a functionally equivalent circuit that satisfies the device’s connectivity constraints. However, NISQ devices are inherently noisy, and minimizing the number of SWAP gates added to the circuit is crucial for reducing computation errors. To achieve this, we propose a subgraph isomorphism algorithm based on the timing weight priority of quantum gates, which provides a better initial mapping for a specific two-dimensional quantum architecture. Additionally, we introduce a heuristic swap sequence selection optim

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Joshi, Aravind, Akshara Kairali, Renju Raju, Adithya Athreya, and Reena Monica P. "Quantum Circuit Optimization of Arithmetic Circuits using ZX Calculus." International Journal of Innovative Technology and Exploring Engineering 13, no. 2 (2024): 26–31. http://dx.doi.org/10.35940/ijitee.b9794.13020124.

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Quantum computing is an emerging technology in which quantum mechanical properties are suitably utilized to perform certain compute-intensive operations faster than classical computers. Quantum algorithms are designed as a combination of quantum circuits that each require a large number of quantum gates, which is a challenge considering the limited number of qubit resources available in quantum computing systems. Our work proposes a technique to optimize quantum arithmetic algorithms by reducing the hardware resources and the number of qubits based on ZX calculus. We have utilized ZX calculus

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URAHAMA, KIICHI, and SHIN-ICHIRO UENO. "A GRADIENT SYSTEM SOLUTION TO POTTS MEAN FIELD EQUATIONS AND ITS ELECTRONIC IMPLEMENTATION." International Journal of Neural Systems 04, no. 01 (1993): 27–34. http://dx.doi.org/10.1142/s0129065793000043.

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A gradient system solution method is presented for solving Potts mean field equations for combinatorial optimization problems subject to winner-take-all constraints. In the proposed solution method the optimum solution is searched by using gradient descent differential equations whose trajectory is confined within the feasible solution space of optimization problems. This gradient system is proven theoretically to always produce a legal local optimum solution of combinatorial optimization problems. An elementary analog electronic circuit implementing the presented method is designed on the bas

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Chen, Zhenwei, Wei Tang, Ze Li, and Jiaqi Lan. "Design and Experimental Analysis of Charge Recovery for Piezoelectric Fan." Actuators 11, no. 1 (2022): 20. http://dx.doi.org/10.3390/act11010020.

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The piezoelectric (PE) fan is widely adopted in the field of microelectronics cooling due to its advantages of high reliability and good heat dissipation characteristics. However, PE fans driven by conventional circuits suffer from plenty of energy loss. To save energy, we propose an inductor-based charge recovery method and apply it to the driving circuit for the PE fan. Two inductor-based driving circuits, a single inductor-based driving (SID) circuit and a double inductor-based driving (DID) circuit are compared. The SID circuit has a simple structure and a slightly higher energy-saving rat

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Li, An, Yuusuke Kobayashi, Yushin Hara, Keisuke Otsuka, and Kanjuro Makihara. "Comparison of Magnetostrictive-Actuated Semi-Active Control Methods Based on Synchronized Switching." Actuators 13, no. 4 (2024): 143. http://dx.doi.org/10.3390/act13040143.

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Three distinct synchronized switching circuits based on a magnetostrictive actuator are compared in this paper to examine their control mechanisms and circuit characteristics. These circuits include a semi-active shunt circuit, a semi-active current inversion and amplification circuit, and a semi-active automatic current inversion and amplification circuit. Each circuit type employs an additional electronic switch. The synchronized switching method enables the rational control of the circuit current generated by the magnetostrictive actuator to fulfill any desired control strategy. Simulation

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Reena, Monica P. "Quantum Circuit Optimization of Arithmetic Circuits using ZX Calculus." International Journal of Innovative Technology and Exploring Engineering (IJITEE) 13, no. 2 (2024): 26–31. https://doi.org/10.35940/ijitee.B9794.13020124.

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<strong>Abstract:</strong> Quantum computing is an emerging technology in which quantum mechanical properties are suitably utilized to perform certain compute-intensive operations faster than classical computers. Quantum algorithms are designed as a combination of quantum circuits that each require a large number of quantum gates, which is a challenge considering the limited number of qubit resources available in quantum computing systems. Our work proposes a technique to optimize quantum arithmetic algorithms by reducing the hardware resources and the number of qubits based on ZX calculus. We

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Nedjah, Nadia, Jalber Dinelli Luna Galindo, Luiza de Macedo Mourelle, and Fernanda Duarte Vilela Reis de Oliveira. "Fault Diagnosis in Analog Circuits Using Swarm Intelligence." Biomimetics 8, no. 5 (2023): 388. http://dx.doi.org/10.3390/biomimetics8050388.

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Open or short-circuit faults, as well as discrete parameter faults, are the most commonly used models in the simulation prior to testing methodology. However, since analog circuits exhibit continuous responses to input signals, faults in specific circuit elements may not fully capture all potential component faults. Consequently, diagnosing faults in analog circuits requires three key aspects: identifying faulty components, determining faulty element values, and considering circuit tolerance constraints. To tackle this problem, a methodology is proposed and implemented for fault diagnosis usin

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Buriennikov, Yurii, Leonid Kozlov, Oana Rusu, et al. "OPTIMIZATION OF PARAMETERS OF THE MOBILE MACHINE ADAPTIVE HYDRAULIC CIRCUIT." International Journal of Modern Manufacturing Technologies 13, no. 3 (2021): 14–21. http://dx.doi.org/10.54684/ijmmt.2021.13.3.14.

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Mobile machine hydraulic circuits tend to adopt electrohydraulics. Such hydraulic circuits are based on controlled pumps, modulated hydraulics, sensors and controllers. This allows adapting the hydraulic circuit operating modes to the changes of external conditions of the machine operation. Application of hydraulic circuits with electrohydraulics in mobile machines allows to use mobile machines efficiently with a high number of removable endangers, increases their performance and improves the quality of performed works. The authors propose an adaptive hydraulic circuit for a mobile machine. Th

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Li, Haoxiang. "Comparison and performance optimization of two absolute circuit designs based on Multisim." Applied and Computational Engineering 129, no. 1 (2025): 63–70. https://doi.org/10.54254/2755-2721/2025.20234.

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Digital circuits are crucial in today's technology, underpinning infrastructure such as computing, communicating, and intelligent devices. Its high efficiency, accuracy and programmable capability drive the development of information processing, data transmission and automation systems. The application of digital circuits has promoted innovation in artificial intelligence, the Internet of Things and other fields, providing strong support for the intelligence and interconnection of modern society. The absolute value circuit is discussed in this paper. The absolute value circuit is implemented f

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Prajapati, Pankaj P., Anilkumar J. Kshatriya, Sureshbhai L. Bharvad, and Abhay B. Upadhyay. "Performance analysis of CMOS based analog circuit design with PVR variation." Bulletin of Electrical Engineering and Informatics 12, no. 1 (2023): 141–48. http://dx.doi.org/10.11591/eei.v12i1.4357.

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Process, supply voltage, and temperature (PVT) are three important factors which contribute to performance variation of the complementary metal–oxide–semiconductor (CMOS) based analog circuits. In this paper, CMOS based analog circuit design with the PVT variation effects are explored. The effects of the PVT variation on the performance of CMOS based analog circuits are introduced. The optimization of CMOS based analog circuits such as differential amplifier (DA) and two-stage operational amplifier (op amp) circuits with PVT variations with different algorithms such as cockoo search (CS), part

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Nguyen, Hoang Trong, and Trang Hoang. "A Novel Framework of Genetic Algorithm and Spectre to Optimize Delay and Power Consumption in Designing Dynamic Comparators." Electronics 12, no. 16 (2023): 3392. http://dx.doi.org/10.3390/electronics12163392.

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In integrated circuit (IC) design, analog circuits contribute significantly as the interface between real and digital world signals. Although they make up a relatively small portion of the overall circuit, their design process is often most time-consuming, mostly from the phase of manual iteration of circuit parameters to meet design specifications. Therefore, the design automation of analog circuits with the help of efficient optimization techniques arises as a promising candidate to address the issue. Among optimization algorithms, while the genetic algorithm (GA) has been shown to be effect

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Shih-Chieh Chang, L. P. P. P. Van Ginneken, and M. Marek-Sadowska. "Circuit optimization by rewiring." IEEE Transactions on Computers 48, no. 9 (1999): 962–70. http://dx.doi.org/10.1109/12.795224.

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B, Anuradha, Kavitha M.S., Karthik S, and Karthikeyan N. "EXPLORING NOVEL DESIGN APPROACH FOR LOW POWER VLSI IN IOT DEVICES." ICTACT Journal on Microelectronics 9, no. 2 (2023): 1562–67. https://doi.org/10.21917/ijme.2023.0272.

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Circuit-level optimization is a critical aspect of designing low-power VLSI circuits for IoT devices. Traditional optimization methods may struggle to explore the vast design space and find the most energy-efficient solutions. This paper introduces a novel approach to circuit-level optimization using an evolutionary chaotic algorithm (ECA) in the context of IoT device design. The ECA leverages the principles of chaos theory and evolutionary algorithms to efficiently explore and optimize the design parameters, leading to significant reductions in power consumption while maintaining performance

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Jeon, Yongjin, Seungjun Baek, Giyoon Kim, and Jongsung Kim. "A Framework for Generating S-Box Circuits with Boyer–Peralta Algorithm-Based Heuristics, and Its Applications to AES, SNOW3G, and Saturnin." IACR Transactions on Cryptographic Hardware and Embedded Systems 2025, no. 1 (2024): 586–631. https://doi.org/10.46586/tches.v2025.i1.586-631.

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In many lightweight cryptography applications, low area and latency are required for efficient implementation. The gate count in the cipher and the circuit depth must be low to minimize these two metrics. Many optimization strategies have been developed for the linear layer, led by the Boyer–Peralta (BP) algorithm. The Advanced Encryption Standard (AES) has been a focus of extensive research in this area. However, while the linear layer uses only XOR gates, the S-box, which is an essential nonlinear component in symmetric cryptography, uses various gate types, making optimization challenging,

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Shindo, Takuya, and Kenya Jin’no. "Switching Angles Optimization of Single Phase PWM DC-AC Inverter by Particle Swarm Optimizations." Journal of Advanced Computational Intelligence and Intelligent Informatics 18, no. 3 (2014): 435–42. http://dx.doi.org/10.20965/jaciii.2014.p0435.

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We consider the design procedure for a single-phase PWM DC-AC inverter using a particle swarm optimization algorithm. The switching operation is the most important component of the single-phase PWM DC-AC inverter. The PSO algorithm optimizes the switching angle effectively. The design procedure of the switching angle evaluates total harmonic distortion and the effective value of output. The proposed evaluation function restricts the scope to evaluating harmonic components. Based on numerical simulation results, we confirmed that the performance of the proposed design procedure was improved com

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Yang, Junping, and Qinghua Song. "Fault Diagnosis of Support Vector Machine Analog Circuits Based on Improved Particle Swarm Optimization." Journal of Nanoelectronics and Optoelectronics 18, no. 6 (2023): 743–52. http://dx.doi.org/10.1166/jno.2023.3417.

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The development of electronic circuits requires that the reliability and security of circuit equipment and system operation are also increasing. In addition, due to the complexity of the operating environment, it is very important to strengthen the fault diagnosis and real-time testing technology of analog circuits in circuit systems. Based on this, this paper studied the fault diagnosis of analog circuits with Support Vector Machine (SVM), and introduced Improved Particle Swarm Optimization (IPSO) algorithm to optimize the parameters of SVM. In other words, the dynamic weight setting and fact

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Zhou, Yang, Sitao Zhang, and Chongyi Chen. "Optimization and improvement of voltage mode band-gap reference circuit and current mode band-gap reference circuit based on comparative analysis method." Theoretical and Natural Science 25, no. 1 (2023): 136–43. http://dx.doi.org/10.54254/2753-8818/25/20240946.

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Voltage mode band-gap reference source and current mode band-gap reference source is the basic unit of integrated circuit, which plays an important role in some circuit systems such as low-voltage linear regulator, power control chip and analog-to-digital/analog-to-digital converter. Band-gap reference circuit is divided into voltage mode band-gap reference circuit and current mode band-gap reference circuit, and their basic principles and optimization methods are different. The voltage mode bandgap reference voltage is generated by superimposing voltages with positive and negative temperature

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Chen, Yuzhu, Xin Liu, Longqi Wang, et al. "Research and Optimization of High-Performance Front-End Circuit Noise for Inertial Sensors." Sensors 24, no. 3 (2024): 805. http://dx.doi.org/10.3390/s24030805.

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An inertial sensor is a crucial payload in China’s Taiji program for space gravitational wave detection. The performance of the capacitive displacement sensing circuit in the low-frequency band (0.1 mHz to 1 Hz) is extremely important because it directly determines the sensitivity of the space gravitational wave detection missions. Therefore, significant, yet challenging, tasks include decreasing the low-frequency noise in capacitive displacement sensing circuits and improving the capacitive sensing resolution. This study analyzes the noise characteristics of the pre-amplifier circuit within t

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Fu, Xiaqing. "Optimizing performance: A comprehensive study of 4-bit absolute value detector circuit using static CMOS technology." Journal of Physics: Conference Series 2786, no. 1 (2024): 012006. http://dx.doi.org/10.1088/1742-6596/2786/1/012006.

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Abstract In the realm of computing advancements, the utilization of numerical comparators has become increasingly pervasive. This scholarly paper delves into the intricacies of a 4-bit absolute value detector circuit, employing a foundation rooted in static CMOS. The comprehensive exploration encompasses both circuit determination and optimization methodologies. The experimental phase entails the derivation of the simplest absolute value converter circuit through the synthesis of a logic expression derived from a truth table. Subsequently, the minimum critical path delay is computed using the

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Chen, Chuandong, Rongshan Wei, Shaohao Wang, and Wei Hu. "Novel Verification Method for Timing Optimization Based on DPSO." VLSI Design 2018 (March 21, 2018): 1–8. http://dx.doi.org/10.1155/2018/8258397.

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Timing optimization for logic circuits is one of the key steps in logic synthesis. Extant research data are mainly proposed based on various intelligence algorithms. Hence, they are neither comparable with timing optimization data collected by the mainstream electronic design automation (EDA) tool nor able to verify the superiority of intelligence algorithms to the EDA tool in terms of optimization ability. To address these shortcomings, a novel verification method is proposed in this study. First, a discrete particle swarm optimization (DPSO) algorithm was applied to optimize the timing of th

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