Relevant bibliographies by topics / CMOS circuit

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'CMOS circuit'

Author: Grafiati
Published: 4 June 2021
Last updated: 25 July 2025

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Journal articles on the topic "CMOS circuit"

1

He, Xinyu. "Design of CMOS circuits through transistor sizing techniques." Applied and Computational Engineering 12, no. 1 (2023): 1–12. http://dx.doi.org/10.54254/2755-2721/12/20230279.

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With the increasingly diverse functional requirements of contemporary electronic products, the complexity of CMOS circuits often used in chips becomes higher and the number of transistors used increases. To solve the resulting performance problems of CMOS circuits, researchers have searched for many transistor sizing technologies. This paper summarizes three methods of CMOS circuit optimization. The paper introduces these three methods in terms of principle, effect, and application scenarios, and compares them respectively. Through analysis and simulation, it can be found that the use of these
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Prajapati, Pankaj P., Anilkumar J. Kshatriya, Sureshbhai L. Bharvad, and Abhay B. Upadhyay. "Performance analysis of CMOS based analog circuit design with PVR variation." Bulletin of Electrical Engineering and Informatics 12, no. 1 (2023): 141–48. http://dx.doi.org/10.11591/eei.v12i1.4357.

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Process, supply voltage, and temperature (PVT) are three important factors which contribute to performance variation of the complementary metal–oxide–semiconductor (CMOS) based analog circuits. In this paper, CMOS based analog circuit design with the PVT variation effects are explored. The effects of the PVT variation on the performance of CMOS based analog circuits are introduced. The optimization of CMOS based analog circuits such as differential amplifier (DA) and two-stage operational amplifier (op amp) circuits with PVT variations with different algorithms such as cockoo search (CS), part
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KIM, JEONG BEOM. "CURRENT MODE CMOS QUATERNARY LOGIC FULL-ADDER." Journal of Circuits, Systems and Computers 18, no. 01 (2009): 199–208. http://dx.doi.org/10.1142/s0218126609005022.

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This paper proposes a quaternary-to-binary logic decoder, a quaternary current buffer, and a quaternary full-adder using current-mode multiple-valued logic (MVL) CMOS circuits. The proposed full-adder is superior to the previous MVL CMOS circuit in both the circuit occupied area and the performance. Comparing with the binary logic full-adder, the proposed full-adder is superior in the circuit occupied area. However, the circuit performance is inferior to the binary logic full-adder. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.25 μm stan
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Oktay, Aytar. "The Investigation of Auto-Zero Comparator Performance of Common Gate Differential Amplifier Based CMOS Inverter Circuit." Journal of Scientific, Technology and Engineering Research (JSTER) 1, no. 2 (2020): 25–32. https://doi.org/10.5281/zenodo.4069563.

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<strong>The Investigation of Auto-Zero Comparator Performance of Common Gate Differential Amplifier Based CMOS Inverter Circuit</strong> <em><strong>Abstract</strong> - In this study, the performance of the common gate difference amplifier cmos inverter circuit as an auto-zero comparator circuit was investigated using 0.18&mu;m CMOS process model in the NCSU Design Kit of the Cadence IC5141 design program. The performance of the proposed structure was compared with traditional inverter circuit and darlington cmos inverter circuit. In accordance with the results of DC analysis, the voltage gain
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Chen, Jiahao. "Integrated circuit design based on CMOS technology principle and its application in GPU." Theoretical and Natural Science 12, no. 1 (2023): 141–46. http://dx.doi.org/10.54254/2753-8818/12/20230454.

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In today's society, the application of integrated circuit technology can be seen everywhere, especially in the past two decades. This paper mainly studies the principle and design of CMOS devices in IC technology and discusses the research and analysis of the acceleration algorithm of IC design. This paper adopts the research method of literature review and analysis to summarize the existing research results. This paper first introduces the development background of integrated circuit technology and the importance of CMOS technology. Subsequently, the concept and interconnection principle of C
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HURST, S. L. "Open-circuit testing of CMOS circuits." International Journal of Electronics 62, no. 2 (1987): 161–65. http://dx.doi.org/10.1080/00207218708920964.

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Bae, Woorham. "CMOS Inverter as Analog Circuit: An Overview." Journal of Low Power Electronics and Applications 9, no. 3 (2019): 26. http://dx.doi.org/10.3390/jlpea9030026.

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Since the CMOS technology scaling has focused on improving digital circuit, the design of conventional analog circuits has become more and more difficult. To overcome this challenge, there have been a lot of efforts to replace conventional analog circuits with digital implementations. Among those approaches, this paper gives an overview of the latest achievement on utilizing a CMOS inverter as an analog circuit. Analog designers have found that a simple resistive feedback pulls a CMOS inverter into an optimum biasing for analog operation. Recently developed applications of the resistive-feedba
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WANG, WEIZHI, and DONGMING JIN. "CMOS DESIGN OF ANALOG FUZZY SYSTEM." Journal of Circuits, Systems and Computers 14, no. 06 (2005): 1101–12. http://dx.doi.org/10.1142/s0218126605002830.

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This paper proposes several improved CMOS analog integrated circuits for fuzzy inference system as the general modules, including voltage-mode implementations of minimization circuit, programmable Gaussian-like membership function circuit, and centroid algorithm normalization circuit without using division. A two-input/one-output fuzzy system composed of these circuits is implemented and testified as a nonlinear function approximator. HSPICE simulation results show that the proposed circuits provide characteristics of high operation capacity, simple inference, low power dissipation, and high p
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SOLIMAN, AHMED M., and AHMED H. MADIAN. "MOS-C KHN FILTER USING VOLTAGE OP AMP, CFOA, OTRA AND DCVC." Journal of Circuits, Systems and Computers 18, no. 04 (2009): 733–69. http://dx.doi.org/10.1142/s021812660900523x.

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MOS-C realizations of the Kerwin–Huelsman–Newcomb (KHN) circuit using the commercially available Voltage Operational Amplifier (VOA) and the Current Feedback Operational Amplifier (CFOA) are reviewed in this paper. Additional MOS-C KHN realizations using the Operational Transresistance Amplifier (OTRA) and the Differential Current Voltage Conveyor (DCVC) are also included. MOS-C realizations of the KHN circuit using CMOS operational amplifier, CMOS current feedback operational amplifier and CMOS operational transresistance amplifier are also given. Spice simulation results using 0.18 CMOS tech
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M. Surekha, V. HariKrishna, B. MadhuSudhan Reddy, G.Tejaswini, I.Rajasekhar, and K.Divya. "Efficient Approaches to Design Full Adder Using Domino Logic Technique." international journal of engineering technology and management sciences 7, no. 2 (2023): 283–88. http://dx.doi.org/10.46647/ijetms.2023.v07i02.033.

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Static CMOS and Domino CMOS Circuits are significantly used in high performance VLSI system. Designing a circuit with low power, high speed performance is one of the challenging aspects. In modern VLSI systems area efficient devices are utmost popular because most of the devices are becoming portable. This paper proposes One- bit full adder circuit is designed using CMOS based on mirror logic and Domino CMOS also designed based on same logic with LTSPICE at 180nm technology with 1.8V supply. This method provides better power and delay.
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Dissertations / Theses on the topic "CMOS circuit"

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Madhyastha, Sadhana. "Design of circuit breakers for large area CMOS VLSI circuits." Thesis, McGill University, 1989. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=59551.

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Large-area ICs require adequate defect-tolerance to achieve a reasonable yield. One concern is that the power distribution network is shared by a number of modules, and any single short between the supply (V$ sb{dd}$) and ground can disable all these modules. The object of this thesis is to evaluate the feasibility of incorporating circuit breakers in large area ICs, which provide protection against such defects by disconnecting the defective modules from the array. A critical analysis and comparison of MOS transistors and parasitic bipolar transistors as circuit breakers are carried out. It i
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Ramirez, Ortiz Rolando. "Circuit design rules for mixed static and dynamic CMOS logic circuits." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp03/NQ37076.pdf.

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Ramirez, Ortiz Rolando Carleton University Dissertation Engineering Electronics. "Circuit design rules for mixed static and dynamics CMOS logic circuits." Ottawa, 1999.

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Zell, Christopher William. "Electrical effects of CMOS circuit packaging." Diss., The University of Arizona, 1996. http://hdl.handle.net/10150/187456.

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Integrated systems are becoming so complex, it is extremely difficult for designers to simulate full systems, particularly early in the design process. What the designer needs is a methodology to quickly look at where he/she is going, and determine if there are any potential packaging related problems. If so, where did the problem originate, and what can be done about it? The designer wants a quick, easy to use and understand methodology which consistently yields reasonably accurate results. This dissertation is limited to CMOS circuits interfacing with metal interconnects. Of particular inter
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Buttar, Alistair George. "CMOS process simulation." Thesis, University of Edinburgh, 1986. http://hdl.handle.net/1842/13282.

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He, Lizhong. "1-Ghz CMOS Analog Signal Squaring Circuit." Wright State University / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=wright1472476550.

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Yang, Hong. "Circuit Design and Reliability of a CMOS Receiver." Doctoral diss., University of Central Florida, 2004. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2102.

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This dissertation explores CMOS RF design and reliability for portable wireless receivers. The objective behind this research is to achieve an increase in integration level, and gain more understanding for RF reliability. The fields covered include device, circuit and system. What is under investigation is a multi-band multi-mode receiver with GSM, DCS-1800 and CDMA compatibility. To my understanding, GSM and CDMA dual-mode mobile phones are progressively investigated in industries, and few commercial products are available. The receiver adopts direct conversion architecture. Some improved cir
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Jin, Yalin. "Radio-frequency integrated-circuit design for CMOS single-chip UWB systems." Thesis, [College Station, Tex. : Texas A&M University, 2008. http://hdl.handle.net/1969.1/ETD-TAMU-2724.

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Rodnunsky, Nelson Lawrence. "Analysis of power dissipations in CMOS circuit designs." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0005/MQ34409.pdf.

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Phang, Khoman S. "CMOS optical preamplifier design using graphical circuit analysis." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/NQ58961.pdf.

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Books on the topic "CMOS circuit"

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Annaratone, Marco. Digital CMOS Circuit Design. Springer US, 1986. http://dx.doi.org/10.1007/978-1-4613-2285-6.

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Allen, P. E. CMOS analog circuit design. Saunders College Publishing, 1987.

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Shoji, Masakazu. CMOS digital circuit technology. Prentice Hall, 1988.

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Annaratone, Marco. Digital CMOS Circuit Design. Springer US, 1986.

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Shoji, Masakazu. CMOS digital circuit technology. Prentice-Hall International, 1988.

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Uyemura, John P. CMOS logic circuit design. Kluwer Academic Publishers, 1999.

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Allen, P. E. CMOS analog circuit design. 2nd ed. Oxford University Press, 2002.

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R, Holberg Douglas, ed. CMOS analog circuit design. 3rd ed. Oxford University Press, USA, 2011.

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R, Holberg Douglas, ed. CMOS analog circuit design. Oxford University Press Inc., 1987.

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R, Holberg Douglas, ed. CMOS analog circuit design. Holt, Rinehart and Winston, 1987.

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Book chapters on the topic "CMOS circuit"

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Castello, Rinaldo. "CMOS Buffer Amplifiers." In Analog Circuit Design. Springer US, 1993. http://dx.doi.org/10.1007/978-1-4757-2233-8_6.

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Wouter, D., J. Groeneveld, and Douwe T. de Jong. "Groundbounce in CMOS." In Analog Circuit Design. Springer US, 1994. http://dx.doi.org/10.1007/978-1-4757-2310-6_1.

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Tiemeijer, L. F., L. M. F. de Maaijer, R. van Langevelde, A. J. Scholten, and D. B. M. Klaassen. "RF CMOS Modelling." In Analog Circuit Design. Springer US, 1999. http://dx.doi.org/10.1007/978-1-4757-3047-0_6.

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Seevinck, Evert. "CMOS Translinear Circuits." In Analog Circuit Design. Springer US, 2001. http://dx.doi.org/10.1007/978-1-4613-1443-1_15.

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Labiod, Samir, Abdelmalek Mouatsi, Zakaria Hadef, and Billel Smaani. "Conventional CMOS circuit design." In Device Circuit Co-Design Issues in FETs. CRC Press, 2023. http://dx.doi.org/10.1201/9781003359234-2.

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Uyemura, John P. "Analog CMOS Circuits." In Circuit Design for CMOS VLSI. Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3620-8_9.

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Uyemura, John P. "Introduction to CMOS." In Circuit Design for CMOS VLSI. Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3620-8_1.

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Uyemura, John P. "The CMOS Inverter." In Circuit Design for CMOS VLSI. Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3620-8_3.

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Uyemura, John P. "CMOS Switch Logic." In Circuit Design for CMOS VLSI. Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3620-8_5.

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Kumar, Abhishek. "CMOS Bootstrap Driver." In Electronic Devices and Circuit Design. Apple Academic Press, 2021. http://dx.doi.org/10.1201/9781003145776-4.

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Conference papers on the topic "CMOS circuit"

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Mallick, Soumen, Shibendu Mahata, Saikat Layek, Arinjoy Mitra, and Bikram Rajak. "Automated Design of CMOS-DACML Circuit." In 2024 IEEE International Conference on Communication, Computing and Signal Processing (IICCCS). IEEE, 2024. http://dx.doi.org/10.1109/iicccs61609.2024.10763693.

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Bagri, Manju, Manoj Kumar, and Ramnish Kumar. "Design of CMOS based Low Power DCO using MT-CMOS technique." In 2025 Devices for Integrated Circuit (DevIC). IEEE, 2025. https://doi.org/10.1109/devic63749.2025.11012317.

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Singh, Jagmeet, Kondrakunta Prasanth Babu, Samala Harshith, and Suman Lata Tripathi. "CMOS Analog Artificial Neural Network." In 2025 Devices for Integrated Circuit (DevIC). IEEE, 2025. https://doi.org/10.1109/devic63749.2025.11012358.

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Xiao, Yang, Martin A. Trefzer, Scott Roy, James Alfred Walker, Simon J. Bale, and Andy M. Tyrrell. "Circuit optimization using device layout motifs." In 2014 5th European Workshop on CMOS Variability (VARI). IEEE, 2014. http://dx.doi.org/10.1109/vari.2014.6957081.

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Polonsky, Stas, Alan Weger, and Moyra McManus. "Picosecond Imaging Circuit Analysis of Leakage Currents in CMOS Circuits." In ISTFA 2002. ASM International, 2002. http://dx.doi.org/10.31399/asm.cp.istfa2002p0387.

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Abstract The light emission from ever increasing OFF-state leakage currents in advanced CMOS technologies can now be reliably measured using existing photon detectors. The measurements of such an emission provide valuable information about the operation of ICs. In this paper we suggest and experimentally confirm two new techniques based on such measurements - Transient Logic State Detection and Power Supply Noise Analysis.
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Gaugel, Daniel M., and Kaigham J. Gabriel. "CMOS-Compatible Micro-Fluidic Chip Cooling Using Buried Channel Fabrication." In ASME 2002 International Mechanical Engineering Congress and Exposition. ASMEDC, 2002. http://dx.doi.org/10.1115/imece2002-33644.

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We present a CMOS-compatible method of fabricating burried channels within bulk single-crystal silicon serving as the substrate of CMOS circuitry. The channels were designed to provide a compact, forced convection heat transfer liquid cooling approach to microprocessor and integrated circuit thermal management. The baseline fabrication process consumers 8–10% of front-side surface area and serves as a foundation for incorporation of buried-channel cooling with CMOS electronics. Channels were fabricated with diameters ranging from 43–92 μm with sacrificial surface area trenches 10 μm wide. A mi
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Jung, Seung-Ho, Jong-Humn Baek, and Seok-Yoon Kim. "Short circuit power estimation of static CMOS circuits." In the 2001 conference. ACM Press, 2001. http://dx.doi.org/10.1145/370155.370528.

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Liu, Weihsing. "CMOS current-reversing circuit." In 2018 7th International Symposium on Next Generation Electronics (ISNE). IEEE, 2018. http://dx.doi.org/10.1109/isne.2018.8394708.

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Slager, J., K. Gudger, T. Williams, et al. "Competing CMOS circuit techniques." In 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers. IEEE, 1993. http://dx.doi.org/10.1109/isscc.1993.280075.

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Km, Jeong Beom. "Novel TSC CMOS circuit." In 2009 IEEE 8th International Conference on ASIC (ASICON). IEEE, 2009. http://dx.doi.org/10.1109/asicon.2009.5351199.

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Reports on the topic "CMOS circuit"

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Nuckolls, L. CMOS ASIC (application specific integrated circuit). Office of Scientific and Technical Information (OSTI), 1989. http://dx.doi.org/10.2172/5551185.

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Lim, Chee. High-performance Input/Output Circuit for CMOS Integrated Circuit Interface. Portland State University Library, 2000. http://dx.doi.org/10.15760/etd.7186.

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Mahooti, Rabe'eh. A CMOS circuit generator using differential pass transistors for implementing Boolean functions. Portland State University Library, 2000. http://dx.doi.org/10.15760/etd.5689.

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Brocco, Lynne M. Macromodeling CMOS Circuits for Timing Simulation. Defense Technical Information Center, 1987. http://dx.doi.org/10.21236/ada459654.

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Likharev, Konstantin K., and James Lukens. Fundamental Problems of Hybrid CMOS/Nanodevice Circuits. Defense Technical Information Center, 2010. http://dx.doi.org/10.21236/ada564340.

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Likharev, Konstantin K., and James Lukens. Fundamental Problems of Hybrid CMOS/Nanodevice Circuits. Defense Technical Information Center, 2010. http://dx.doi.org/10.21236/ada565890.

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Resnick, Douglas, and Konstantin Likharev. Hybrid CMOS/Nanodevice Integrated Circuits Design and Fabrication. Defense Technical Information Center, 2008. http://dx.doi.org/10.21236/ada487894.

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Pouliquen, Philippe O., and Mark N. Martin. Latch-Up Detection and Cancellation in CMOS VLSI Circuits. Defense Technical Information Center, 2000. http://dx.doi.org/10.21236/ada399884.

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Chang, Young-hoon, and Jon T. Butler. The Design of Current Mode CMOS Multiple-Valued Circuits. Defense Technical Information Center, 1991. http://dx.doi.org/10.21236/ada608087.

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Onneweer, Siep, Hans Kerkhoff, and Jon Butler. Structural Computer-Aided Design of Current-Mode CMOS Logic Circuits. Defense Technical Information Center, 1988. http://dx.doi.org/10.21236/ada608071.

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