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Relevant bibliographies by topics / Microelectronic technology / Dissertations / Theses

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Dissertations / Theses on the topic 'Microelectronic technology'

Author: Grafiati

Published: 28 May 2022

Last updated: 30 July 2025

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1

Al-Nedawe, Basman M. "Microelectronic implementation of dicode PPM system employing RS codes." Thesis, University of Huddersfield, 2014. http://eprints.hud.ac.uk/id/eprint/26229/.

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Optical fibre systems have played a key role in making possible the extraordinary growth in world-wide communications that has occurred in the last 25 years, and are vital in enabling the proliferating use of the Internet. Its high bandwidth capabilities, low attenuation characteristics, low cost, and immunity from the many disturbances that can afflict electrical wires and wireless communication links make it ideal for gigabit transmission and a major building block in the telecommunication infrastructure. A number of different techniques are used for the transmission of digital information b

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2

Zhu, Qi. "Helix-type compliant off-chip interconnect for microelectronic packaging." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/17541.

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3

Li, Yiming. "Plasma processing of advanced interconnects for microelectronic applications." Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/11034.

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4

Ma, Lunyu. "Design and development of stress-engineered compliant interconnect in microelectronic packaging." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/16066.

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5

Haemer, Joseph Michael. "Thermo-mechanical modeling and design of micro-springs for microelectronic probing and packaging." Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/16830.

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6

Zhang, Jian. "In-process stress analysis of flip chip assembly and reliability assessment during environmental and power cycling tests." Diss., Available online, Georgia Institute of Technology, 2004:, 2003. http://etd.gatech.edu/theses/available/etd-04082004-180504/unrestricted/zhang%5fjian%5f200312%5fphd.pdf.

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7

Ma, Wei. "Low temperature metal-based micro fabrication and packaging technology /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?MECH%202005%20MA.

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8

McCaslin, Luke. "Methodology for predicting microelectronic substrate warpage incorporating copper trace pattern characteristics." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24641.

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9

Lin, Ta-Hsuan. "Assembly process development, reliability and numerical assessment of copper column flexible flip chip technology." Diss., Online access via UMI:, 2008.

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Thesis (Ph. D.)--State University of New York at Binghamton, Department of Systems Science and Industrial Engineering, Thomas J. Watson School of Engineering and Applied Science, 2008.<br>Includes bibliographical references.

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10

Ng, Siu Lung. "Effect of thermal and mechanical factors on single and multi-chip BGA packages." Diss., Online access via UMI:, 2007.

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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2007.<br>Includes bibliographical references.

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11

Prabhakumar, Ananth. "System based material design for wafer level underfills :." Diss., Online access via UMI:, 2004.

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Thesis (Ph. D.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Systems Science Dept., 2004<br>Only abstract available. "At the request of the author, this graduate work is not available for purchase." Includes bibliographical references.

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12

Lightsey, Charles Hunter. "All-copper chip-to-substrate interconnections for flip-chip packages." Thesis, Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/34729.

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Avatrel 8000P's excellent photo-definition properties and mechanical strength make it an ideal polymer collar material. Avatrel 8000P is a high contrast, I-line sensitive mixture that can be developed in traditional aqueous-base developers. The great photolithographical performance of this photopolymer can be partly contributed to the minimal amount of light absorbed by the base norbornene polymer. The processing conditions noted in this work are an optimized version, which have been shown to give superior photolithographical performance. The simple baking procedures make Avatrel 8000P eas

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13

Baynham, Grant Andrew. "Flip chip processing of lead-free solders and halogen-free high density microvia substrates." Thesis, Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/19313.

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14

Zhu, Boyuan. "The Electromagnetic Compatibility Problems of Integrated Circuits." Thesis, Griffith University, 2011. http://hdl.handle.net/10072/365527.

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With the constant speed of growth in semiconductor technology, integrated circuit (IC) has taken a considerable position in an electronic system. The integrated circuit is working in a low supply voltage with high operation frequency. The internal complexity and chip density are also increased dramatically. Modern microelectronic technology in wafer fabrication easily allows component densities to exceed one million transistors per die. So far, integrated circuits are suering from various and complicated electromagnetic environments. Being the heart of an electronic system, stability and relia

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15

Sundaram, Venkatesh. "Advances in electronic packaging technologies by ultra-small microvias, super-fine interconnections and low loss polymer dielectrics." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/28141.

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Thesis (M. S.)--Materials Science and Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Tummala, Rao; Committee Member: Iyer, Mahadevan; Committee Member: Saxena, Ashok; Committee Member: Swaminathan, Madhavan; Committee Member: Wong, Chingping.

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16

Rivers, Norman. "An investigation of BGA electronic packaging using Moiré interferometry." [Tampa, Fla. : s.n.], 2003. http://purl.fcla.edu/fcla/etd/SFE0000078.

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17

Lee, Sangil. "Fundamental study of underfill void formation in flip chip assembly." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/29755.

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Thesis (Ph.D)--Mechanical Engineering, Georgia Institute of Technology, 2010.<br>Committee Chair: Baldwin, Daniel; Committee Member: Colton, Jonathan; Committee Member: Ghiaasiaan, Mostafa; Committee Member: Moon, Jack; Committee Member: Tummala, Rao. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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18

Huang, Xingjia. "Investigation and analysis on the solder ball shear strength of plastic ball grid array, chip scale, and flip chip packages with eutectic Pb-Sn and Pb-free solders /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?MECH%202003%20HUANG.

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19

Miller, Ross Alan. "Thermo-Mechanical Selective Laser Assisted Die Transfer." Thesis, North Dakota State University, 2011. https://hdl.handle.net/10365/29859.

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Laser Induced Forward Transfer (LIFT) techniques show promise as a disruptive technology which will enable the placement of components smaller than what conventional pick-and-place techniques are capable of today. Limitations of current die-attach techniques are presented and discussed and present the opportunity for a new placement method. This study introduces the Thermo-Mechanical Selective Laser Assisted Die Transfer (tmSLADT) process and is an application of the unique blistering behavior of a dynamic releasing layer when irradiated by low energy focused UV laser pulses. The potential of

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20

Zheng, Leo Young. "Modeling and experiments of underfill flow in a large die with a non-uniform bump pattern." Diss., Online access via UMI:, 2008.

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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2008.<br>Includes bibliographical references.

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21

Lee, Dong Gun. "Strain measurement of flip-chip solder bumps using digital image correlation with optical microscopy." Diss., Online access via UMI:, 2009.

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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2009.<br>Includes bibliographical references.

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22

Liang, Hongwei. "Development of microwave and millimeter-wave pin grid array and ball grid array packages." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/14867.

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23

Mehrotra, Gaurav. "Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/22594.

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24

Kacker, Karan. "Design and fabrication of free-standing structures as off-chip interconnects for microsystems packaging." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26464.

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Thesis (Ph.D)--Mechanical Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Dr. Suresh K. Sitaraman; Committee Member: Dr. F. Levent Degertekin; Committee Member: Dr. Ioannis Papapolymerou; Committee Member: Dr. Madhavan Swaminathan; Committee Member: Dr. Nazanin Bassiri-Gharb. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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25

Jha, Gopal Chandra. "Copper to copper bonding by nano interfaces for fine pitch interconnections and thermal applications." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/22588.

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26

Jiang, Hongjin. "Synthesis of tin, silver and their alloy nanoparticles for lead-free interconnect applications." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/22636.

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Thesis (Ph. D.)--Chemistry and Biochemistry, Georgia Institute of Technology, 2008.<br>Committee Chair: Dr. C. P. Wong; Committee Member: Dr. Boris Mizaikoff; Committee Member: Dr. Rigoberto Hernandez; Committee Member: Dr. Z. John Zhang; Committee Member: Dr. Z.L. Wang.

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27

Osborn, Tyler Nathaniel. "All-copper chip-to-substrate interconnects for high performance integrated circuit devices." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/28211.

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Thesis (M. S.)--Chemical Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Kohl, Paul; Committee Member: Bidstrup Allen, Sue Ann; Committee Member: Fuller, Thomas; Committee Member: Hesketh, Peter; Committee Member: Hess, Dennis; Committee Member: Meindl, James.

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28

Khan, Sadia Arefin. "Electromigration analysis of high current carrying adhesive-based copper-to-copper interconnections." Thesis, Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/44885.

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"More Than Moore's Law" is the driving principle for the electronic packaging industry. This principle focuses on system integration instead of transistor density in order to achieve faster, thinner, and smarter electronic devices at a low cost. A core area of electronics packaging is interconnection technology, which enables ultra-miniaturization and high functional density. Solder bump technology is one of the original, and most common interconnection methods for flip chips. With growing demand for finer pitch and higher number of I/Os, solder bumps have been forced to smaller dimensions and

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29

Ramasubramanian, Arun Shrrivats. "Advanced process window design for 01005 assemblies." Diss., Online access via UMI:, 2008.

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Thesis (M.S.)--State University of New York at Binghamton, Department of Systems Science and Industrial Engineering, Thomas J. Watson School of Engineering and Applied Science, 2008.<br>Includes bibliographical references.

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30

Ткач, Олена Петрівна, Елена Петровна Ткач, Olena Petrivna Tkach та ін. "Акустоелектронний сенсор фізичних величин на поверхневих акустичних хвилях". Thesis, Сумський державний університет, 2018. http://essuir.sumdu.edu.ua/handle/123456789/67906.

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Розроблення сенсорних пристроїв на вітчизняному та світовому ринках є прогресивним напрямом в подальшому розвитку наноелектроніки. На основі поверхневих хвиль розроблена велика кількість сенсорів з високими показниками точності, що дозволяють вимірювати вагу, тиск, прискорення та ін. До переваг даних пристроїв можна віднести те, що вони створюються на основі елементів інтегральної електроніки, оптики та різноманітних мікроелектронних технологій і при цьому забезпечують контроль декількох фізичних величин. Проте актуальними залишаються питання пошуку нових матеріалів для підкладки та топології

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31

Tumne, Pushkraj Satish. "Investigation of bulk solder and intermetallic failures in PB free BGA by joint level testing." Diss., Online access via UMI:, 2009.

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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department or Systems Science and Industrial Engineering, 2009.<br>Includes bibliographical references.

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32

Ramkumar, S. Manian. "Process analysis and performance characterization of a novel anisotropic conductive adhesive for lead-free surface mount electronics assembly." Diss., Online access via UMI:, 2008.

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33

Colella, Michael. "Evaluation, Optimization,and Reliability of No-flow Underfill Process." Thesis, Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-01262004-204348/unrestricted/colella%5Fmichael%5F200405%5Fms.pdf.

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Thesis (M.S.)--Mechanical Engineering, Georgia Institute of Technology, 2004.<br>Daniel Baldwin, Committee Chair; Suresh Sitaraman, Committee Member; Steven Danyluk, Committee Member. Includes bibliographical references (leaves 238-241).

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34

Majeed, Sulman. "Rework & reliability of area array components." Diss., Online access via UMI:, 2009.

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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engfineering and Applied Science, Department of Systems Science and Industrial Engineering, 2009.<br>Includes bibliographical references.

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35

Yoon, Sangwoong. "LC-tank CMOS Voltage-Controlled Oscillators using High Quality Inductor Embedded in Advanced Packaging Technologies." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4887.

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This dissertation focuses on high-performance LC-tank CMOS VCO design at 2 GHz. The high-Q inductors are realized using wiring metal lines in advanced packages. Those inductors are used in the resonator of the VCO to achieve low phase noise, low power consumption, and a wide frequency tuning range. In this dissertation, a fine-pitch ball-grid array (FBGA) package, a multichip module (MCM)-L package, and a wafer-level package (WLP) are incorporated to realize the high-Q inductor. The Q-factors of inductors embedded in packages are compared to those of inductors monolithically integrated on Si

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36

Boussetta, Hatem. "Étude et réalisation de transistors bipolaires à pseudo-hétérojonction dans le cadre d'une technologie microélectronique BiCMOS." Grenoble 1, 1995. http://www.theses.fr/1995GRE10024.

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Ce travail s'inscrit dans le cadre de l'etude de transistors bipolaires a bases epitaxiees fortement dopees realises dans la technologie bicmos du centre national d'etudes des telecommunications de meylan. Grace au fort dopage de la base, le fonctionnement de ces transistors se rapproche de celui des transistors bipolaires a heterojonctions ; pour cette raison on les nomme transistors bipolaires a pseudo heterojonction. Apres avoir presente la nouvelle structure emetteur-base et la technologie de fabrication bicmos, nous decrivons les techniques et les outils de caracterisation mis en jeu. Dan

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37

Bhat, Anirudh. "Response of multi-path compliant interconnects subjected to drop and impact loading." Thesis, Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/50132.

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Conventional solder balls used in microelectronic packaging suffer from thermo- mechanical damage due to difference in coefficient of thermal expansion between the die and the substrate or the substrate and the board. Compliant interconnects are replacements for solder balls which accommodate this differential displacement by mechanically decoupling the die from the substrate or the substrate from the board and aim to improve overall reliability and life of the microelectronic component. Research is being conducted to develop compliant interconnect structures which offer good mechanical compli

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38

Gravier, Thierry. "Etude de l'architecture émetteur/base de transistors bipolaires simple polysilicium pour filières BICMOS 0. 5-0. 35 µm." Université Joseph Fourier (Grenoble), 1996. http://www.theses.fr/1996GRE10262.

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Ce travail concerne les architectures de transistors bipolaires npn a un niveau de polysilicium (emetteur), compatibles avec les technologies cmos. Nous proposons des concepts novateurs dans le but de repousser l'utilisation de ce type d'architecture pour des technologies bicmos 0,35 microns. Dans un premier temps, nous nous sommes interesses a la formation de la base du transistor et avons etudie deux approches nouvelles dans ce domaine. Tout d'abord, des bases minces ont ete obtenues par diffusion du dopant de base (bore) depuis le polysicilium formant l'emetteur. Ce dopant est au prealable

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39

Christensen, John Hayes. "Generalized emulation of microcircuits technology transition strategy." Master's thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-03302010-020434/.

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40

Bharath, Krishna. "Signal and power integrity co-simulation using the multi-layer finite difference method." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/28155.

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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Madhavan Swaminathan; Committee Member: Andrew F. Peterson; Committee Member: David C. Keezer; Committee Member: Saibal Mukhopadyay; Committee Member: Suresh Sitaraman.

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41

Choudhury, Abhishek. "Chip-last embedded low temperature interconnections with chip-first dimensions." Thesis, Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/37104.

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Small form-factor packages with high integration density are driving the innovations in chip-to-package interconnections. Metallurgical interconnections have evolved from the conventional eutectic and lead-free solders to fine pitch copper pillars with lead-free solder cap. However, scaling down the bump pitch below 50-80µm and increasing the interconnect density with this approach creates a challenge in terms of accurate solder mask lithography and joint reliability with low stand-off heights. Going beyond the state of the art flip-chip interconnection technology to achieve ultra-fine bump pi

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42

Agrawal, Akash. "Board level energy comparison and interconnect reliability modeling under drop impact." Diss., Online access via UMI:, 2009.

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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2009.<br>Includes bibliographical references.

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43

Aglen, Andreas Flåt, and Sondre Gullord Graff. "On International Technology Diffusion : A Case Study of the Norwegian Microelectronics Industry." Thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for industriell økonomi og teknologiledelse, 2013. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-24795.

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The study identifies two knowledge networks through which firms can identify and absorb new knowledge. One such knowledge network is nationally oriented, and constitutes of commercial and non-commercial actors situated in a domestic environment. The other network is internationally oriented, and allows national firms to tap into knowledge pools that reside in foreign countries. Research traditions have investigated these networks separately; cluster theory in particular has gotten immensely popular for its emphasis on the local knowledge network. We derive a model of international diffusion th

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44

Ailloud-Boissonnet, Laurence. "Étude et mise au point de transistors bipolaires NPN à structure double-polysilicium intégrables dans une technologie BiCMOS 0,35 µm." Grenoble INPG, 1998. http://www.theses.fr/1998INPG0083.

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L'objet de notre travail etait de developper et d'etudier une architecture de transistors bipolaires double-polysilicium integrables dans une technologie bicmos 0,35 m. La fabrication des transistors bipolaires double-polysilicium sur plaquette de 200 mm a ete realisee pour la premiere fois en france lors de notre etude, au sein de l'equipe mixte st/cnet/leti. Un important travail de mise au point technologique, couple a une optimisation des performances electriques a ete effectue. L'objectif est de fabriquer des transistor bipolaires performants (le cahier des charges precise une frequence de

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45

Save, Didier. "Etude et developpement de technologies d'isolation cmos pour circuits integres ulsi." Toulouse 3, 1988. http://www.theses.fr/1988TOU30011.

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L'isolation des circuits cmos est une des cles de leur miniaturisation extreme. Les technologies d'isolation de l'ulsi devront eliminer les risques de courants de fuite et de "latch up" a la peripherie du caisson, ainsi que les phenomenes perimetriques, dus a l'isolation de champ, qui degradent les performances des petits transistors (tension de seuil, capacite de diffusion). L'isolation dielectrique du caisson par tranchee profonde est choisie ici pour sa compatilibite avec les filieres de fabrication existantes. La principale difficulte de la technique reside dans la gravure parfaitement ver

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46

Bhalerao, Vikram. "Process development and reliability study for 01005 components in a lead-free assembly environment." Diss., Online access via UMI:, 2008.

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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2008.<br>Includes bibliographical references.

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47

Garcia, Alain. "Contribution à l'étude des mécanismes de création de défauts lors de la réalisation de substrats simox." Grenoble INPG, 1995. http://www.theses.fr/1995INPG0057.

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Le simox (separation by implanted oxygen) est un materiau soi qui presente de fortes potentialites dans le domaine de la micro-electronique. Utilise dans les annees 80 pour des applications militaires et spatiale, il est actuellement le principal candidat pour les applications civiles: cmos faible consommation. Apres une etude detaillee des defauts presents dans le materiau, la premiere partie de ce travail a ete consacree a la mise au point de procedures de caracterisation fiables des defauts cristallins. Ces methodes (revelation chimique et topographie x) sont adaptees a caracterisation de f

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48

Mao, Jifeng. "Modeling of simultaneous switching noise in on-chip and package power distribution networks using conformal mapping, finite difference time domain and cavity resonator methods." Diss., Available online, Georgia Institute of Technology, 2005, 2004. http://etd.gatech.edu/theses/available/etd-10062004-125025/.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.<br>Madhavan Swaminathan, Committee Chair ; Sung Kyu Lim, Committee Member ; Abhijit Chatterjee, Committee Member ; David C. Keezer, Committee Member ; C. P. Wong, Committee Member. Vita. Includes bibliographical references.

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49

Choi, Jae Young. "Modeling and simulation for signal and power integrity of electronic packages." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45885.

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The objective of this dissertation is to develop electrical modeling and co-simulation methodologies for signal and power integrity of package and board applications. The dissertation includes 1) the application of the finite element method to the optimization for decoupling capacitor selection and placement on a power delivery network (PDN), 2) the development of a PDN modeling method effective for multidimensional and multilayer geometries, 3) the analysis and modeling of return path discontinuities (RPDs), and 4) the implementation of the absorbing boundary condition for PDN modeling. The

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50

Denorme, Stéphane. "Étude de l'influence des procédés technologiques de type BiCMOS à haute densité d'intégration sur la réalisation de bases fines très dopées dans les transistors bipolaires submicroniques." Université Joseph Fourier (Grenoble ; 1971-2015), 1995. http://www.theses.fr/1995GRE10130.

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Pour la plupart des applications bicmos, l'effort principal porte maintenant sur la reduction de la consommation et la recherche de frequences de fonctionnement elevees et on s'oriente vers des transistors bipolaires a base fine si ou sige tres dopee. Or l'integration croissante des transistors et la reduction des dimensions qu'elle entraine, ont deux effets. D'une part, la reduction des bilans thermiques donne une forte importance a la presence de defauts ponctuels hors equilibre a l'origine de la diffusion acceleree des dopants. D'autre part, l'effet des etapes technologiques creatrices de d

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