Relevant bibliographies by topics / Pass Transistor Logic (PTL)

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Pass Transistor Logic (PTL)'

Author: Grafiati
Published: 4 June 2021
Last updated: 11 February 2022

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Journal articles on the topic "Pass Transistor Logic (PTL)"

1

Cho, Geun Rae, and Tom Chen. "On Mixed PTL/Static Logic for Low-power and High-speed Circuits." VLSI Design 12, no. 3 (January 1, 2001): 399–406. http://dx.doi.org/10.1155/2001/59548.

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We present more evidence in a 0.25 μm CMOS technology that the pass-transistor logic (PTL) structure that mixes conventional PTL structure with static logic gates can achieve better performance and lower power consumption compared to conventional PTL structure. The goal is to use the static gates to perform both logic functions as well as buffering. Our experimental results demonstrate that the proposed mixed PTL structure beats pure static structure and conventional PTL in 9 out of 15 test cases for either delay or power consumption or both in a 0.25 μm CMOS process. The average delay, power consumption, and power-delay product of the proposed structure for 15 test cases are 10% to 20% better of than the pure static implementations and up to 50% better than the conventional PTL implementations.
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Jiang, Jin Tao, Li Fang Ye, and Jian Ping Hu. "Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration." Applied Mechanics and Materials 39 (November 2010): 73–78. http://dx.doi.org/10.4028/www.scientific.net/amm.39.73.

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Leakage power reduction is extremely important in the design of nano-circuits. Gate leakage has become a significant component in currently used nanometer CMOS processes with gate oxide structure. The structure and operation of the PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits that consist mostly of PMOS transistors are complementary to PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) ones that consist mostly of NMOS transistors. This paper investigates gate leakage reduction of the PAL-2P circuits in nanometer CMOS processes with gate oxide materials. An s27 benchmark circuit from the ISCAS89 sequential benchmark set is verified using the PAL-2P scheme. All circuits are simulated with HSPICE using the 65nm CMOS process with gate oxide materials. Based on the power dissipation models of PAL-2P adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations using SPICE simulations. The PAL-2P circuits consume low static power compared with traditional PAL-2N ones.
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Lin, Jin-Fa, Zheng-Jie Hong, Chang-Ming Tsai, Bo-Cheng Wu, and Shao-Wei Yu. "Novel Low-Complexity and Low-Power Flip-Flop Design." Electronics 9, no. 5 (May 10, 2020): 783. http://dx.doi.org/10.3390/electronics9050783.

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In this paper, a compact and low-power true single-phase flip-flop (FF) design with fully static operations is presented. The design is developed by using various circuit-reduction schemes and features a hybrid logic style employing both pass transistor logic (PTL) and static complementary metal-oxide semiconductor (CMOS) logic to reduce circuit complexity. These circuit optimization measures pay off in various aspects, including smaller clock-to-Q (CQ) delay, lower average power, lower leakage power, and smaller layout area; and the transistor-count is only 17. Fabricated in TSMC 180 nm CMOS technology, it reduces by over 29% the chip area compared to the conventional transmission gate FF (TGFF). To further show digital circuit/system level advantages, a multi-mode shift register has been realized. Experimental measurement results at 1.8 V/4 MHz show that, compared with the TGFF design, the proposed design saves 64.7% of power consumption while reducing chip area by 26.2%.
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Ng, K. W., and K. T. Lau. "Improved PAL-2N logic with complementary pass-transistor logic evaluation tree." Microelectronics Journal 31, no. 1 (January 2000): 55–59. http://dx.doi.org/10.1016/s0026-2692(99)00089-0.

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Zhang, Wei Qiang, Li Su, Jun Wang, Bin Bin Liu, and Jian Ping Hu. "Design and Manufacture of Energy-Recycling Pads for Low-Power Chips." Key Engineering Materials 460-461 (January 2011): 467–72. http://dx.doi.org/10.4028/www.scientific.net/kem.460-461.467.

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Energy-recycling output pad cells for driving adiabatic chips are designed, which have been fabricated with Chartered 0.35um process and tested. The proposed energy-recycling output pad cells include mainly bonding pads, electrostatic discharge (ESD) protection circuits, and two stage energy-recycling buffers that are used to drive the large load capacitances on chip pads. The two stage energy-recycling buffers are realized using CPAL (Complementary Pass-transistor Adiabatic Logic) and PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration), respectively. For comparison, a conventional output pad cell is also embedded in the test chip. The function verifications and energy loss tests for the three output pad cells are carried out. The energy consumption of the proposed two energy-recycling output pad cells has large savings over a wide range of frequencies, as compared with the conventional CMOS counterparts, since the energy on large load capacitances in the chip pads can be well recycled.
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Parameshwara, M. C., and H. C. Srinivasaiah. "Low-Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic Applications." Journal of Circuits, Systems and Computers 26, no. 01 (October 4, 2016): 1750014. http://dx.doi.org/10.1142/s0218126617500141.

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A novel “16 transistor” (16T) 1-bit Full adder (FA) circuit based on CMOS transmission-gate (TG) and pass transistor logics (PTL) is presented. This 1-bit FA circuit with TG and PTL structure is derived based on carry dependent sum implementation approach. The design metrics (DMs) such as power, delay, power-delay-product (PDP), and transistor-count (TC) for this 1-bit FA are compared against eight other standard and state-of-the-art 1-bit FA circuits reported till date. All the comparisons are done at post layout level with respect to the DMs under consideration. The proposed 1-bit FA dissipates an average power of 2.118[Formula: see text][Formula: see text]W, with a delay of 606 ps, with an area of 33.1[Formula: see text][Formula: see text]m2, resulting in a PDP of 1.28 fJ. This power and hence the PDP is the lowest of all, ever reported till date. In this comparative study a common test bench with a supply voltage [Formula: see text][Formula: see text]V, input signal frequency [Formula: see text][Formula: see text]MHz is used. This 1-bit FA is designed and implemented using Cadences' 90[Formula: see text]nm “generic-process-design-kit” (GPDK).
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Nuthalapati, Soniya, Ranjitha P.V.Sai, Radhika Rani Kalapala, Lourdu Sasi Rekha Lingisetty, Sirisha Mekala, and Parveen Mohammad Firdosia. "Design a Low Power and High Speed 130nm Fulladder using Exclusive-OR and Exclusive NOR Gates." International Journal of Innovative Technology and Exploring Engineering 10, no. 5 (March 30, 2021): 81–86. http://dx.doi.org/10.35940/ijitee.e8659.0310521.

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This literature illustrates the high speed and low power Full Adder (FADD) designs. This study relates to the composited structure of FADD design composed in one unit. In this the EXCL-OR/EXCL-NOR designs are used to design the FADD. Mostly concentrates on high speed standard FADD structure by combining the EXCL-OR/EXCL-NOR design in single unit. We implemented two composite structures of FADD through the full swing EXCL-OR/EXCL-NOR designs. And the EXCL-OR/EXCL-NOR design is done through pass transistor logic (PTL) and the same design projected on the composited FADD design. Such that the delay, area of the design, power requirement for the circuit gets optimized. The two composited FADD designs are compared and reduced the constraints of power requirement, area, delay and the power delay product (PDP). The simulated outcomes are verified through 130nnm CMOS mentor graphics tool.
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NG, K. W., and K. T. LAU. "A NOVEL ADIABATIC REGISTER FILE DESIGN." Journal of Circuits, Systems and Computers 10, no. 01n02 (February 2000): 67–76. http://dx.doi.org/10.1142/s0218126600000032.

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A novel 8-word × 16-bit adiabatic register file is designed. The adiabatic circuits are based on the Pass-transistor Adiabatic Logic with NMOS pull-down configuration (PAL-2N). Using adiabatic switching technique, the power consumption of the register file is significantly reduced as the energy transferred to the large capacitance buses is mostly recovered. HSPICE simulation results have shown power savings of more than 77% as compared to the conventional CMOS implementation. Although the proposed register file is designed with only one read port and one write port, multiple read and/or write ports can be easily constructed by adding additional read and/or write port transistors.
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Ben-Asher, Yosi, Esti Stein, and Vladislav Tartakovsky. "FPGA Realization of the Reconfigurable Mesh Counting Algorithm." Journal of Circuits, Systems and Computers 30, no. 09 (January 18, 2021): 2150157. http://dx.doi.org/10.1142/s0218126621501577.

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Pass transistor logic (PTL) is a circuit design technique wherein transistors are used as switches. The reconfigurable mesh (RM) is a model that exploits the power of PTLs signal switching, by enabling flexible bus connections in a grid of processing elements containing switches. RM algorithms have theoretical results proving that [Formula: see text] can speed up computations significantly. However, the RM assumes that the latency of broadcasting a signal through [Formula: see text] switches (bus length) is 1. This is an unrealistic assumption preventing physical realizations of the RM. We propose the restricted-RM (RRM) wherein the bus lengths are restricted to [Formula: see text], [Formula: see text]. We show that counting the number of 1-bits in an input of [Formula: see text] bits can be done in [Formula: see text] steps for [Formula: see text] by an [Formula: see text] RRM. An almost matching lower bound is presented, using a technique which adds to the few existing lower-bound techniques in this area. Finally, the algorithm was directly coded over an FPGA, outperforming an optimal tree of adders. This work presents an alternative way of counting, which is fundamental for summing, beating regular Boolean circuits for large numbers, where summing a vast amount of numbers is the basis of any accelerator in embedded systems such as neural-nets and streaming. a
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Bhattacharjee, Pritam, and Alak Majumder. "A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application." Journal of Circuits, Systems and Computers 28, no. 07 (June 27, 2019): 1950108. http://dx.doi.org/10.1142/s0218126619501081.

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Advancement in technology towards mobile computing and communication demands longer battery life, which mandates the low power design methodologies. In this paper, we have presented a novel low-power 8T flip-flop (FF) architecture, which has outsmarted the existing well-known dynamic, semi-dynamic and explicit pulsed flip-flops in terms of power and delay. The major ingredient of this architecture is a voltage keeper, which is incorporated to achieve reliable logic switching at the propagating nodes of the design. However, we have also come up with two new approaches of gated clock generation based on transmission gate (TG) and pass transistor logic (PTL) as a modification of LECTOR-based gating. These gating logics have proved themselves to be competent enough to reduce both the static and dynamic power dissipations and hence are employed to the proposed flip-flop to achieve further reduction in power than its nongated correspondent. The performance of this proposed gated flip-flop is tested in a finite state machine with its application in low-power serial adder design. All the simulations are carried out using 65-nm and 90-nm CMOS technologies with a power supply of 1.1[Formula: see text]V at 6.6[Formula: see text]GHz clock frequency. The gated FF saves 52.12%, 6.36% and 28.18% average power-using LECTOR, TG and PTLs, respectively, with respect to its nongated counterpart in 65-nm technology. The performance metrics of gated and nongated proposed designs are affirmed in the environment of commercialized CMOS foundry.
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Dissertations / Theses on the topic "Pass Transistor Logic (PTL)"

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Garg, Rajesh. "Generalized buffering of pass transistor logic (PTL) stages using Boolean division and don't cares." Texas A&M University, 2003. http://hdl.handle.net/1969.1/5906.

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Pass Transistor Logic (PTL) is a well known approach for implementing digital circuits. In order to handle larger designs and also to ensure that the total number of series devices in the resulting circuit is bounded, partitioned Reduced Ordered Binary Decision Diagrams (ROBDDs) can be used to generate the PTL circuit. The output signals of each partitioned block typically needs to be buffered. In this thesis, a new methodology is presented to perform generalized buffering of the outputs of PTL blocks. By performing the Boolean division of each PTL block using different gates in a library, we select the gate that results in the largest reduction in the height of the PTL block. In this manner, these gates serve the function of buffering the outputs of the PTL blocks, while also reducing the height and delay of the PTL block. PTL synthesis with generalized buffering was implemented in two different ways. In the first approach, Boolean division was used to perform generalized buffering. In the second approach, compatible observability don't cares (CODCs) were utilized in tandem with Boolean division to simplify the ROBDDs and to reduce the logic in PTL structure. Also CODCs were computed in two different manners: one using full simplify to compute complete CODCs and another using, approximate CODCs (ACODCs). Over a number of examples, on an average, generalized buffering without CODCs results in a 24% reduction in delay, and a 3% improvement in circuit area, compared to a traditional buffered PTL implementation. When ACODCs were used, the delay was reduced by 29%, and the total area was reduced by 5% compared to traditional buffering. With complete CODCs, the delay and area reduction compared to traditional buffering was 28% and 6% respectively. Therefore, results show that generalized buffering provides better implementation of the circuits than the traditional buffering method.
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Ragavan, Rengarajan. "Reconfigurable FSM for Ultra-Low Power Wireless Sensor Network Nodes." Thesis, Linköpings universitet, Elektroniska komponenter, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-100121.

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Wireless sensor networks (WSN) play an important role in today’s monitoring and controlsystems like environmental monitoring, military surveillance, industrial sensing and control, smarthome systems and tracking systems. As the application of WSN grows by leaps and bounds, there is anincreasing demand in placing a larger number of sensors and controllers to meet the requirements. Theincreased number of sensors necessitates flexibility in the functioning of nodes. Nodes in wirelesssensor networks should be capable of being dynamically reconfigured to perform various tasks is theneed of the hour.In order to achieve flexibility in node functionality, it is common to adopt reconfigurablearchitecture for WSN nodes. FPGA-based architectures are popular reconfigurable architectures bywhich WSN nodes can be programmed to take up different roles across time. Area and power are themajor overheads in FPGA based architectures, where interconnect consumes more power and area thanlogic cells. The contemporary WSN standard requires longer battery life and micro size nodes for easyplacement and maintenance-free operation for years together.Three solutions have been studied and evaluated to approach this problem: 1) Homogenousembedded FPGA platform, 2) Power gated reconfigurable finite state machines and 3) Pass transistorlogic (PTL) based reconfigurable finite state machines. Embedded FPGA is a CMOS 65nm customdeveloped small homogenous FPGA which holds the functionality of the WSN nodes and it will bedynamically reconfigured from time to time to change the functionality of the node. In Power gatedreconfigurable FSM architecture, the functionality of the node is expressed in the form of finite statemachines, which will be implemented in a LUT based power gated design. In PTL based reconfigurablefinite state machine architecture, the finite state machines are completely realized using PTL basedcustom designed sets of library components. Low power configuration memory is used to dynamicallyreconfigure the design with various FSMs at different times.
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Varadharajan, Swetha. "Digital and Analog Applications of Double Gate Mosfets." Ohio University / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1132759182.

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Henry, Michael B. "Emerging Power-Gating Techniques for Low Power Digital Circuits." Diss., Virginia Tech, 2011. http://hdl.handle.net/10919/29627.

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As transistor sizes scale down and levels of integration increase, leakage power has become a critical problem in modern low-power microprocessors. This is especially true for ultra-low-voltage (ULV) circuits, where high levels of leakage force designers to chose relatively high threshold voltages, which limits performance. In this thesis, an industry-standard technique known as power-gating is explored, whereby transistors are used to disconnect the power from idle portions of a chip. Present power-gating implementations suffer from limitations including non-zero off-state leakage, which can aggregate to a large amount of wasted energy during long idle periods, and high energy overhead, which limits its use to long-term system-wide sleep modes. As this thesis will show however, by vastly increasing the effectiveness of power-gating through the use of emerging technologies, and by implementing aggressive hardware-oriented power-gating policies, leakage in microprocessors can be eliminated to a large extent. This allows the threshold voltage to be lowered, leading to ULV microprocessors with both low switching energy and high performance. The first emerging technology investigated is the Nanoelectromechnical-Systems (NEMS) switch, which is a CMOS-compatible mechanical relay with near-infinite off-resistance and low on-resistance. When used for power-gating, this switch completely eliminates off-state leakage, yet is compact enough to be contained on die. This has tremendous benefits for applications with long sleep times. For example, a NEMS-power-gated architecture performing an FFT per hour consumes 30 times less power than a transistor-power-gated architecture. Additionally, the low on-resistance can lower power-gating area overhead by 36-83\%. The second technology targets the high energy overhead associated with powering a circuit on and off. This thesis demonstrates that a new logic style specifically designed for ULV operation, Sense Amplifier Pass Transistor Logic (SAPTL), requires power-gates that are 8-10 times smaller, and consumes up to 15 times less boot-up energy, compared to static-CMOS. These abilities enable effective power-gating of an SAPTL circuit, even for very short idle periods. Microprocessor simulations demonstrate that a fine-grained power-gating policy, along with this drastically lower overhead, can result in up to a 44\% drop in energy. Encompassing these investigations is an energy estimation framework built around a cycle-accurate microprocessor simulator, which allows a wide range of circuit and power-gating parameters to be optimized. This framework implements two hardware-based power-gating schedulers that are completely invisible to the OS, and have extremely low hardware overhead, allowing for a large number of power-gated regions. All together, this thesis represents the most complete and forward-looking study on power-gating in the ULV region. The results demonstrate that aggressive power-gating allows designers to leverage the very low switching energy of ULV operation, while achieving performance levels that can greatly expand the capabilities of energy-constrained systems.
Ph. D.
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Tsai, Ming-Yu, and 蔡明諭. "An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/09027930047814983581.

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博士
國立中山大學
資訊工程學系研究所
98
The mainstream of current VLSI design and logic synthesis is based on traditional CMOS logic circuits. However, in the past two decades, various new logic circuit design styles based on pass-transistor logic (PTL) have been proposed. Compared with CMOS circuits, these PTL-based circuits are claimed to have better results in area, speed, and power in some particular applications, such as adder and multiplier designs. Since most current automatic logic synthesis tools (such as Synopsys Design Compiler) are based on conventional CMOS standard cell library, the corresponding logic minimization for CMOS logic cannot be directly employed to generate efficient PTL circuits. In this dissertation, we develop two novel PTL synthesizers that can efficiently generate PTL-based circuits. One is based on pure PTL cells; the other mixes CMOS and PTL cells in the standard cell library to achieve better performance in area, speed, and power. Since PTL-based circuits are constructed by only a few basic PTL cells, the layouts in PTL cells can be easily updated to design large SoC systems as the process technology migrates rapidly in current Nano technology era. The proposed PTL logic synthesis flows employ the popular Synopsys Design Compiler (DC) to perform logic translation and minimization based on the standard cell library composed of PTL and CMOS cells, thus, the PTL design flow can be easily embedded in the standard cell-based ASIC design flow. In this dissertation, we also discuss PTL-based designs of some fundamental hardware components. Furthermore, the proposed PTL cell library is used to synthesize large processor systems in applications of computer arithmetic and 3D graphics.
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WANG, JIA-LONG, and 王家龍. "Area-optimal pass transistor logic minimization." Thesis, 1989. http://ndltd.ncl.edu.tw/handle/79027637899409777660.

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Chen, Shi Zong, and 陳世宗. "Sirup: single rail up-down pass-transistor-logic." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/65632113048817408437.

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Hsu, Chih-Cheng, and 許志成. "Automatic Optimization in Pass-Transistor-Based Logic Synthesizer." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/86877104888035726165.

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碩士
國立中山大學
資訊工程學系研究所
88
In this thesis, An automatic optimization logic synthesizer in pass-transistor-based is developed for logic mapping of the combinational circuits. The format of inputs is Boolean functions with expression of sum of product and we can input several functions for hardware sharing at the same time. Depending the difference of circuits, we use the RC delay model to do optimization for both area and speed performance. The final, output is Verilog gate-level code and HSPICE netlist that provide Verilog-in for automatic place-and-route and simulation. It only needs little executing time for searching the best result and we can quickly gate it.
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VEN-CHIEH, HSIEH, and 謝文傑. "A New Logic Synthesis and Optimization Procedure Using Pass-Transistor Logic." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/96660896455884414515.

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碩士
淡江大學
電機工程學系
88
At logic design level, a proper choice of a circuit style for implementing combinational logic is very important. Many kinds of logic styles using pass-transistor circuit have been proposed with the objective to improve the performance of static CMOS logic. And the advantages present by pass-transistor logic have been proved in many cases from 2-input XOR gate to Multiplier. But when compares to classical NAND/NOR or some other simple logic gate, functions can be realized with better performance and smaller area by using static CMOS logic. The result a logic style may provide high performance only in some specific logic functions may confuse someone in logic style selecting. So a formulation of universal rules for optimal logic style, which provide high performance for arbitrary logic function, is needed. Moreover, the static CMOS logic network structure can be seems as a special case of the pass-transistor logic network that pass variables are only power lines. Thus, it is possible to develop a new logic style combine the advantages of both static CMOS logic and pass-transistor logic for arbitrary logic function and high performance applications. The objective of this work is to propose a new logic circuit synthesis and optimization procedure for arbitrary logic function implementation. Follow the synthesis and optimization procedures, a high performance new circuit which is low power consumption, low power-delay product, area efficient and high robustness against transistor downsizing and voltage scaling will produced.
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Chen, Jian-Hung, and 陳建宏. "Low Power and High Speed Logic Synthesis with Pass Transistor Logic." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/59671970997835239984.

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碩士
國立中山大學
資訊工程學系研究所
89
In this thesis, a pass-transistor logic synthesizer is developed for logic mapping of any combinational circuits based on only two types of cells: 2-to-1 multiplexors and inverters. The input contains several sum-of-product Boolean function expressions. Our synthesizer will consider the hardware sharing among these Boolean functions in order to save area. The output of our synthesizer is pass-transistor-based circuits with optimized transistor width in terms of user-specified speed and power performance measurement. During optimization, the Elmore RC delay model is used to estimate the critical path delay and the power is characterized by the switching of all the internal nodes. The final outputs are HSPICE netlists and Verilog gate-level code that allow more detailed timing simulation and automatic placement-routing.
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Books on the topic "Pass Transistor Logic (PTL)"

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Mokhlesi, Jamileh. Design automation for differential pass-transistor logic. Ottawa: National Library of Canada, 1994.

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Mittal, Manish. Application of GaAS differential pass transistor logic in high speed digital circuits. Ottawa: National Library of Canada = Bibliothèque nationale du Canada, 1992.

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Pasternak, John Henry. High-speed differential pass-transistor logic. 1991.

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Pasternak, John Henry. CMOS pass-transistor logic design for VLSI. 1987.

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Book chapters on the topic "Pass Transistor Logic (PTL)"

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Munteanu, Mihai, Peter A. Ivey, Luke Seed, Marios Psilogeorgopoulos, Neil Powell, and Istvan Bogdan. "Single Ended Pass-Transistor Logic." In VLSI: Systems on a Chip, 206–17. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/978-0-387-35498-9_19.

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Hu, Jianping, Xiaoyan Luo, and Li Su. "A New Clocked Adiabatic Logic with Complementary Pass-Transistor Logic Evaluation Trees." In 2011 International Conference in Electrics, Communication and Automatic Control Proceedings, 1729–35. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-8849-2_224.

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Manju, C. S., N. Poovizhi, and R. Rajkumar. "Power Efficient Pulse Triggered Flip-Flop Design Using Pass Transistor Logic." In Emerging Trends in Computing and Expert Technology, 48–61. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-32150-5_5.

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Ni, Haiyan, Xiaolei Sheng, and Jianping Hu. "Voltage Scaling for Adiabatic Register File Based on Complementary Pass-Transistor Adiabatic Logic." In Lecture Notes in Electrical Engineering, 39–46. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-19706-2_6.

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Hang, Guoqiang, Yang Yang, Xiaohui Hu, and Hongli Zhu. "Application of Neuron-MOS and Pass Transistor to Voltage-Mode Ternary Logic Circuit." In Electrical, Information Engineering and Mechatronics 2011, 2109–17. London: Springer London, 2012. http://dx.doi.org/10.1007/978-1-4471-2467-2_249.

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Ni, Haiyan, Lifang Ye, and Jianping Hu. "Dual-Threshold CMOS Technique for Pass-Transistor Adiabatic Logic with PMOS Pull-Up Configuration." In Lecture Notes in Electrical Engineering, 31–38. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-19706-2_5.

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Hu, Jianping, Binbin Liu, and Lv Yu. "Dual-Threshold CMOS for Complementary Pass-Transistor Adiabatic Logic with Gate-Length Biasing Techniques." In 2011 International Conference in Electrics, Communication and Automatic Control Proceedings, 1683–89. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-8849-2_218.

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Song, Minkyu. "Design of a Low Power 108-bit Conditional Sum Adder Using Energy Economized Pass-transistor Logic (EEPL)." In VLSI: Integrated Systems on Silicon, 227–38. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-0-387-35311-1_19.

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"Pass-Transistor Logic." In Bebop to the Boolean Boogie, 401–4. Elsevier, 2003. http://dx.doi.org/10.1016/b978-075067543-7/50031-4.

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"Pass-Transistor Logic." In Bebop to the Boolean Boogie, 423–26. Elsevier, 2009. http://dx.doi.org/10.1016/b978-1-85617-507-4.00034-6.

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Conference papers on the topic "Pass Transistor Logic (PTL)"

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Meher, P. K., Shen-Fu Hsiao, Chia-Sheng Wen, and Ming-Yu Tsai. "Low-Cost Design of Serial-Parallel Multipliers Over GF(2^m) Using Hybrid Pass-Transistor Logic (PTL) and CMOS Logic." In 2010 International Symposium on Electronic System Design (ISED 2010). IEEE, 2010. http://dx.doi.org/10.1109/ised.2010.33.

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Oliver, Lara D., Krishnendu Chakrabarty, and Hisham Z. Massoud. "Dual-threshold pass-transistor logic design." In the 19th ACM Great Lakes symposium. New York, New York, USA: ACM Press, 2009. http://dx.doi.org/10.1145/1531542.1531610.

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Zhou, Hai, and Adnan Aziz. "Buffer minimization in pass transistor logic." In the 2000 international symposium. New York, New York, USA: ACM Press, 2000. http://dx.doi.org/10.1145/332357.332384.

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Buch, Narayan, Newton, and Sangiovanni-Vincentelli. "Logic synthesis for large pass transistor circuits." In Proceedings of IEEE International Conference on Computer Aided Design (ICCAD). IEEE, 1997. http://dx.doi.org/10.1109/iccad.1997.643609.

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Tai-Hung Liu, M. K. Ganai, A. Aziz, and J. L. Burns. "Performance driven synthesis for pass-transistor logic." In Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013). IEEE, 1999. http://dx.doi.org/10.1109/icvd.1999.745184.

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Hang, Guoqiang, and Xuanchang Zhou. "Novel CMOS static ternary logic using double pass-transistor logic." In 2010 2nd International Conference on Information Science and Engineering (ICISE). IEEE, 2010. http://dx.doi.org/10.1109/icise.2010.5689867.

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Pasternak, John H., and C. Andre T. Salama. "Optimization of Submicron CMOS Differential Pass-Transistor Logic." In ESSCIRC '89: 15th European Solid-State Circuits Conference. IEEE, 1989. http://dx.doi.org/10.1109/esscirc.1989.5468086.

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Gao, Lixin. "High performance Complementary Pass transistor Logic full adder." In Mechanical Engineering and Information Technology (EMEIT). IEEE, 2011. http://dx.doi.org/10.1109/emeit.2011.6023114.

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Hsiao, Shen-Fu, Ming-Yu Tsai, and Chia-Sheng Wen. "Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits." In APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems. IEEE, 2006. http://dx.doi.org/10.1109/apccas.2006.342077.

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Mittal, Mudit, and Arun Pratap Singh Rathod. "Digital circuit optimization using Pass Transistor Logic architectures." In 2016 International Conference on Emerging Trends in Communication Technologies (ETCT). IEEE, 2016. http://dx.doi.org/10.1109/etct.2016.7882922.

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