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Dissertations / Theses on the topic 'Pass Transistor Logic (PTL)'

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Published: 4 June 2021

Last updated: 25 July 2025

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1

Garg, Rajesh. "Generalized buffering of pass transistor logic (PTL) stages using Boolean division and don't cares." Texas A&M University, 2003. http://hdl.handle.net/1969.1/5906.

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Pass Transistor Logic (PTL) is a well known approach for implementing digital circuits. In order to handle larger designs and also to ensure that the total number of series devices in the resulting circuit is bounded, partitioned Reduced Ordered Binary Decision Diagrams (ROBDDs) can be used to generate the PTL circuit. The output signals of each partitioned block typically needs to be buffered. In this thesis, a new methodology is presented to perform generalized buffering of the outputs of PTL blocks. By performing the Boolean division of each PTL block using different gates in a library, we

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2

Ragavan, Rengarajan. "Reconfigurable FSM for Ultra-Low Power Wireless Sensor Network Nodes." Thesis, Linköpings universitet, Elektroniska komponenter, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-100121.

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Wireless sensor networks (WSN) play an important role in today’s monitoring and controlsystems like environmental monitoring, military surveillance, industrial sensing and control, smarthome systems and tracking systems. As the application of WSN grows by leaps and bounds, there is anincreasing demand in placing a larger number of sensors and controllers to meet the requirements. Theincreased number of sensors necessitates flexibility in the functioning of nodes. Nodes in wirelesssensor networks should be capable of being dynamically reconfigured to perform various tasks is theneed of the hour

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3

Varadharajan, Swetha. "Digital and Analog Applications of Double Gate Mosfets." Ohio University / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1132759182.

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4

Henry, Michael B. "Emerging Power-Gating Techniques for Low Power Digital Circuits." Diss., Virginia Tech, 2011. http://hdl.handle.net/10919/29627.

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As transistor sizes scale down and levels of integration increase, leakage power has become a critical problem in modern low-power microprocessors. This is especially true for ultra-low-voltage (ULV) circuits, where high levels of leakage force designers to chose relatively high threshold voltages, which limits performance. In this thesis, an industry-standard technique known as power-gating is explored, whereby transistors are used to disconnect the power from idle portions of a chip. Present power-gating implementations suffer from limitations including non-zero off-state leakage, which ca

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5

Tsai, Ming-Yu, and 蔡明諭. "An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/09027930047814983581.

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博士<br>國立中山大學<br>資訊工程學系研究所<br>98<br>The mainstream of current VLSI design and logic synthesis is based on traditional CMOS logic circuits. However, in the past two decades, various new logic circuit design styles based on pass-transistor logic (PTL) have been proposed. Compared with CMOS circuits, these PTL-based circuits are claimed to have better results in area, speed, and power in some particular applications, such as adder and multiplier designs. Since most current automatic logic synthesis tools (such as Synopsys Design Compiler) are based on conventional CMOS standard cell library, the c

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6

WANG, JIA-LONG, and 王家龍. "Area-optimal pass transistor logic minimization." Thesis, 1989. http://ndltd.ncl.edu.tw/handle/79027637899409777660.

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7

Chen, Shi Zong, and 陳世宗. "Sirup: single rail up-down pass-transistor-logic." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/65632113048817408437.

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8

Hsu, Chih-Cheng, and 許志成. "Automatic Optimization in Pass-Transistor-Based Logic Synthesizer." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/86877104888035726165.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>88<br>In this thesis, An automatic optimization logic synthesizer in pass-transistor-based is developed for logic mapping of the combinational circuits. The format of inputs is Boolean functions with expression of sum of product and we can input several functions for hardware sharing at the same time. Depending the difference of circuits, we use the RC delay model to do optimization for both area and speed performance. The final, output is Verilog gate-level code and HSPICE netlist that provide Verilog-in for automatic place-and-route and simulation. It only needs

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9

VEN-CHIEH, HSIEH, and 謝文傑. "A New Logic Synthesis and Optimization Procedure Using Pass-Transistor Logic." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/96660896455884414515.

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碩士<br>淡江大學<br>電機工程學系<br>88<br>At logic design level, a proper choice of a circuit style for implementing combinational logic is very important. Many kinds of logic styles using pass-transistor circuit have been proposed with the objective to improve the performance of static CMOS logic. And the advantages present by pass-transistor logic have been proved in many cases from 2-input XOR gate to Multiplier. But when compares to classical NAND/NOR or some other simple logic gate, functions can be realized with better performance and smaller area by using static CMOS logic. The result a logic style

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10

Chen, Jian-Hung, and 陳建宏. "Low Power and High Speed Logic Synthesis with Pass Transistor Logic." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/59671970997835239984.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>89<br>In this thesis, a pass-transistor logic synthesizer is developed for logic mapping of any combinational circuits based on only two types of cells: 2-to-1 multiplexors and inverters. The input contains several sum-of-product Boolean function expressions. Our synthesizer will consider the hardware sharing among these Boolean functions in order to save area. The output of our synthesizer is pass-transistor-based circuits with optimized transistor width in terms of user-specified speed and power performance measurement. During optimization, the Elmore RC delay mo

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11

Teng-Yuan, Lin, and 林鼎源. "Analysis and Applications of Pass-Transistor/ CMOS Collaborated Logic." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/09404824821994602851.

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碩士<br>大同工學院<br>電機工程研究所<br>86<br>This thesis focuses on the analysis and application of PCCL. The PCCL is especially used in low-power VLSI and a universal gate. We try to implement a set of logic functions and discuss the waveforms attenuated by pass-transistors. We discuss the technique improved by inverter-restoring and the waveform can be restored to at 500 MHz operation frequency. We try to replace the level-restoring circuit of PCCL by inverter-latch one. Finally, we don't implement by BDD, but implement by AND and OR gates of convWe simulate the critical-path waveform by HSPICE. The pr

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12

Cho, Hamm-Min, and 卓瀚民. "Mixing Pass-Transistor Logic with CMOS Logic for Low-Power Cell- Based Designs." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/83489899657484360995.

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碩士<br>國立中正大學<br>電機工程學系<br>86<br>Owing to the demand of the portable products small area and low- power are the main considerations in cell-based IC design. In this thesis we try to propose a methodology to combine pass- transistor logic and complementary CMOS logic to reduce power consumption. We first identify the types of logic functions suited for each individual logic style. Then we replace certain complementary CMOS cells in the cell library with pass- transistor cells. The modified ce

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13

Li, Yu-Cheng, and 李育晟. "Low Power Divider Design Using Pass Transistor Logic Circuit Scheme." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/24911630754490373033.

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碩士<br>朝陽科技大學<br>資訊與通訊系<br>104<br>An increasing demand of communication mobile, the demand for larger data transmission and operation speed has grown significantly over time. It forces the system to process at a faster operation speed, and function more efficiently. However, it could translate into issues that involve higher power consumption and over-heating. As a result, suppressing and controlling the operation power at a higher operation frequency has become a crucial subject of study. Universal communication system involves high-speed dividers and it is primarily scheme in TSPC (True-Singl

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14

Chien, Hung-Chun, and 簡鴻駿. "A Full Adder Realized by Bootstrapped Pass Transistor Logic Structure." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/33594552186358259766.

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碩士<br>南台科技大學<br>電子工程系<br>95<br>We use ALU broadly in VLSI such as Digital Signal Processor (DSP), Image Processor, and Microprocessor. Adder, subtractor, and multiplicer, which are included full adder, are the most common operation units in ALU. We can use software to do most calculation but not use hardware. The most basic circuit doing calculation in the computer is binary adder. For example, we can use of addition to do subtracting, continuous adding to do multiplication, and continuous subtracting to do division. Thus, adder is very important in the ALU and also can influence the performan

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15

Tsai, Cheng-Hsuan, and 蔡政軒. "Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/55551706681576129798.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>98<br>The mainstream of current VLSI design and logic synthesis is based on traditional CMOS logic circuits. However, various new logic circuit design styles based on pass-transistor logic (PTL) have been proposed. The advantage of PTL is higher speed, smaller area and lower power for some particular circuits such as XOR. Since most current automatic logic synthesis tools (such as Synopsys Design Compiler) are based on conventional CMOS standard cell library, the corresponding logic minimization for CMOS logic cannot be directly employed to generate efficient PTL c

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16

Yang, Yuling. "Design of high performance multiple-input pass-transistor-logic XOR circuits." Thesis, 2003. http://spectrum.library.concordia.ca/2129/1/MQ77726.pdf.

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XOR gates are basic building blocks in the design of almost all kinds of digital circuits for signal processing, generation and control. The performance of the XOR gates can be a factor determining the performance of the complete circuits. In particular, XOR gates with a large number of inputs, which are often used for parallel processing, may make a major contribution to the delay of the circuits. Some reduction of the delay can be achieved but usually at the expense of the power dissipation. In this thesis, a comprehensive study of the XOR gate design is presented. Based on the study, an ap

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17

Chen, Dai-Yen, and 陳達彥. "Logic/Circuit Synthesizer Based on Low-Complexity Pass-Transistor Cell Library." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/15156757388339666671.

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碩士<br>國立中山大學<br>資訊工程研究所<br>87<br>In this thesis, A pass-transistor-based cell library containing four types of cells is designed and the corresponding logic/circuit synthesizer is developed for logic mapping of any combinational and dynamic circuits. There are four driven capability selects for each type of cells. The format of input is Boolean functions with expressions of sum of product and we can input several functions for hardware sharing at the same time. It provides several optional modes such as high density、high performance、dynamic logic circuit, etc. . It also does optimization for b

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18

Liu, Yi-Yu, and 劉一宇. "Low Power Driven Pass Transistor Logic Synthesis by Binary Decision Diagrams." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/11833238090918998559.

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碩士<br>國立清華大學<br>資訊工程學系<br>88<br>In this paper, we present methods to synthesize low power Pass Transistor Logic (PTL) cell. Given that the power consumption of a PTL cell includes power consumed at the gate terminal and source/drain capacitance when current flows from power/ground to output, we will translate finding a low power PTL cell to finding an OBDD with some defined cost function. This cost function includes the minimization of occurrence of variables with high transition probability and the minimization of the expected path length of an OBDD. To compute the cost function efficiently,

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19

Wen, Chia-Sheng, and 溫家聖. "Logic Synthesis of High-Performance Combinational Circuits Based on Pass-Transistor Cell Library." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/69965336703238055475.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>91<br>This thesis proposes a new variable-order prediction method to predict the Shannon expansion order during the BDD tree generator. Combining this method with the original minimum width method, we can generator a better BDD tree to be used in our pass-transistor logic synthesizer. Also we propose two partitioning methods to reduce the length of the critical paths. The first method can effectively reduce the critical path delay at the cost of much higher area cost. The second method explores the common factors in the Boolean functions to reduce the critical path

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20

Lu, Chih-hung, and 呂志宏. "A New Current-Sensing Complementary Pass-Transistor Logic for Low-Voltage Low-Power Applications." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/87368718272694349914.

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碩士<br>國立交通大學<br>電子研究所<br>83<br>In this thesis,we had developed a new circuit, it is called Current-Sensing Complementary Pass-Transistor Logic(CSCPTL). By applying the advantages of pass-transistor and the fast sensing characteristic in low voltage swing, the proposed new circuit has advantages on low-volateg low-power operation. As the portable personal computer and consu,er electronic system needs is getting critical, the new circuit has a fast operation speed under 1.2V supply voltage wi

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21

Liao, Yi-Yi, and 廖以義. "The Design of Low-Power Current-Sensing Complementary Pass- Transistor Logic and It's Application for Low-Voltage High-Speed Multiplier." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/03087688244714051905.

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22

Liow, Yu-Yee, and 廖以義. "The Design of Low-Power Current-Sensing Complementary Pass- Transistor Logic and It's Application for Low-Voltage High-Speed Multiplier." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/49651992329882673659.

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碩士<br>淡江大學<br>電機工程學系<br>84<br>Recently, power dissipation is becoming an important constraint in portable e-lectronic systems. In this thesis, a new low-power current-sensing complement-ary pass-transistor logic (LCSCPTL) is proposed and analyzed. Since the curre-nt-sensing scheme can yield a faster sensing speed under small voltage swingthan the voltage-sensing scheme, the new logic circuit can be used in the low-voltage low-power digital system for high speed applications. It is shown t

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