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Journal articles on the topic 'Pass Transistor Logic (PTL)'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 July 2025

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1

Arunabala, Dr C. "Design of a 4 bit Arithmetic and Logical unit with Low Power and High Speed." International Journal of Innovative Technology and Exploring Engineering 10, no. 5 (2021): 87–92. http://dx.doi.org/10.35940/ijitee.e8660.0310521.

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In this presented work we designed the 4- bit Arithmetic & Logical Unit (ALU) by using the different modules. The Various modules are AND gate & OR gate designed with six transistors, While the XOR modules is designed with both eight transistors & six transistors. The six transistor XOR module gives optimized results. Another one is the four by one multiplexer designed with eight transistors implemented using Pass transistor logic (PTL) style. The full adder module is designed by using 18 transistors implemented through PTL style. Here because of PTL style the number of transistor

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2

Dr.C.Arunabala*, Ch.Jyothirmayi, N. S. V. Sreeja.T D, Burra Hrithika Suma, Udumula Reddy, and I.R.AnushaDevi. "Design of a 4 bit Arithmetic and Logical unit with Low Power and High Speed." International Journal of Innovative Technology and Exploring Engineering (IJITEE) 10, no. 5 (2021): 87–92. https://doi.org/10.35940/ijitee.E8660.0310521.

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In this presented work we designed the 4- bit Arithmetic & Logical Unit (ALU) by using the different modules. The Various modules are AND gate & OR gate designed with six transistors, While the XOR modules is designed with both eight transistors & six transistors. The six transistor XOR module gives optimized results. Another one is the four by one multiplexer designed with eight transistors implemented using Pass transistor logic (PTL) style. The full adder module is designed by using 18 transistors implemented through PTL style. Here because of PTL style the number of transistor

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3

Cho, Geun Rae, and Tom Chen. "On Mixed PTL/Static Logic for Low-power and High-speed Circuits." VLSI Design 12, no. 3 (2001): 399–406. http://dx.doi.org/10.1155/2001/59548.

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We present more evidence in a 0.25 μm CMOS technology that the pass-transistor logic (PTL) structure that mixes conventional PTL structure with static logic gates can achieve better performance and lower power consumption compared to conventional PTL structure. The goal is to use the static gates to perform both logic functions as well as buffering. Our experimental results demonstrate that the proposed mixed PTL structure beats pure static structure and conventional PTL in 9 out of 15 test cases for either delay or power consumption or both in a 0.25 μm CMOS process. The average delay, power

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4

Ganesh, Racha, K. Lal Kishore, and P. Srinivasa Rao. "Performance Analysis of Hybrid Comparator using 45nm Technology." CVR Journal of Science and Technology 25, no. 1 (2024): 15–23. http://dx.doi.org/10.32377/cvrjst2503.

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In the present real-time world, due to the improvements and innovations of System on Chip (SoC) applications, there is a requirement to integrate multiple technology design topologies. The electronic system design is classified as analog, digital, and mixed-signal design. The comparator is the major building block used in the datapath of System on Chip (SoC) application device. The usage of these devices depends on not only functionality but also on the non-functionality parameters considering different performance estimation metrics. The nonfunctional performance metrics for a transistor leve

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Lamani, Deepa Suranam, and Dr H. V. Ravish Aradhya. "Design of Low Power 64-Bit Hybrid Full Adder." International Journal for Research in Applied Science and Engineering Technology 11, no. 8 (2023): 2200–2205. http://dx.doi.org/10.22214/ijraset.2023.55554.

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Abstract: In the realm of Computer Science, integrated circuits (ICs) have propelled microprocessor and digital signal processor development, hinging on the 1-bit full adder's significance for mathematical tasks. To amplify overall efficiency, enhancing this adder is pivotal. As demand surges for power-efficient devices like smartphones and MP3 players, maintaining a balance between speed, size, and power usage becomes imperative. Engineers tackle this challenge while bridging battery technology gaps. We propose advanced 1-bit full adder designs, evaluated via Cadence Virtuoso. A hybrid versio

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Rajasekhar, K., B. Sandhya, G. Srinivas, and N. Manogna. "Performance of Different Full Adder Structures for Optimized Design." International Journal of Advance Research and Innovation 8, no. 2 (2020): 74–80. http://dx.doi.org/10.51976/ijari.822013.

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Design of high performance and energy efficient digital systems are one of the most important research areas in VLSI system design which is suitable for real-time applications. One of the functional elements used in complex arithmetic circuits is an adder. To design an energy efficient adder one-bit full adder cell is designed based on adiabatic logic. The proposed ALFA cell is designed using adiabatic logic which results with the negligible amount of exchange of energy with the surrounding environment. Therefore, the application circuits based on this logic will have negligible energy loss du

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7

Jiang, Jin Tao, Li Fang Ye, and Jian Ping Hu. "Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration." Applied Mechanics and Materials 39 (November 2010): 73–78. http://dx.doi.org/10.4028/www.scientific.net/amm.39.73.

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Leakage power reduction is extremely important in the design of nano-circuits. Gate leakage has become a significant component in currently used nanometer CMOS processes with gate oxide structure. The structure and operation of the PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits that consist mostly of PMOS transistors are complementary to PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) ones that consist mostly of NMOS transistors. This paper investigates gate leakage reduction of the PAL-2P circuits in nanometer CMOS processes with g

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8

Siddaiah, Premananda Belegehalli, Sahithi Narsepalli, Sanya Mittal, and Abdur Rehman. "Area and power efficient divide-by-32/33 dual-modulus pre-scaler using split-path TSPC with AVLS for frequency divider." Journal of Electrical Engineering 74, no. 5 (2023): 403–12. http://dx.doi.org/10.2478/jee-2023-0048.

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Abstract Pre-scalers are electronic circuits used in phase-locked loops to multiply frequencies. This is achieved by dividing the high-frequency signals generated from a voltage-controlled oscillator. The high-frequency operation of pre-scaler circuits leads to significantly higher power consumption. To address this, D flip-flops (D-FF) realized using true-single phase clocking (TSPC) logic. The work suggests incorporating the Adaptive Voltage Level Source (AVLS) circuit with the Dual Modulus Pre-Scaler (DMPS) circuit to reduce power consumption. In addition to the incorporation of the AVLS ci

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9

Lin, Jin-Fa, Zheng-Jie Hong, Chang-Ming Tsai, Bo-Cheng Wu, and Shao-Wei Yu. "Novel Low-Complexity and Low-Power Flip-Flop Design." Electronics 9, no. 5 (2020): 783. http://dx.doi.org/10.3390/electronics9050783.

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In this paper, a compact and low-power true single-phase flip-flop (FF) design with fully static operations is presented. The design is developed by using various circuit-reduction schemes and features a hybrid logic style employing both pass transistor logic (PTL) and static complementary metal-oxide semiconductor (CMOS) logic to reduce circuit complexity. These circuit optimization measures pay off in various aspects, including smaller clock-to-Q (CQ) delay, lower average power, lower leakage power, and smaller layout area; and the transistor-count is only 17. Fabricated in TSMC 180 nm CMOS

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Mathiazhagan, V., N. P. Ananthamoorthy, and C. Venkatesh. "Design and Implementation of Enhanced Edge Triggered Flip-Flop for Low Power Dissipation." Journal of Nanoelectronics and Optoelectronics 17, no. 9 (2022): 1261–73. http://dx.doi.org/10.1166/jno.2022.3291.

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Power consumption in integrated circuits is one of the prominent aspects of the design methodologies that affect cost and efficiency. It holds a prominent role in the design and fabrication of Integrated Circuits (ICs). Power consumption in ICs increases largely due to clock diffusion techniques and Flip-Flops (FFs) since they consume a huge amount of power to carry out internal transitions. Various researchers have proposed different flip-flop circuit designs for reducing power consumption in clocking systems. When integrated circuits are operating at high frequency, the clock functions are u

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Ying, Yong Jie, and Zaharah Johari. "Simulation and Characterization of Carbon Nanotube-based 2:1 Multiplexer Electrical Properties." Journal of Physics: Conference Series 2622, no. 1 (2023): 012023. http://dx.doi.org/10.1088/1742-6596/2622/1/012023.

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Abstract This paper reports on using simulation to characterize a Carbon Nanotube (CNT) based 2:1 multiplexer (MUX). This study aimed to evaluate the electrical properties, particularly the propagation delay, average power consumption, Power-Delay Product (PDP), and Energy-Delay Product (EDP). Different design approaches namely conventional CMOS, Pass Transistor Logic (PTL) approach, and Gate Diffusion Input (GDI) were adopted. The voltage supply (VDD) and diameter of the CNT are varied to see the effect on the electrical properties. The simulation was carried out using HSPICE. Through simulat

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12

Li, Yucen. "A 6-bit absolute value detector based on MOSFET and PTL structure." Applied and Computational Engineering 39, no. 1 (2024): 209–17. http://dx.doi.org/10.54254/2755-2721/39/20230602.

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As science and technology develop fast, people nowadays can have an easy approach to various advanced products. The use of Internet of Things has become a reality. To ensure its reliable implementation in daily life, stable and efficient hardware equipment like sensor is essential, where absolute value detector is widely used. A detector is created on the basis of this. The circuit can compare a signed 6-bit number with the threshold of a 5-bit number. This design uses MOS and pass-transistor logic (PLT) structure as the basic parts to form the transcoding logic and the subtraction logic. This

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Zhang, Wei Qiang, Li Su, Jun Wang, Bin Bin Liu, and Jian Ping Hu. "Design and Manufacture of Energy-Recycling Pads for Low-Power Chips." Key Engineering Materials 460-461 (January 2011): 467–72. http://dx.doi.org/10.4028/www.scientific.net/kem.460-461.467.

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Energy-recycling output pad cells for driving adiabatic chips are designed, which have been fabricated with Chartered 0.35um process and tested. The proposed energy-recycling output pad cells include mainly bonding pads, electrostatic discharge (ESD) protection circuits, and two stage energy-recycling buffers that are used to drive the large load capacitances on chip pads. The two stage energy-recycling buffers are realized using CPAL (Complementary Pass-transistor Adiabatic Logic) and PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration), respectively. For comparison, a c

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Ng, K. W., and K. T. Lau. "Improved PAL-2N logic with complementary pass-transistor logic evaluation tree." Microelectronics Journal 31, no. 1 (2000): 55–59. http://dx.doi.org/10.1016/s0026-2692(99)00089-0.

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15

Yu, Yihe, Wanyuan Pan, Chengcheng Tang, Ningyuan Yin, and Zhiyi Yu. "Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model." Electronics 13, no. 7 (2024): 1284. http://dx.doi.org/10.3390/electronics13071284.

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The multiplier is the fundamental component of many computing modules. As the most important component of a multiplier, the full adder (FA) also has a significant impact on the overall performance. Full adders based on pass transistor logic (PTL) have been a very popular research field in recent years, but the uneven delay makes it difficult to analyze the critical path of multipliers based on PTL full adders. In this paper, we propose a model to evaluate the critical path of the carry save array (CSA) multiplier that could reduce the size of the simulation input set from 4 G to 93 K to finall

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16

Md, Khairul Islam, and Nath Biswas Satyendra. "Comparative Study of a Low-Power High-Speed Arithmetic Logic Unit Design Techniques." Journal of VLSI Design and its Advancement 7, no. 2 (2024): 19–30. https://doi.org/10.5281/zenodo.11260037.

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<em>The Arithmetic Logic Unit is the most important unit of a microprocessor. It performs complex operations for the processing unit and is considered as the fundamental building block of a CPU. Because of its importance in the VLSI industry, it is always a major challenge to make it high-speed, low-power consuming, robust, and compact. In this paper five different techniques, CMOS, GDI, MGDI, TGL, and PTL are used to design a 1-bit ALU with 8 different logical and arithmetic operations. The results are compared with respect to three different parameters, Transistor count, Power dissipation, a

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17

Rohit, Kumar *. Sachin Tyagi. "DESIGN OF LOW-POWER FULL ADDER IN 0.18 µm CMOS TECHNOLOGY." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 5, no. 8 (2016): 446–56. https://doi.org/10.5281/zenodo.59758.

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With the increase in device integration level and the growth in complexity of Integrated circuits, small delay and low power dissipation become important parameters as these increases performance and portability. Battery storage is limited, to extend battery life; low power operation is the primary requirement in integrated circuits. Furthermore, high speed and multiple parallel applications need high computing power, placing greater demands on energy storage elements within the system. Large power dissipation in high performance digital systems requires large size heat sinks. These off chip c

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18

Manchala, Venkat Subba Rao, Satyajeet Sahoo, and G. Ramana Murthy. "Design of Hybrid Full Adder using 6T-XOR-Cell for High Speed Processor Designs Applications." International Journal on Recent and Innovation Trends in Computing and Communication 10, no. 1s (2022): 329–36. http://dx.doi.org/10.17762/ijritcc.v10i1s.5900.

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Hybrid-logic implementation is highly suitable in the design of a full adder circuit to attain high-speed low-power consumption, which helps to design n any high speed ALUs that can be used in varies processors and applicable for high speed IoT- Application. XOR/XNOR-cell, Hybrid Full Adder (HFA) are the fundamental building block to perform any arithmetic operation. In this paper, different types of high-speed, low-power 6T-XOR/XNOR-cell designs are being proposed and simulated results are presented. The proposed HFA is simulated using a cadence virtuoso environment in a 45nm technology with

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19

Parameshwara, M. C., and H. C. Srinivasaiah. "Low-Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic Applications." Journal of Circuits, Systems and Computers 26, no. 01 (2016): 1750014. http://dx.doi.org/10.1142/s0218126617500141.

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A novel “16 transistor” (16T) 1-bit Full adder (FA) circuit based on CMOS transmission-gate (TG) and pass transistor logics (PTL) is presented. This 1-bit FA circuit with TG and PTL structure is derived based on carry dependent sum implementation approach. The design metrics (DMs) such as power, delay, power-delay-product (PDP), and transistor-count (TC) for this 1-bit FA are compared against eight other standard and state-of-the-art 1-bit FA circuits reported till date. All the comparisons are done at post layout level with respect to the DMs under consideration. The proposed 1-bit FA dissipa

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20

SoniyaNuthalapati, Ranjitha P.V.Sai, Radhika Rani Kalapala, Lourdu Sasi Rekha Lingisetty, Mekala Sirisha, and Mohammad FirdosiaParveen. "Design a Low Power and High Speed 130nm Fulladder using Exclusive-OR and Exclusive-NOR Gates." International Journal of Innovative Technology and Exploring Engineering (IJITEE) 10, no. 5 (2021): 81–86. https://doi.org/10.35940/ijitee.E8659.0310521.

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This literature illustrates the high speed and low power Full Adder (FADD) designs. This study relates to the composited structure of FADD design composed in one unit. In this the EXCL-OR/EXCL-NOR designs are used to design the FADD. Mostly concentrates on high speed standard FADD structure by combining the EXCL-OR/EXCL-NOR design in single unit. We implemented two composite structures of FADD through the full swing EXCL-OR/EXCL-NOR designs. And the EXCL-OR/EXCL-NOR design is done through pass transistor logic (PTL) and the same design projected on the composited FADD design. Such that the del

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21

Nuthalapati, Soniya, Ranjitha P.V.Sai, Radhika Rani Kalapala, Lourdu Sasi Rekha Lingisetty, Sirisha Mekala, and Parveen Mohammad Firdosia. "Design a Low Power and High Speed 130nm Fulladder using Exclusive-OR and Exclusive NOR Gates." International Journal of Innovative Technology and Exploring Engineering 10, no. 5 (2021): 81–86. http://dx.doi.org/10.35940/ijitee.e8659.0310521.

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This literature illustrates the high speed and low power Full Adder (FADD) designs. This study relates to the composited structure of FADD design composed in one unit. In this the EXCL-OR/EXCL-NOR designs are used to design the FADD. Mostly concentrates on high speed standard FADD structure by combining the EXCL-OR/EXCL-NOR design in single unit. We implemented two composite structures of FADD through the full swing EXCL-OR/EXCL-NOR designs. And the EXCL-OR/EXCL-NOR design is done through pass transistor logic (PTL) and the same design projected on the composited FADD design. Such that the del

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22

NG, K. W., and K. T. LAU. "A NOVEL ADIABATIC REGISTER FILE DESIGN." Journal of Circuits, Systems and Computers 10, no. 01n02 (2000): 67–76. http://dx.doi.org/10.1142/s0218126600000032.

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A novel 8-word × 16-bit adiabatic register file is designed. The adiabatic circuits are based on the Pass-transistor Adiabatic Logic with NMOS pull-down configuration (PAL-2N). Using adiabatic switching technique, the power consumption of the register file is significantly reduced as the energy transferred to the large capacitance buses is mostly recovered. HSPICE simulation results have shown power savings of more than 77% as compared to the conventional CMOS implementation. Although the proposed register file is designed with only one read port and one write port, multiple read and/or write

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23

Ben-Asher, Yosi, Esti Stein, and Vladislav Tartakovsky. "FPGA Realization of the Reconfigurable Mesh Counting Algorithm." Journal of Circuits, Systems and Computers 30, no. 09 (2021): 2150157. http://dx.doi.org/10.1142/s0218126621501577.

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Pass transistor logic (PTL) is a circuit design technique wherein transistors are used as switches. The reconfigurable mesh (RM) is a model that exploits the power of PTLs signal switching, by enabling flexible bus connections in a grid of processing elements containing switches. RM algorithms have theoretical results proving that [Formula: see text] can speed up computations significantly. However, the RM assumes that the latency of broadcasting a signal through [Formula: see text] switches (bus length) is 1. This is an unrealistic assumption preventing physical realizations of the RM. We pro

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24

Li, Hao. "Analysis Of 4-Bit Absolute Value Detector for ECG Signal Comparation." Highlights in Science, Engineering and Technology 71 (November 28, 2023): 227–34. http://dx.doi.org/10.54097/hset.v71i.12699.

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In the present era, where numerous heart conditions are prevalent, the significance of monitoring cardiac electrical signals has surged within the medical realm. Within this study, we leverage Complementary Metal Oxide Semiconductor (CMOS) and Pass-transistor Logic (PTL) methodologies for crafting and refining a 4-bit absolute value detection mechanism. This mechanism serves to identify and juxtapose electrocardiogram (ECG) signals. The 4-bit absolute value detection system is bifurcated into two core segments: one for absolute value identification and the other for comparative analysis. This

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25

Bhattacharjee, Pritam, and Alak Majumder. "A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application." Journal of Circuits, Systems and Computers 28, no. 07 (2019): 1950108. http://dx.doi.org/10.1142/s0218126619501081.

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Advancement in technology towards mobile computing and communication demands longer battery life, which mandates the low power design methodologies. In this paper, we have presented a novel low-power 8T flip-flop (FF) architecture, which has outsmarted the existing well-known dynamic, semi-dynamic and explicit pulsed flip-flops in terms of power and delay. The major ingredient of this architecture is a voltage keeper, which is incorporated to achieve reliable logic switching at the propagating nodes of the design. However, we have also come up with two new approaches of gated clock generation

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26

Dokic, B. L. "A Review on Energy Efficient CMOS Digital Logic." Engineering, Technology & Applied Science Research 3, no. 6 (2013): 552–61. http://dx.doi.org/10.48084/etasr.389.

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Autonomy of power supply used in portable devices directly depends on energy efficiency of digital logic. This means that digital systems, beside high processing power and very complex functionality, must also have very low power consumption. Power consumption depends on many factors: system architecture, technology, basic cells topology-speed, and accuracy of assigned tasks. In this paper, a review and comparison of CMOS topologies techniques and operating modes is given, as CMOS technology is expected to be the optimum choice in the near future. It is shown that there is a full analogy in th

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27

Srivastava, Pawan, and Dr Ram Chandra Singh Chauhan. "Design of Power Efficient Phase Frequency Detector and Voltage Controlled Oscillator for PLL Applications in 45 nm CMOS Technology." Journal of University of Shanghai for Science and Technology 23, no. 11 (2021): 184–97. http://dx.doi.org/10.51201/jusst/21/10879.

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A novel phase frequency detector is designed which is made up of 16 transistors whereas conventional is of 48 transistors. This paper also presented the design of charge pump circuit and current starved VCO (CSVCO). These are the critical blocks that are widely used for applications like clock and data recovery circuit, PLL, frequency synthesizer. The proposed PFD eliminates the reset circuit using pass transistor logic and operates effectively at higher frequencies. The circuits are designed using Cadence Virtuoso v6.1 in 45nm CMOS technology having supply voltage 1V. It was found that the po

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28

Wu, Yang Bo, Jian Ping Hu, and Hong Li. "Leakage Power Estimation of Adiabatic Circuits Using SPICE in Nanometer CMOS Processes." Advanced Materials Research 108-111 (May 2010): 625–30. http://dx.doi.org/10.4028/www.scientific.net/amr.108-111.625.

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In deep sub-micro CMOS process, the leakage power is becoming a significant proportion in power dissipation. Hence, estimating the leakage power of CMOS circuits is very important in low-power design. In this paper, an estimation technology for the total leakage power of adiabatic logic circuits by using SPICE is proposed. The basic principle of power estimation for traditional CMOS circuits using SPICE is introduced. According to the energy dissipation characteristic of adiabatic circuits, the estimation technology for leakage power is discussed. Taken as an example, the estimation for total

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29

Hu, Jian Ping, Xiao Ying Yu, and Bin Bin Liu. "Manufacturing and Testing of Adiabatic Array Multiplier for Micro Power Digital Systems." Key Engineering Materials 460-461 (January 2011): 473–78. http://dx.doi.org/10.4028/www.scientific.net/kem.460-461.473.

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Power-efficient multipliers are essential for micro systems, where low-power signal processing hardware is demanded. This paper presents an adiabatic array multiplier based on PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) circuits. It is composed of a multiplier array containing partial product generators and 1-bit (half and full) adders, and a final carry-lookahead adder. For comparison, a conventional array multiplier is also implemented. Full-custom layouts are drawn, and HSPICE simulations are carried out using the net-list extracted from their layout. The adia

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AL-ASSADI, WALEED, ANURA P. JAYASUMANA, and YASHWANT K. MALAIYA. "Pass-transistor logic design." International Journal of Electronics 70, no. 4 (1991): 739–49. http://dx.doi.org/10.1080/00207219108921324.

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Pasternak, J. H., and C. A. T. Salama. "Differential pass-transistor logic." IEEE Circuits and Devices Magazine 9, no. 4 (1993): 23–28. http://dx.doi.org/10.1109/101.250230.

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32

Hsiao, Shen-Fu, Jia-Siang Yeh, and Da-Yen Chen. "High-performance Multiplexer-based Logic Synthesis Using Pass-transistor Logic." VLSI Design 15, no. 1 (2002): 417–26. http://dx.doi.org/10.1080/1065514021000054736.

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An automatic logic/circuit synthesizer is developed which takes several Boolean functions as input and generates netlist output with basic composing cells from the pass-transistor cell library containing only two types of cells: 2-to-1 multiplexers and inverters. The synthesis procedure first constructs efficient binary decision diagrams (BDDs) for these Boolean functions considering both multi-function sharing and minimum width. Each node in the BDD trees is realized by using a 2-to-1 multiplexer (MUX) of proper driving capability designed pass-transistor logic. The inverters are then inserte

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33

Zhou, H., and A. Aziz. "Buffer minimization in pass transistor logic." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20, no. 5 (2001): 693–97. http://dx.doi.org/10.1109/43.920711.

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Pasternak, J. H., A. S. Shubat, and C. A. T. Salama. "CMOS differential pass-transistor logic design." IEEE Journal of Solid-State Circuits 22, no. 2 (1987): 216–22. http://dx.doi.org/10.1109/jssc.1987.1052705.

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Pasternak, J. H., and C. A. T. Salama. "GaAs MESFET differential pass-transistor logic." Electronics Letters 26, no. 19 (1990): 1597. http://dx.doi.org/10.1049/el:19901023.

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Yano, K., Y. Sasaki, K. Rikino, and K. Seki. "Top-down pass-transistor logic design." IEEE Journal of Solid-State Circuits 31, no. 6 (1996): 792–803. http://dx.doi.org/10.1109/4.509865.

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Pasternak, J. H., and C. A. T. Salama. "GaAs MESFET differential pass-transistor logic." IEEE Journal of Solid-State Circuits 26, no. 9 (1991): 1309–16. http://dx.doi.org/10.1109/4.84949.

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Zimmermann, R., and W. Fichtner. "Low-power logic styles: CMOS versus pass-transistor logic." IEEE Journal of Solid-State Circuits 32, no. 7 (1997): 1079–90. http://dx.doi.org/10.1109/4.597298.

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Hu, Xuan, Amy S. Abraham, Jean Anne C. Incorvia, and Joseph S. Friedman. "Hybrid Pass Transistor Logic With Ambipolar Transistors." IEEE Transactions on Circuits and Systems I: Regular Papers 68, no. 1 (2021): 301–10. http://dx.doi.org/10.1109/tcsi.2020.3034042.

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Oklobdzija, V. G., and B. Duchene. "Synthesis of high-speed pass-transistor logic." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 44, no. 11 (1997): 974–76. http://dx.doi.org/10.1109/82.644054.

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Zhuang, N., M. V. Scotti, and P. Y. K. Cheung. "PTM: Technology mapper for pass-transistor logic." IEE Proceedings - Computers and Digital Techniques 146, no. 1 (1999): 13. http://dx.doi.org/10.1049/ip-cdt:19990244.

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Shubat, A. S., J. A. Pretorius, and C. A. T. Salama. "Differential pass transistor logic in CMOS technology." Electronics Letters 22, no. 6 (1986): 294. http://dx.doi.org/10.1049/el:19860200.

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SHAMANNA, M., K. CAMERON, and S. R. WHITAKER. "Multiple-input, multiple-output pass transistor logic." International Journal of Electronics 79, no. 1 (1995): 33–45. http://dx.doi.org/10.1080/00207219508926248.

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Jung, Seong-Ook, and Sung-Mo Kang. "Modular charge recycling pass transistor logic (MCRPL)." Electronics Letters 36, no. 5 (2000): 404. http://dx.doi.org/10.1049/el:20000386.

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Datta, Rajesh Kumar. "A Pass Transistor based Multifunction Gate Design." Indian Journal of VLSI Design 3, no. 2 (2023): 5–8. http://dx.doi.org/10.54105/ijvlsid.b1222.093223.

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This study introduces a gate design that uses pass transistor switches and enables the implementation of all necessary logic gates with a single structure. This gate design can be used for efficient circuit resizing and creating secure obfuscated circuits. This work also presents simulation results that demonstrate the effectiveness of the gate in performing various logic gate operations.

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Rajesh, Kumar Datta. "A Pass Transistor based Multifunction Gate Design." Indian Journal of VLSI Design (IJVLSID) 3, no. 2 (2023): 5–8. https://doi.org/10.54105/ijvlsid.B1222.093223.

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This study introduces a gate design that uses pass transistor switches and enables the implementation of all necessary logic gates with a single structure. This gate design can be used for efficient circuit resizing and creating secure obfuscated circuits. This work also presents simulation results that demonstrate the effectiveness of the gate in performing various logic gate operations.

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47

Yaminikumari, Jampani, and Gudla Bhanu Gupta. "Implementation of 1-bit Full Adder Circuit Using Pass Transistor Logic." International Journal for Research in Applied Science and Engineering Technology 10, no. 7 (2022): 4974–82. http://dx.doi.org/10.22214/ijraset.2022.46097.

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Abstract: In this work, we have implemented 1-bit Full Adder Circuit using Pass Transistor Logic. Pass Transistor Logic is used for high-speed technology and is easy to build the basic gate structures. The developed circuit is an extension of pass transistor logic Ex-or gate. The 1-bit Full Adder Circuit has been performed and obtained I-V characteristics and power for sum and carry were calculated. The effect of scaling on the overall performance is also analysed through the performance evaluation of 1-bit full adder circuit. Simulation results have been performed on LT Spice tool simulator a

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Chaitanya, S.* Abhishek B. S. Harshavardhan S. Karthik S. Manju T. M. "Design and Analysis of Adders Using Pass Transistor Logic for Multipliers." International Journal of Scientific Research and Technology 2, no. 5 (2025): 326–37. https://doi.org/10.5281/zenodo.15421140.

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This paper demonstrates the design and optimization of a Multiplier using pass transistor logic with half and full adders in 90 nm and 45 nm CMOS technology. The design methodology utilizes fewer transistors and low-power pass transistor logic to improve system efficiency. Implementation and simulation proved these designs to be superior than traditional CMOS designs in terms of area, delay, power dissipation, and energy efficiency. Optimized adders in the multiplier framework thus provide compact, power efficient multiplier design. A comparison to conventional designs shows significant reduct

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CHANG, ROBERT C., PO-CHUNG HUNG, and HSIN-LEI LIN. "LOW POWER ENERGY RECOVERY COMPLEMENTARY PASS-TRANSISTOR LOGIC." Journal of Circuits, Systems and Computers 15, no. 04 (2006): 491–504. http://dx.doi.org/10.1142/s0218126606003271.

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A proposed adiabatic logic called Energy Recovery Complementary Pass-transistor Logic (ERCPL) is presented in this paper. It operates with a two-phase nonoverlapping power-clock supply. It uses bootstrapping to achieve efficient power saving and eliminates any nonadiabatic losses on the charge-steering devices. A scheme is used to recover part of the energy trapped in the bootstrapping nodes. We compare the energy dissipation between ERCPL and other logic circuits by simulation. Simulation results show that a pipelined ERCPL carry look-ahead adder can achieve a power reduction of 80% over the

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Swathi, Panchadi, and Gudla Bhanu Gupta. "Implementation of 2-bit Multiplier Circuit Using Pass Transistor Logic." International Journal for Research in Applied Science and Engineering Technology 10, no. 7 (2022): 5013–22. http://dx.doi.org/10.22214/ijraset.2022.46100.

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Abstract: In this paper, we implemented 2-bit Multiplier Circuit using Pass Transistor Logic. Pass Transistor Logic is used for high speed technology and is easy to build the basic gate structures. The developed circuit is an extension of pass transistor logic Ex-or gate. The proposed Multiplier circuit is implemented in 2x2 bit multiplier to achieve high speed, low area and less power dissipation. VLSI schematic tool and the analysis is done by using the LT Spice simulator. This paper aims at an optimization of power area and voltages of multiplier to show the better performance. The design i

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