Relevant bibliographies by topics / Pass Transistor Logic (PTL)

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Pass Transistor Logic (PTL)'

Author: Grafiati
Published: 4 June 2021
Last updated: 25 July 2025

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Journal articles on the topic "Pass Transistor Logic (PTL)"

1

Arunabala, Dr C. "Design of a 4 bit Arithmetic and Logical unit with Low Power and High Speed." International Journal of Innovative Technology and Exploring Engineering 10, no. 5 (2021): 87–92. http://dx.doi.org/10.35940/ijitee.e8660.0310521.

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In this presented work we designed the 4- bit Arithmetic & Logical Unit (ALU) by using the different modules. The Various modules are AND gate & OR gate designed with six transistors, While the XOR modules is designed with both eight transistors & six transistors. The six transistor XOR module gives optimized results. Another one is the four by one multiplexer designed with eight transistors implemented using Pass transistor logic (PTL) style. The full adder module is designed by using 18 transistors implemented through PTL style. Here because of PTL style the number of transistor
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Dr.C.Arunabala*, Ch.Jyothirmayi, N. S. V. Sreeja.T D, Burra Hrithika Suma, Udumula Reddy, and I.R.AnushaDevi. "Design of a 4 bit Arithmetic and Logical unit with Low Power and High Speed." International Journal of Innovative Technology and Exploring Engineering (IJITEE) 10, no. 5 (2021): 87–92. https://doi.org/10.35940/ijitee.E8660.0310521.

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In this presented work we designed the 4- bit Arithmetic & Logical Unit (ALU) by using the different modules. The Various modules are AND gate & OR gate designed with six transistors, While the XOR modules is designed with both eight transistors & six transistors. The six transistor XOR module gives optimized results. Another one is the four by one multiplexer designed with eight transistors implemented using Pass transistor logic (PTL) style. The full adder module is designed by using 18 transistors implemented through PTL style. Here because of PTL style the number of transistor
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Cho, Geun Rae, and Tom Chen. "On Mixed PTL/Static Logic for Low-power and High-speed Circuits." VLSI Design 12, no. 3 (2001): 399–406. http://dx.doi.org/10.1155/2001/59548.

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We present more evidence in a 0.25 μm CMOS technology that the pass-transistor logic (PTL) structure that mixes conventional PTL structure with static logic gates can achieve better performance and lower power consumption compared to conventional PTL structure. The goal is to use the static gates to perform both logic functions as well as buffering. Our experimental results demonstrate that the proposed mixed PTL structure beats pure static structure and conventional PTL in 9 out of 15 test cases for either delay or power consumption or both in a 0.25 μm CMOS process. The average delay, power
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Ganesh, Racha, K. Lal Kishore, and P. Srinivasa Rao. "Performance Analysis of Hybrid Comparator using 45nm Technology." CVR Journal of Science and Technology 25, no. 1 (2024): 15–23. http://dx.doi.org/10.32377/cvrjst2503.

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In the present real-time world, due to the improvements and innovations of System on Chip (SoC) applications, there is a requirement to integrate multiple technology design topologies. The electronic system design is classified as analog, digital, and mixed-signal design. The comparator is the major building block used in the datapath of System on Chip (SoC) application device. The usage of these devices depends on not only functionality but also on the non-functionality parameters considering different performance estimation metrics. The nonfunctional performance metrics for a transistor leve
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Lamani, Deepa Suranam, and Dr H. V. Ravish Aradhya. "Design of Low Power 64-Bit Hybrid Full Adder." International Journal for Research in Applied Science and Engineering Technology 11, no. 8 (2023): 2200–2205. http://dx.doi.org/10.22214/ijraset.2023.55554.

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Abstract: In the realm of Computer Science, integrated circuits (ICs) have propelled microprocessor and digital signal processor development, hinging on the 1-bit full adder's significance for mathematical tasks. To amplify overall efficiency, enhancing this adder is pivotal. As demand surges for power-efficient devices like smartphones and MP3 players, maintaining a balance between speed, size, and power usage becomes imperative. Engineers tackle this challenge while bridging battery technology gaps. We propose advanced 1-bit full adder designs, evaluated via Cadence Virtuoso. A hybrid versio
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Rajasekhar, K., B. Sandhya, G. Srinivas, and N. Manogna. "Performance of Different Full Adder Structures for Optimized Design." International Journal of Advance Research and Innovation 8, no. 2 (2020): 74–80. http://dx.doi.org/10.51976/ijari.822013.

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Design of high performance and energy efficient digital systems are one of the most important research areas in VLSI system design which is suitable for real-time applications. One of the functional elements used in complex arithmetic circuits is an adder. To design an energy efficient adder one-bit full adder cell is designed based on adiabatic logic. The proposed ALFA cell is designed using adiabatic logic which results with the negligible amount of exchange of energy with the surrounding environment. Therefore, the application circuits based on this logic will have negligible energy loss du
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Jiang, Jin Tao, Li Fang Ye, and Jian Ping Hu. "Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration." Applied Mechanics and Materials 39 (November 2010): 73–78. http://dx.doi.org/10.4028/www.scientific.net/amm.39.73.

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Leakage power reduction is extremely important in the design of nano-circuits. Gate leakage has become a significant component in currently used nanometer CMOS processes with gate oxide structure. The structure and operation of the PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits that consist mostly of PMOS transistors are complementary to PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) ones that consist mostly of NMOS transistors. This paper investigates gate leakage reduction of the PAL-2P circuits in nanometer CMOS processes with g
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Siddaiah, Premananda Belegehalli, Sahithi Narsepalli, Sanya Mittal, and Abdur Rehman. "Area and power efficient divide-by-32/33 dual-modulus pre-scaler using split-path TSPC with AVLS for frequency divider." Journal of Electrical Engineering 74, no. 5 (2023): 403–12. http://dx.doi.org/10.2478/jee-2023-0048.

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Abstract Pre-scalers are electronic circuits used in phase-locked loops to multiply frequencies. This is achieved by dividing the high-frequency signals generated from a voltage-controlled oscillator. The high-frequency operation of pre-scaler circuits leads to significantly higher power consumption. To address this, D flip-flops (D-FF) realized using true-single phase clocking (TSPC) logic. The work suggests incorporating the Adaptive Voltage Level Source (AVLS) circuit with the Dual Modulus Pre-Scaler (DMPS) circuit to reduce power consumption. In addition to the incorporation of the AVLS ci
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Lin, Jin-Fa, Zheng-Jie Hong, Chang-Ming Tsai, Bo-Cheng Wu, and Shao-Wei Yu. "Novel Low-Complexity and Low-Power Flip-Flop Design." Electronics 9, no. 5 (2020): 783. http://dx.doi.org/10.3390/electronics9050783.

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In this paper, a compact and low-power true single-phase flip-flop (FF) design with fully static operations is presented. The design is developed by using various circuit-reduction schemes and features a hybrid logic style employing both pass transistor logic (PTL) and static complementary metal-oxide semiconductor (CMOS) logic to reduce circuit complexity. These circuit optimization measures pay off in various aspects, including smaller clock-to-Q (CQ) delay, lower average power, lower leakage power, and smaller layout area; and the transistor-count is only 17. Fabricated in TSMC 180 nm CMOS
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Mathiazhagan, V., N. P. Ananthamoorthy, and C. Venkatesh. "Design and Implementation of Enhanced Edge Triggered Flip-Flop for Low Power Dissipation." Journal of Nanoelectronics and Optoelectronics 17, no. 9 (2022): 1261–73. http://dx.doi.org/10.1166/jno.2022.3291.

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Power consumption in integrated circuits is one of the prominent aspects of the design methodologies that affect cost and efficiency. It holds a prominent role in the design and fabrication of Integrated Circuits (ICs). Power consumption in ICs increases largely due to clock diffusion techniques and Flip-Flops (FFs) since they consume a huge amount of power to carry out internal transitions. Various researchers have proposed different flip-flop circuit designs for reducing power consumption in clocking systems. When integrated circuits are operating at high frequency, the clock functions are u
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Dissertations / Theses on the topic "Pass Transistor Logic (PTL)"

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Garg, Rajesh. "Generalized buffering of pass transistor logic (PTL) stages using Boolean division and don't cares." Texas A&M University, 2003. http://hdl.handle.net/1969.1/5906.

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Pass Transistor Logic (PTL) is a well known approach for implementing digital circuits. In order to handle larger designs and also to ensure that the total number of series devices in the resulting circuit is bounded, partitioned Reduced Ordered Binary Decision Diagrams (ROBDDs) can be used to generate the PTL circuit. The output signals of each partitioned block typically needs to be buffered. In this thesis, a new methodology is presented to perform generalized buffering of the outputs of PTL blocks. By performing the Boolean division of each PTL block using different gates in a library, we
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Ragavan, Rengarajan. "Reconfigurable FSM for Ultra-Low Power Wireless Sensor Network Nodes." Thesis, Linköpings universitet, Elektroniska komponenter, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-100121.

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Wireless sensor networks (WSN) play an important role in today’s monitoring and controlsystems like environmental monitoring, military surveillance, industrial sensing and control, smarthome systems and tracking systems. As the application of WSN grows by leaps and bounds, there is anincreasing demand in placing a larger number of sensors and controllers to meet the requirements. Theincreased number of sensors necessitates flexibility in the functioning of nodes. Nodes in wirelesssensor networks should be capable of being dynamically reconfigured to perform various tasks is theneed of the hour
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Varadharajan, Swetha. "Digital and Analog Applications of Double Gate Mosfets." Ohio University / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1132759182.

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Henry, Michael B. "Emerging Power-Gating Techniques for Low Power Digital Circuits." Diss., Virginia Tech, 2011. http://hdl.handle.net/10919/29627.

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As transistor sizes scale down and levels of integration increase, leakage power has become a critical problem in modern low-power microprocessors. This is especially true for ultra-low-voltage (ULV) circuits, where high levels of leakage force designers to chose relatively high threshold voltages, which limits performance. In this thesis, an industry-standard technique known as power-gating is explored, whereby transistors are used to disconnect the power from idle portions of a chip. Present power-gating implementations suffer from limitations including non-zero off-state leakage, which ca
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Tsai, Ming-Yu, and 蔡明諭. "An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/09027930047814983581.

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博士<br>國立中山大學<br>資訊工程學系研究所<br>98<br>The mainstream of current VLSI design and logic synthesis is based on traditional CMOS logic circuits. However, in the past two decades, various new logic circuit design styles based on pass-transistor logic (PTL) have been proposed. Compared with CMOS circuits, these PTL-based circuits are claimed to have better results in area, speed, and power in some particular applications, such as adder and multiplier designs. Since most current automatic logic synthesis tools (such as Synopsys Design Compiler) are based on conventional CMOS standard cell library, the c
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WANG, JIA-LONG, and 王家龍. "Area-optimal pass transistor logic minimization." Thesis, 1989. http://ndltd.ncl.edu.tw/handle/79027637899409777660.

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Chen, Shi Zong, and 陳世宗. "Sirup: single rail up-down pass-transistor-logic." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/65632113048817408437.

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Hsu, Chih-Cheng, and 許志成. "Automatic Optimization in Pass-Transistor-Based Logic Synthesizer." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/86877104888035726165.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>88<br>In this thesis, An automatic optimization logic synthesizer in pass-transistor-based is developed for logic mapping of the combinational circuits. The format of inputs is Boolean functions with expression of sum of product and we can input several functions for hardware sharing at the same time. Depending the difference of circuits, we use the RC delay model to do optimization for both area and speed performance. The final, output is Verilog gate-level code and HSPICE netlist that provide Verilog-in for automatic place-and-route and simulation. It only needs
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VEN-CHIEH, HSIEH, and 謝文傑. "A New Logic Synthesis and Optimization Procedure Using Pass-Transistor Logic." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/96660896455884414515.

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碩士<br>淡江大學<br>電機工程學系<br>88<br>At logic design level, a proper choice of a circuit style for implementing combinational logic is very important. Many kinds of logic styles using pass-transistor circuit have been proposed with the objective to improve the performance of static CMOS logic. And the advantages present by pass-transistor logic have been proved in many cases from 2-input XOR gate to Multiplier. But when compares to classical NAND/NOR or some other simple logic gate, functions can be realized with better performance and smaller area by using static CMOS logic. The result a logic style
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Chen, Jian-Hung, and 陳建宏. "Low Power and High Speed Logic Synthesis with Pass Transistor Logic." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/59671970997835239984.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>89<br>In this thesis, a pass-transistor logic synthesizer is developed for logic mapping of any combinational circuits based on only two types of cells: 2-to-1 multiplexors and inverters. The input contains several sum-of-product Boolean function expressions. Our synthesizer will consider the hardware sharing among these Boolean functions in order to save area. The output of our synthesizer is pass-transistor-based circuits with optimized transistor width in terms of user-specified speed and power performance measurement. During optimization, the Elmore RC delay mo
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Books on the topic "Pass Transistor Logic (PTL)"

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Mokhlesi, Jamileh. Design automation for differential pass-transistor logic. National Library of Canada, 1994.

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Mittal, Manish. Application of GaAS differential pass transistor logic in high speed digital circuits. National Library of Canada = Bibliothèque nationale du Canada, 1992.

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Pasternak, John Henry. High-speed differential pass-transistor logic. 1991.

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Pasternak, John Henry. CMOS pass-transistor logic design for VLSI. 1987.

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Book chapters on the topic "Pass Transistor Logic (PTL)"

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Munteanu, Mihai, Peter A. Ivey, Luke Seed, Marios Psilogeorgopoulos, Neil Powell, and Istvan Bogdan. "Single Ended Pass-Transistor Logic." In VLSI: Systems on a Chip. Springer US, 2000. http://dx.doi.org/10.1007/978-0-387-35498-9_19.

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Babu, Hafiz Md Hasan. "Easily Testable PLAs Using Pass Transistor Logic." In VLSI Circuits and Embedded Systems. CRC Press, 2022. http://dx.doi.org/10.1201/9781003269182-16.

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Babu, Hafiz Md Hasan. "Multiple-Valued Flip-Flops Using Pass Transistor Logic." In VLSI Circuits and Embedded Systems. CRC Press, 2022. http://dx.doi.org/10.1201/9781003269182-9.

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Hu, Jianping, Xiaoyan Luo, and Li Su. "A New Clocked Adiabatic Logic with Complementary Pass-Transistor Logic Evaluation Trees." In 2011 International Conference in Electrics, Communication and Automatic Control Proceedings. Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-8849-2_224.

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Raj, Sumit, Utkarsh Chaurasia, Aayush Bahukhandi, and Poornima Mittal. "Hybrid Approximate Adders Using Pass Transistor Logic and Transmission Gate." In Advances in Intelligent Systems and Computing. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-4369-9_28.

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Manju, C. S., N. Poovizhi, and R. Rajkumar. "Power Efficient Pulse Triggered Flip-Flop Design Using Pass Transistor Logic." In Emerging Trends in Computing and Expert Technology. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-32150-5_5.

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Kanoujia, Sandhya, Rishav Kumar, and P. Karuppanan. "Low Power Radix-4 Booth Multiplier Design Using Pass Transistor Logic." In VLSI, Communication and Signal Processing. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-0973-5_26.

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Babu, Hafiz Md Hasan. "Voltage-Mode Pass Transistor-Based Multi-Valued Multiple-Output Logic Circuits." In VLSI Circuits and Embedded Systems. CRC Press, 2022. http://dx.doi.org/10.1201/9781003269182-10.

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Ni, Haiyan, Xiaolei Sheng, and Jianping Hu. "Voltage Scaling for Adiabatic Register File Based on Complementary Pass-Transistor Adiabatic Logic." In Lecture Notes in Electrical Engineering. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-19706-2_6.

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Hang, Guoqiang, Yang Yang, Xiaohui Hu, and Hongli Zhu. "Application of Neuron-MOS and Pass Transistor to Voltage-Mode Ternary Logic Circuit." In Electrical, Information Engineering and Mechatronics 2011. Springer London, 2012. http://dx.doi.org/10.1007/978-1-4471-2467-2_249.

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Conference papers on the topic "Pass Transistor Logic (PTL)"

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Chowdhury, Paramita, Arnesh Halder, Ankit Mahata, Anshu Das, Molla Safidur Rahaman, and Sunipa Roy. "Designing and Utilizing of Novel Pass Transistor Logic for Low Power CMOS Full Adder." In 2025 IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI). IEEE, 2025. https://doi.org/10.1109/iatmsi64286.2025.10984669.

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S, Kusuma H., H. M. Kalpana, and Ravi H. K. "Design and Comparative Analysis of Half and Full Adders Using CMOS and Pass Transistor Logic Styles." In 2025 3rd International Conference on Smart Systems for applications in Electrical Sciences (ICSSES). IEEE, 2025. https://doi.org/10.1109/icsses64899.2025.11010034.

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Sardroudi, Farzin Mahboob, Mehdi Habibi, and Mohammad Hossein Moaiyeri. "Design of Long Signal Path Ternary Computational Blocks Using Dynamic and Pass Transistor Logic Based on Carbon Nanotube Field Effect Transistors." In 2024 6th Iranian International Conference on Microelectronics (IICM). IEEE, 2024. https://doi.org/10.1109/iicm65053.2024.10824662.

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Sudhakar, Pasupuleti Naga, and Vijaya Kishore Veparala. "Design of GNRFET ternary circuits using pass transistor logic (PTL)." In THE 6TH INTERNATIONAL CONFERENCE OF ICE-ELINVO 2023: Digital Solutions for Sustainable and Green Development. AIP Publishing, 2025. https://doi.org/10.1063/5.0249485.

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Meher, P. K., Shen-Fu Hsiao, Chia-Sheng Wen, and Ming-Yu Tsai. "Low-Cost Design of Serial-Parallel Multipliers Over GF(2^m) Using Hybrid Pass-Transistor Logic (PTL) and CMOS Logic." In 2010 International Symposium on Electronic System Design (ISED 2010). IEEE, 2010. http://dx.doi.org/10.1109/ised.2010.33.

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Oliver, Lara D., Krishnendu Chakrabarty, and Hisham Z. Massoud. "Dual-threshold pass-transistor logic design." In the 19th ACM Great Lakes symposium. ACM Press, 2009. http://dx.doi.org/10.1145/1531542.1531610.

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Zhou, Hai, and Adnan Aziz. "Buffer minimization in pass transistor logic." In the 2000 international symposium. ACM Press, 2000. http://dx.doi.org/10.1145/332357.332384.

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Buch, Narayan, Newton, and Sangiovanni-Vincentelli. "Logic synthesis for large pass transistor circuits." In Proceedings of IEEE International Conference on Computer Aided Design (ICCAD). IEEE, 1997. http://dx.doi.org/10.1109/iccad.1997.643609.

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Tai-Hung Liu, M. K. Ganai, A. Aziz, and J. L. Burns. "Performance driven synthesis for pass-transistor logic." In Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013). IEEE, 1999. http://dx.doi.org/10.1109/icvd.1999.745184.

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Hang, Guoqiang, and Xuanchang Zhou. "Novel CMOS static ternary logic using double pass-transistor logic." In 2010 2nd International Conference on Information Science and Engineering (ICISE). IEEE, 2010. http://dx.doi.org/10.1109/icise.2010.5689867.

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