Log in

Relevant bibliographies by topics / Pass Transistor Logic (PTL) / Journal articles

To see the other types of publications on this topic, follow the link: Pass Transistor Logic (PTL).

Journal articles on the topic 'Pass Transistor Logic (PTL)'

Author: Grafiati

Published: 4 June 2021

Last updated: 11 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'Pass Transistor Logic (PTL).'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

Cho, Geun Rae, and Tom Chen. "On Mixed PTL/Static Logic for Low-power and High-speed Circuits." VLSI Design 12, no. 3 (January 1, 2001): 399–406. http://dx.doi.org/10.1155/2001/59548.

Full text

Abstract:

We present more evidence in a 0.25 μm CMOS technology that the pass-transistor logic (PTL) structure that mixes conventional PTL structure with static logic gates can achieve better performance and lower power consumption compared to conventional PTL structure. The goal is to use the static gates to perform both logic functions as well as buffering. Our experimental results demonstrate that the proposed mixed PTL structure beats pure static structure and conventional PTL in 9 out of 15 test cases for either delay or power consumption or both in a 0.25 μm CMOS process. The average delay, power consumption, and power-delay product of the proposed structure for 15 test cases are 10% to 20% better of than the pure static implementations and up to 50% better than the conventional PTL implementations.

APA, Harvard, Vancouver, ISO, and other styles

2

Jiang, Jin Tao, Li Fang Ye, and Jian Ping Hu. "Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration." Applied Mechanics and Materials 39 (November 2010): 73–78. http://dx.doi.org/10.4028/www.scientific.net/amm.39.73.

Full text

Abstract:

Leakage power reduction is extremely important in the design of nano-circuits. Gate leakage has become a significant component in currently used nanometer CMOS processes with gate oxide structure. The structure and operation of the PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits that consist mostly of PMOS transistors are complementary to PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) ones that consist mostly of NMOS transistors. This paper investigates gate leakage reduction of the PAL-2P circuits in nanometer CMOS processes with gate oxide materials. An s27 benchmark circuit from the ISCAS89 sequential benchmark set is verified using the PAL-2P scheme. All circuits are simulated with HSPICE using the 65nm CMOS process with gate oxide materials. Based on the power dissipation models of PAL-2P adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations using SPICE simulations. The PAL-2P circuits consume low static power compared with traditional PAL-2N ones.

APA, Harvard, Vancouver, ISO, and other styles

3

Lin, Jin-Fa, Zheng-Jie Hong, Chang-Ming Tsai, Bo-Cheng Wu, and Shao-Wei Yu. "Novel Low-Complexity and Low-Power Flip-Flop Design." Electronics 9, no. 5 (May 10, 2020): 783. http://dx.doi.org/10.3390/electronics9050783.

Full text

Abstract:

In this paper, a compact and low-power true single-phase flip-flop (FF) design with fully static operations is presented. The design is developed by using various circuit-reduction schemes and features a hybrid logic style employing both pass transistor logic (PTL) and static complementary metal-oxide semiconductor (CMOS) logic to reduce circuit complexity. These circuit optimization measures pay off in various aspects, including smaller clock-to-Q (CQ) delay, lower average power, lower leakage power, and smaller layout area; and the transistor-count is only 17. Fabricated in TSMC 180 nm CMOS technology, it reduces by over 29% the chip area compared to the conventional transmission gate FF (TGFF). To further show digital circuit/system level advantages, a multi-mode shift register has been realized. Experimental measurement results at 1.8 V/4 MHz show that, compared with the TGFF design, the proposed design saves 64.7% of power consumption while reducing chip area by 26.2%.

APA, Harvard, Vancouver, ISO, and other styles

4

Ng, K. W., and K. T. Lau. "Improved PAL-2N logic with complementary pass-transistor logic evaluation tree." Microelectronics Journal 31, no. 1 (January 2000): 55–59. http://dx.doi.org/10.1016/s0026-2692(99)00089-0.

Full text

APA, Harvard, Vancouver, ISO, and other styles

5

Zhang, Wei Qiang, Li Su, Jun Wang, Bin Bin Liu, and Jian Ping Hu. "Design and Manufacture of Energy-Recycling Pads for Low-Power Chips." Key Engineering Materials 460-461 (January 2011): 467–72. http://dx.doi.org/10.4028/www.scientific.net/kem.460-461.467.

Full text

Abstract:

Energy-recycling output pad cells for driving adiabatic chips are designed, which have been fabricated with Chartered 0.35um process and tested. The proposed energy-recycling output pad cells include mainly bonding pads, electrostatic discharge (ESD) protection circuits, and two stage energy-recycling buffers that are used to drive the large load capacitances on chip pads. The two stage energy-recycling buffers are realized using CPAL (Complementary Pass-transistor Adiabatic Logic) and PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration), respectively. For comparison, a conventional output pad cell is also embedded in the test chip. The function verifications and energy loss tests for the three output pad cells are carried out. The energy consumption of the proposed two energy-recycling output pad cells has large savings over a wide range of frequencies, as compared with the conventional CMOS counterparts, since the energy on large load capacitances in the chip pads can be well recycled.

APA, Harvard, Vancouver, ISO, and other styles

6

Parameshwara, M. C., and H. C. Srinivasaiah. "Low-Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic Applications." Journal of Circuits, Systems and Computers 26, no. 01 (October 4, 2016): 1750014. http://dx.doi.org/10.1142/s0218126617500141.

Full text

Abstract:

A novel “16 transistor” (16T) 1-bit Full adder (FA) circuit based on CMOS transmission-gate (TG) and pass transistor logics (PTL) is presented. This 1-bit FA circuit with TG and PTL structure is derived based on carry dependent sum implementation approach. The design metrics (DMs) such as power, delay, power-delay-product (PDP), and transistor-count (TC) for this 1-bit FA are compared against eight other standard and state-of-the-art 1-bit FA circuits reported till date. All the comparisons are done at post layout level with respect to the DMs under consideration. The proposed 1-bit FA dissipates an average power of 2.118[Formula: see text][Formula: see text]W, with a delay of 606 ps, with an area of 33.1[Formula: see text][Formula: see text]m2, resulting in a PDP of 1.28 fJ. This power and hence the PDP is the lowest of all, ever reported till date. In this comparative study a common test bench with a supply voltage [Formula: see text][Formula: see text]V, input signal frequency [Formula: see text][Formula: see text]MHz is used. This 1-bit FA is designed and implemented using Cadences' 90[Formula: see text]nm “generic-process-design-kit” (GPDK).

APA, Harvard, Vancouver, ISO, and other styles

7

Nuthalapati, Soniya, Ranjitha P.V.Sai, Radhika Rani Kalapala, Lourdu Sasi Rekha Lingisetty, Sirisha Mekala, and Parveen Mohammad Firdosia. "Design a Low Power and High Speed 130nm Fulladder using Exclusive-OR and Exclusive NOR Gates." International Journal of Innovative Technology and Exploring Engineering 10, no. 5 (March 30, 2021): 81–86. http://dx.doi.org/10.35940/ijitee.e8659.0310521.

Full text

Abstract:

This literature illustrates the high speed and low power Full Adder (FADD) designs. This study relates to the composited structure of FADD design composed in one unit. In this the EXCL-OR/EXCL-NOR designs are used to design the FADD. Mostly concentrates on high speed standard FADD structure by combining the EXCL-OR/EXCL-NOR design in single unit. We implemented two composite structures of FADD through the full swing EXCL-OR/EXCL-NOR designs. And the EXCL-OR/EXCL-NOR design is done through pass transistor logic (PTL) and the same design projected on the composited FADD design. Such that the delay, area of the design, power requirement for the circuit gets optimized. The two composited FADD designs are compared and reduced the constraints of power requirement, area, delay and the power delay product (PDP). The simulated outcomes are verified through 130nnm CMOS mentor graphics tool.

APA, Harvard, Vancouver, ISO, and other styles

8

NG, K. W., and K. T. LAU. "A NOVEL ADIABATIC REGISTER FILE DESIGN." Journal of Circuits, Systems and Computers 10, no. 01n02 (February 2000): 67–76. http://dx.doi.org/10.1142/s0218126600000032.

Full text

Abstract:

A novel 8-word × 16-bit adiabatic register file is designed. The adiabatic circuits are based on the Pass-transistor Adiabatic Logic with NMOS pull-down configuration (PAL-2N). Using adiabatic switching technique, the power consumption of the register file is significantly reduced as the energy transferred to the large capacitance buses is mostly recovered. HSPICE simulation results have shown power savings of more than 77% as compared to the conventional CMOS implementation. Although the proposed register file is designed with only one read port and one write port, multiple read and/or write ports can be easily constructed by adding additional read and/or write port transistors.

APA, Harvard, Vancouver, ISO, and other styles

9

Ben-Asher, Yosi, Esti Stein, and Vladislav Tartakovsky. "FPGA Realization of the Reconfigurable Mesh Counting Algorithm." Journal of Circuits, Systems and Computers 30, no. 09 (January 18, 2021): 2150157. http://dx.doi.org/10.1142/s0218126621501577.

Full text

Abstract:

Pass transistor logic (PTL) is a circuit design technique wherein transistors are used as switches. The reconfigurable mesh (RM) is a model that exploits the power of PTLs signal switching, by enabling flexible bus connections in a grid of processing elements containing switches. RM algorithms have theoretical results proving that [Formula: see text] can speed up computations significantly. However, the RM assumes that the latency of broadcasting a signal through [Formula: see text] switches (bus length) is 1. This is an unrealistic assumption preventing physical realizations of the RM. We propose the restricted-RM (RRM) wherein the bus lengths are restricted to [Formula: see text], [Formula: see text]. We show that counting the number of 1-bits in an input of [Formula: see text] bits can be done in [Formula: see text] steps for [Formula: see text] by an [Formula: see text] RRM. An almost matching lower bound is presented, using a technique which adds to the few existing lower-bound techniques in this area. Finally, the algorithm was directly coded over an FPGA, outperforming an optimal tree of adders. This work presents an alternative way of counting, which is fundamental for summing, beating regular Boolean circuits for large numbers, where summing a vast amount of numbers is the basis of any accelerator in embedded systems such as neural-nets and streaming. a

APA, Harvard, Vancouver, ISO, and other styles

10

Bhattacharjee, Pritam, and Alak Majumder. "A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application." Journal of Circuits, Systems and Computers 28, no. 07 (June 27, 2019): 1950108. http://dx.doi.org/10.1142/s0218126619501081.

Full text

Abstract:

Advancement in technology towards mobile computing and communication demands longer battery life, which mandates the low power design methodologies. In this paper, we have presented a novel low-power 8T flip-flop (FF) architecture, which has outsmarted the existing well-known dynamic, semi-dynamic and explicit pulsed flip-flops in terms of power and delay. The major ingredient of this architecture is a voltage keeper, which is incorporated to achieve reliable logic switching at the propagating nodes of the design. However, we have also come up with two new approaches of gated clock generation based on transmission gate (TG) and pass transistor logic (PTL) as a modification of LECTOR-based gating. These gating logics have proved themselves to be competent enough to reduce both the static and dynamic power dissipations and hence are employed to the proposed flip-flop to achieve further reduction in power than its nongated correspondent. The performance of this proposed gated flip-flop is tested in a finite state machine with its application in low-power serial adder design. All the simulations are carried out using 65-nm and 90-nm CMOS technologies with a power supply of 1.1[Formula: see text]V at 6.6[Formula: see text]GHz clock frequency. The gated FF saves 52.12%, 6.36% and 28.18% average power-using LECTOR, TG and PTLs, respectively, with respect to its nongated counterpart in 65-nm technology. The performance metrics of gated and nongated proposed designs are affirmed in the environment of commercialized CMOS foundry.

APA, Harvard, Vancouver, ISO, and other styles

11

Dokic, B. L. "A Review on Energy Efficient CMOS Digital Logic." Engineering, Technology & Applied Science Research 3, no. 6 (December 18, 2013): 552–61. http://dx.doi.org/10.48084/etasr.389.

Full text

Abstract:

Autonomy of power supply used in portable devices directly depends on energy efficiency of digital logic. This means that digital systems, beside high processing power and very complex functionality, must also have very low power consumption. Power consumption depends on many factors: system architecture, technology, basic cells topology-speed, and accuracy of assigned tasks. In this paper, a review and comparison of CMOS topologies techniques and operating modes is given, as CMOS technology is expected to be the optimum choice in the near future. It is shown that there is a full analogy in the behavior of digital circuits in sub-threshold and strong inversion. Therefore, synthesis of digital circuits is the same for both strong and weak operating modes. Analysis of the influence of the technology, MOS transistor threshold voltage (Vt) and power supply voltage (Vdd) on digital circuit power consumption and speed for both operating modes is given. It is shown that optimal power consumption (minimum power consumption for given speed) depends on optimal choice of threshold, and power supply voltage. Multi Vdd /Vt techniques are analyzed as well. A review and analysis of alternative logical circuit's topologies – pass logic (PL), complementary pass logic (CPL), push-pull pass logic (PPL) and adiabatic logic – is also given. As shown, adiabatic logic is the optimum choice regarding energy efficiency.

APA, Harvard, Vancouver, ISO, and other styles

12

Wu, Yang Bo, Jian Ping Hu, and Hong Li. "Leakage Power Estimation of Adiabatic Circuits Using SPICE in Nanometer CMOS Processes." Advanced Materials Research 108-111 (May 2010): 625–30. http://dx.doi.org/10.4028/www.scientific.net/amr.108-111.625.

Full text

Abstract:

In deep sub-micro CMOS process, the leakage power is becoming a significant proportion in power dissipation. Hence, estimating the leakage power of CMOS circuits is very important in low-power design. In this paper, an estimation technology for the total leakage power of adiabatic logic circuits by using SPICE is proposed. The basic principle of power estimation for traditional CMOS circuits using SPICE is introduced. According to the energy dissipation characteristic of adiabatic circuits, the estimation technology for leakage power is discussed. Taken as an example, the estimation for total leakage power dissipations of PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) circuits is illustrated using the proposed estimation technology.

APA, Harvard, Vancouver, ISO, and other styles

13

Hu, Jian Ping, Xiao Ying Yu, and Bin Bin Liu. "Manufacturing and Testing of Adiabatic Array Multiplier for Micro Power Digital Systems." Key Engineering Materials 460-461 (January 2011): 473–78. http://dx.doi.org/10.4028/www.scientific.net/kem.460-461.473.

Full text

Abstract:

Power-efficient multipliers are essential for micro systems, where low-power signal processing hardware is demanded. This paper presents an adiabatic array multiplier based on PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) circuits. It is composed of a multiplier array containing partial product generators and 1-bit (half and full) adders, and a final carry-lookahead adder. For comparison, a conventional array multiplier is also implemented. Full-custom layouts are drawn, and HSPICE simulations are carried out using the net-list extracted from their layout. The adiabatic and conventional array multipliers have been embedded in a test chip, which have been fabricated with Chartered 0.35um process and tested to verify its function.

APA, Harvard, Vancouver, ISO, and other styles

14

AL-ASSADI, WALEED, ANURA P. JAYASUMANA, and YASHWANT K. MALAIYA. "Pass-transistor logic design." International Journal of Electronics 70, no. 4 (April 1991): 739–49. http://dx.doi.org/10.1080/00207219108921324.

Full text

APA, Harvard, Vancouver, ISO, and other styles

15

Pasternak, J. H., and C. A. T. Salama. "Differential pass-transistor logic." IEEE Circuits and Devices Magazine 9, no. 4 (July 1993): 23–28. http://dx.doi.org/10.1109/101.250230.

Full text

APA, Harvard, Vancouver, ISO, and other styles

16

Pasternak, J. H., A. S. Shubat, and C. A. T. Salama. "CMOS differential pass-transistor logic design." IEEE Journal of Solid-State Circuits 22, no. 2 (April 1987): 216–22. http://dx.doi.org/10.1109/jssc.1987.1052705.

Full text

APA, Harvard, Vancouver, ISO, and other styles

17

Zhou, H., and A. Aziz. "Buffer minimization in pass transistor logic." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20, no. 5 (May 2001): 693–97. http://dx.doi.org/10.1109/43.920711.

Full text

APA, Harvard, Vancouver, ISO, and other styles

18

Yano, K., Y. Sasaki, K. Rikino, and K. Seki. "Top-down pass-transistor logic design." IEEE Journal of Solid-State Circuits 31, no. 6 (June 1996): 792–803. http://dx.doi.org/10.1109/4.509865.

Full text

APA, Harvard, Vancouver, ISO, and other styles

19

Pasternak, J. H., and C. A. T. Salama. "GaAs MESFET differential pass-transistor logic." IEEE Journal of Solid-State Circuits 26, no. 9 (1991): 1309–16. http://dx.doi.org/10.1109/4.84949.

Full text

APA, Harvard, Vancouver, ISO, and other styles

20

Pasternak, J. H., and C. A. T. Salama. "GaAs MESFET differential pass-transistor logic." Electronics Letters 26, no. 19 (1990): 1597. http://dx.doi.org/10.1049/el:19901023.

Full text

APA, Harvard, Vancouver, ISO, and other styles

21

Zimmermann, R., and W. Fichtner. "Low-power logic styles: CMOS versus pass-transistor logic." IEEE Journal of Solid-State Circuits 32, no. 7 (July 1997): 1079–90. http://dx.doi.org/10.1109/4.597298.

Full text

APA, Harvard, Vancouver, ISO, and other styles

22

Oklobdzija, V. G., and B. Duchene. "Synthesis of high-speed pass-transistor logic." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 44, no. 11 (1997): 974–76. http://dx.doi.org/10.1109/82.644054.

Full text

APA, Harvard, Vancouver, ISO, and other styles

23

Zhuang, N., M. V. Scotti, and P. Y. K. Cheung. "PTM: Technology mapper for pass-transistor logic." IEE Proceedings - Computers and Digital Techniques 146, no. 1 (1999): 13. http://dx.doi.org/10.1049/ip-cdt:19990244.

Full text

APA, Harvard, Vancouver, ISO, and other styles

24

Hu, Xuan, Amy S. Abraham, Jean Anne C. Incorvia, and Joseph S. Friedman. "Hybrid Pass Transistor Logic With Ambipolar Transistors." IEEE Transactions on Circuits and Systems I: Regular Papers 68, no. 1 (January 2021): 301–10. http://dx.doi.org/10.1109/tcsi.2020.3034042.

Full text

APA, Harvard, Vancouver, ISO, and other styles

25

SHAMANNA, M., K. CAMERON, and S. R. WHITAKER. "Multiple-input, multiple-output pass transistor logic." International Journal of Electronics 79, no. 1 (July 1995): 33–45. http://dx.doi.org/10.1080/00207219508926248.

Full text

APA, Harvard, Vancouver, ISO, and other styles

26

Jung, Seong-Ook, and Sung-Mo Kang. "Modular charge recycling pass transistor logic (MCRPL)." Electronics Letters 36, no. 5 (2000): 404. http://dx.doi.org/10.1049/el:20000386.

Full text

APA, Harvard, Vancouver, ISO, and other styles

27

Shubat, A. S., J. A. Pretorius, and C. A. T. Salama. "Differential pass transistor logic in CMOS technology." Electronics Letters 22, no. 6 (1986): 294. http://dx.doi.org/10.1049/el:19860200.

Full text

APA, Harvard, Vancouver, ISO, and other styles

28

Hsiao, Shen-Fu, Jia-Siang Yeh, and Da-Yen Chen. "High-performance Multiplexer-based Logic Synthesis Using Pass-transistor Logic." VLSI Design 15, no. 1 (January 1, 2002): 417–26. http://dx.doi.org/10.1080/1065514021000054736.

Full text

Abstract:

An automatic logic/circuit synthesizer is developed which takes several Boolean functions as input and generates netlist output with basic composing cells from the pass-transistor cell library containing only two types of cells: 2-to-1 multiplexers and inverters. The synthesis procedure first constructs efficient binary decision diagrams (BDDs) for these Boolean functions considering both multi-function sharing and minimum width. Each node in the BDD trees is realized by using a 2-to-1 multiplexer (MUX) of proper driving capability designed pass-transistor logic. The inverters are then inserted all along the MUX paths in order to improve the speed performance and to alleviate the voltage-drop problem. Several methods are proposed to reduce the critical path delay in the multiplexer-chains for generation of faster circuits. Compared to the recently proposed pass-transistor-based top-down design, our synthesizer has better speed and area performance due to the reduced number of cascaded inverters.

APA, Harvard, Vancouver, ISO, and other styles

29

Srivastava, A. "A Study of n-MOS Natural Transistor for Pass Transistor Logic." Physica Status Solidi (a) 126, no. 1 (July 16, 1991): K87—K92. http://dx.doi.org/10.1002/pssa.2211260149.

Full text

APA, Harvard, Vancouver, ISO, and other styles

30

Jaekel, A., S. Bandyopadhyay, and G. A. Jullien. "Multi-level factorisation technique for pass transistor logic." IEE Proceedings - Circuits, Devices and Systems 145, no. 1 (1998): 48. http://dx.doi.org/10.1049/ip-cds:19981737.

Full text

APA, Harvard, Vancouver, ISO, and other styles

31

Abbasian, A., S. H. Rasouli, A. Afzali-Kusha, and M. Nourani. "No-race charge-recycling complementary pass transistor logic." IEE Proceedings - Computers and Digital Techniques 151, no. 3 (2004): 183. http://dx.doi.org/10.1049/ip-cdt:20040256.

Full text

APA, Harvard, Vancouver, ISO, and other styles

32

CHANG, ROBERT C., PO-CHUNG HUNG, and HSIN-LEI LIN. "LOW POWER ENERGY RECOVERY COMPLEMENTARY PASS-TRANSISTOR LOGIC." Journal of Circuits, Systems and Computers 15, no. 04 (August 2006): 491–504. http://dx.doi.org/10.1142/s0218126606003271.

Full text

Abstract:

A proposed adiabatic logic called Energy Recovery Complementary Pass-transistor Logic (ERCPL) is presented in this paper. It operates with a two-phase nonoverlapping power-clock supply. It uses bootstrapping to achieve efficient power saving and eliminates any nonadiabatic losses on the charge-steering devices. A scheme is used to recover part of the energy trapped in the bootstrapping nodes. We compare the energy dissipation between ERCPL and other logic circuits by simulation. Simulation results show that a pipelined ERCPL carry look-ahead adder can achieve a power reduction of 80% over the conventional CMOS case. Operation of an 8-bit ERCPL CLA fabricated using the TSMC 0.35 μm 1P4M CMOS technology has been experimentally verified.

APA, Harvard, Vancouver, ISO, and other styles

33

Hirabayashi, Kanji. "Self-checking CMOS circuits using pass-transistor logic." Journal of Electronic Testing 2, no. 2 (June 1991): 205–8. http://dx.doi.org/10.1007/bf00133504.

Full text

APA, Harvard, Vancouver, ISO, and other styles

34

Taki, Kazuo, and Bu-Yeol Lee. "Low power pass-transistor logic and application examples." Electronics and Communications in Japan (Part III: Fundamental Electronic Science) 81, no. 9 (September 1998): 54–66. http://dx.doi.org/10.1002/(sici)1520-6440(199809)81:9<54::aid-ecjc7>3.0.co;2-z.

Full text

APA, Harvard, Vancouver, ISO, and other styles

35

Thangasamy, Veeraiyah, Noor Ain Kamsani, Mohd Nizar Hamidon, Shaiful Jahari Hashim, Zubaida Yusoff, and Muhammad Faiz Bukhori. "Low power 18T pass transistor logic ripple carry adder." IEICE Electronics Express 12, no. 6 (2015): 20150176. http://dx.doi.org/10.1587/elex.12.20150176.

Full text

APA, Harvard, Vancouver, ISO, and other styles

36

Shelar, R. S., and S. S. Sapatnekar. "BDD decomposition for delay oriented pass transistor logic synthesis." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13, no. 8 (August 2005): 957–70. http://dx.doi.org/10.1109/tvlsi.2005.853601.

Full text

APA, Harvard, Vancouver, ISO, and other styles

37

Tsung-Te Liu, L. P. Alarcon, M. D. Pierson, and J. M. Rabaey. "Asynchronous Computing in Sense Amplifier-Based Pass Transistor Logic." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, no. 7 (July 2009): 883–92. http://dx.doi.org/10.1109/tvlsi.2008.2012054.

Full text

APA, Harvard, Vancouver, ISO, and other styles

38

Oklobdzija, V. G., D. Maksimovic, and Fengcheng Lin. "Pass-transistor adiabatic logic using single power-clock supply." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 44, no. 10 (1997): 842–46. http://dx.doi.org/10.1109/82.633443.

Full text

APA, Harvard, Vancouver, ISO, and other styles

39

Pasternak, J. H., and C. A. T. Salama. "Design of submicrometer CMOS differential pass-transistor logic circuits." IEEE Journal of Solid-State Circuits 26, no. 9 (1991): 1249–58. http://dx.doi.org/10.1109/4.84941.

Full text

APA, Harvard, Vancouver, ISO, and other styles

40

Avci, M., and T. Yildirim. "General design method for complementary pass transistor logic circuits." Electronics Letters 39, no. 1 (2003): 46. http://dx.doi.org/10.1049/el:20030102.

Full text

APA, Harvard, Vancouver, ISO, and other styles

41

Liu, F., and K. T. Lau. "Pass-transistor adiabatic logic with NMOS pull-down configuration." Electronics Letters 34, no. 8 (1998): 739. http://dx.doi.org/10.1049/el:19980571.

Full text

APA, Harvard, Vancouver, ISO, and other styles

42

Wu, Yangbo, and Jianping Hu. "Near-Threshold Computing of Clocked Adiabatic Logic with Complementary Pass-Transistor Logic Circuits." Journal of Low Power Electronics 7, no. 3 (August 1, 2011): 393–402. http://dx.doi.org/10.1166/jolpe.2011.1144.

Full text

APA, Harvard, Vancouver, ISO, and other styles

43

Lu, Bin Bin, and Jian Ping Hu. "Complementary Pass-Transistor Adiabatic Logic Using Dual Threshold CMOS Techniques." Applied Mechanics and Materials 39 (November 2010): 55–60. http://dx.doi.org/10.4028/www.scientific.net/amm.39.55.

Full text

Abstract:

With rapid technology scaling down, the energy dissipation of nanometer CMOS circuits is becoming a major concern, because of the increasing sub-threshold leakage in nanometer CMOS processes. This paper introduces a dual threshold CMOS (DTCMOS) technique for CPAL (complementary pass-transistor adiabatic logic) circuits to reduce sub-threshold leakage dissipations. The method to size the transistors of the dual-threshold CPAL gates is also discussed. A full adder using dual-threshold CPAL circuits is realized using 45nm BSIM4 CMOS model. HSPICE simulation results show that leakage dissipations of the CPAL full adder with DTCMOS techniques are reduced compared with the basic CPAL one.

APA, Harvard, Vancouver, ISO, and other styles

44

Cho, Geun Rae, and Tom Chen. "Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic." Analog Integrated Circuits and Signal Processing 42, no. 3 (March 2005): 219–29. http://dx.doi.org/10.1007/s10470-005-6756-7.

Full text

APA, Harvard, Vancouver, ISO, and other styles

45

Chang, R. C., P. C. Hung, and I. H. Wang. "Complementary pass-transistor energy recovery logic for low-power applications." IEE Proceedings - Computers and Digital Techniques 149, no. 4 (2002): 146. http://dx.doi.org/10.1049/ip-cdt:20020447.

Full text

APA, Harvard, Vancouver, ISO, and other styles

46

Oklobdzija, Vojin G. "Differential and pass-transistor CMOS logic for high performance systems." Microelectronics Journal 29, no. 10 (October 1998): 679–88. http://dx.doi.org/10.1016/s0026-2692(98)00033-0.

Full text

APA, Harvard, Vancouver, ISO, and other styles

47

WOO-HYUN PAIK HOON-JAE KI SOO-WON K. "Low power logic design using push-pull pass-transistor logics." International Journal of Electronics 84, no. 5 (May 1998): 467–78. http://dx.doi.org/10.1080/002072198134571.

Full text

APA, Harvard, Vancouver, ISO, and other styles

48

Chennakesavulu, M., T. Jayachandra Prasad, and V. Sumalatha. "Improved Performance of Error Controlling Codes Using Pass Transistor Logic." Circuits, Systems, and Signal Processing 37, no. 3 (July 4, 2017): 1145–61. http://dx.doi.org/10.1007/s00034-017-0596-4.

Full text

APA, Harvard, Vancouver, ISO, and other styles

49

Abbas, Waseem, Zubair Mehmood, and Munkyo Seo. "A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS." Electronics 9, no. 9 (September 13, 2020): 1502. http://dx.doi.org/10.3390/electronics9091502.

Full text

Abstract:

A 65–67 GHz phase-locked loop (PLL) with a novel low power phase-frequency detector (PFD) in 65 nm LP CMOS is presented. The PLL consists of a V-band voltage-controlled oscillator (VCO), a divide-by-two injection-locked frequency divider (ILFD), and a current-mode logic (CML) divider chain. A charge pump (CP) and a 2nd-order loop filter are used with PFD for VCO tuning. The PFD is implemented with 16 transistors with dead-zone-free capability. The measured locking range of the PLL is from 65.15 to 67.4 GHz, with −11.5 dBm measured output power at 66.05 GHz while consuming 88 mW. The measured phase noise at 1 MHz offset is −84.43 dBc/Hz. The chip area of the PLL is 0.84 mm2 including probing pads. The proposed PLL can be utilized as a frequency synthesizer for carrier signal generation in IEEE 802.11ad standard high data rate transceiver circuits.

APA, Harvard, Vancouver, ISO, and other styles

50

Pandey, Neeta, Damini Garg, Kirti Gupta, and Bharat Choudhary. "Hybrid Dynamic MCML Style: A High Speed Dynamic MCML Style." Journal of Engineering 2016 (2016): 1–10. http://dx.doi.org/10.1155/2016/8027150.

Full text

Abstract:

This paper proposes hybrid dynamic current mode logic (H-DyCML) as an alternative to existing dynamic CML (DyCML) style for digital circuit design in mixed-signal applications. H-DyCML introduces complementary pass transistors for implementation of logic functions. This allows reduction in the stacked source-coupled transistor pair levels in comparison to the existing DyCML style. The resulting reduction in transistor pair levels permits significant speed improvement. SPICE simulations using TSMC 180 nm and 90 nm CMOS technology parameters are carried out to verify the functionality and to identify their advantages. Some issues related to the compatibility of the complementary pass transistor logic have been investigated and the appropriate solutions have been proposed. The performance of the proposed H-DyCML gates is compared with the existing DyCML gates. The comparison confirms that proposed H-DyCML gates is faster than the existing DyCML gates.

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!