Relevant bibliographies by topics / Turbo decoder

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Turbo decoder'

Author: Grafiati
Published: 4 June 2021
Last updated: 14 March 2023

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'Turbo decoder.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "Turbo decoder"

1

Shafieipour, Mohammad, Heng-Siong Lim, and Teong-Chee Chuah. "Decoding of Turbo Codes in Symmetric Alpha-Stable Noise." ISRN Signal Processing 2011 (March 29, 2011): 1–7. http://dx.doi.org/10.5402/2011/683972.

Full text
Abstract:
This paper investigates the decoding of turbo codes in impulsive symmetric α-stable (SαS) noise. Due to the nonexistence of a closed-form expression for the probability density function (pdf) of α-stable processes, numerical-based SαS pdf is used to derive branch transition probability (btp) for the maximum a posteriori turbo decoder. Results show that in Gaussian noise, the turbo decoder achieves similar performance using both the conventional and the proposed btps, but in impulsive channels, the turbo decoder with the proposed btp substantially outperforms the turbo decoder utilizing the conventional btp. Results also confirm that the turbo decoder incorporating the proposed btp outperforms the existing Cauchy-based turbo decoder in non-Cauchy impulsive noise, while the two decoders accomplish similar performance in Cauchy noise.
APA, Harvard, Vancouver, ISO, and other styles
2

Boudaoud, A., M. El Haroussi, and E. Abdelmounim. "VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based on Majority Logic Codes." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 4 (August 1, 2017): 1824. http://dx.doi.org/10.11591/ijece.v7i4.pp1824-1832.

Full text
Abstract:
This paper presents the electronic synthesis, VHDL design and implementation on FPGA of turbo decoders for Difference Set Codes (DSC) decoded by the majority logic (ML). The VHDL design is based on the decoding equations that we have simplified, in order to reduce the complexity and is implemented on parallel process to increase the data rate. A co-simulation using the Dsp-Builder tool on a platform designed on Matlab/Simulink, allows the measurement of the performance in terms of BER (Bit Error Rate) as well as the decoder validation. These decoders can be a good choice for future digital transmission chains. For example, for the Turbo decoder based on the product code DSC (21.11)² with a quantization of 5 bits and for one complete iteration, the results show the possibility of integration of our entire turbo decoder on a single chip, with lower latency at 0.23 microseconds and data rate greater than 500 Mb/s.
APA, Harvard, Vancouver, ISO, and other styles
3

Islam, MS, MA Quaium, M. Morshed, and RC Roy. "Hardware implementation issues of turbo decoders." Bangladesh Journal of Scientific and Industrial Research 47, no. 3 (December 21, 2012): 327–32. http://dx.doi.org/10.3329/bjsir.v47i3.13068.

Full text
Abstract:
This paper gives a general overview of the implementation aspects of turbo decoders. Although the parallel architecture of the turbo code is emphasized, the serial concatenated convolutional codes for the turbo decoder are discussed too. Considering the general structure of iterative decoders, the main features of the soft input and soft output algorithm, which are the heart of a turbo decoder, are observed. The efficient parallel architectures of turbo decoders are shown which allow high speed implementation. Apart from these, implementation aspects like quantization issues and stopping rules to increase the throughput as well as an evaluation of the various turbo decoders are discussed. Finally, we suggest a number of solutions to overcome the implementation issues as well as the complexities without affecting the high throughput rate. DOI: http://dx.doi.org/10.3329/bjsir.v47i3.13068 Bangladesh J. Sci. Ind. Res. 47(3), 327-332 2012
APA, Harvard, Vancouver, ISO, and other styles
4

Wangrok Oh and Kyungwhoon Cheun. "Turbo decoder." IEEE Communications Letters 4, no. 8 (August 2000): 255–57. http://dx.doi.org/10.1109/4234.864186.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Maity, Niladri Pratap, and Reshmi Maity. "Low Power Design of near Shannon Limit Coding: Turbo Codes." Advanced Materials Research 433-440 (January 2012): 7213–17. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.7213.

Full text
Abstract:
In this paper secure channel coding schemes based on Turbo Codes are suggested and implemented. The design of encoder using Recursive Systematic Code (RSC) with puncturing techniques is presented. Component decoders are implemented by Log-Maximum-a-Posteriori (Log-MAP) algorithm and thereafter implementation of overall turbo decoder is illustrated in detail. Finally we have investigated low power design technique of the turbo decoder design with variable iteration techniques.
APA, Harvard, Vancouver, ISO, and other styles
6

Lehnigk-Emden, T., U. Wasenmüller, C. Gimmler, and N. Wehn. "Analysis of iteration control for turbo decoders in turbo synchronization applications." Advances in Radio Science 7 (May 18, 2009): 139–44. http://dx.doi.org/10.5194/ars-7-139-2009.

Full text
Abstract:
Abstract. Wireless data transmission results in frequency and phase offsets of the signal in the receiver. In addition, the received symbols are corrupted by noise. Therefore, synchronization and channel coding are vital parts of each receiver in digital communication systems. By combining the phase and frequency synchronization with an advanced iterative channel decoder (inner loop) e.g. turbo codes in an iterative way (outer loop), the communications performance can be further increased. This principle is referred to as turbo synchronization. The energy consumption and the peak throughput of the system depend on the number of iterations for both loops. An advanced iteration control can decrease the mean number of needed iterations by detecting correctly decoded blocks. This leads to a dramatic energy saving or to an increase of throughput. In this paper we present a new stopping criterion for decodable blocks for turbo decoding in interrelation with turbo synchronization. Furthermore the implementation complexity of the turbo decoder is shown on a Xilinx FPGA.
APA, Harvard, Vancouver, ISO, and other styles
7

Salmela, Perttu, Harri Sorokin, and Jarmo Takala. "A Programmable Max-Log-MAP Turbo Decoder Implementation." VLSI Design 2008 (December 22, 2008): 1–17. http://dx.doi.org/10.1155/2008/319095.

Full text
Abstract:
In the advent of very high data rates of the upcoming 3G long-term evolution telecommunication systems, there is a crucial need for efficient and flexible turbo decoder implementations. In this study, a max-log-MAP turbo decoder is implemented as an application-specific instruction-set processor. The processor is accompanied with accelerating computing units, which can be controlled in detail. With a novel memory interface, the dual-port memory for extrinsic information is avoided. As a result, processing one trellis stage with max-log-MAP algorithm takes only 1.02 clock cycles on average, which is comparable to pure hardware decoders. With six turbo iterations and 277 MHz clock frequency 22.7 Mbps, decoding speed is achieved on 130 nm technology.
APA, Harvard, Vancouver, ISO, and other styles
8

MARTINA, MAURIZIO, MARIO NICOLA, and GUIDO MASERA. "VLSI IMPLEMENTATION OF WiMax CONVOLUTIONAL TURBO CODE ENCODER AND DECODER." Journal of Circuits, Systems and Computers 18, no. 03 (May 2009): 535–64. http://dx.doi.org/10.1142/s0218126609005241.

Full text
Abstract:
A VLSI encoder and decoder implementation for the IEEE 802.16 WiMax convolutional turbo code is presented. Architectural choices employed to achieve high throughput, while granting a limited occupation of resources, are addressed both for the encoder and decoder side, including also the subblock interleaving and symbol selection functions specified in the standard. The complete encoder and decoder architectures, implemented on a 0.13 μm standard cell technology, sustain a decoded throughput of more than 90 Mb/s with a 200 MHz clock frequency. The encoder has the complexity of 9.2 kgate of logic and 187.2 kbit of memory, whereas the complete decoder requires 167.7 kgate and 1163 kbit.
APA, Harvard, Vancouver, ISO, and other styles
9

Yang, Le, Tianchun Ye, Bin Wu, and Ruiqi Zhang. "LTE turbo decoder design." Journal of Semiconductors 36, no. 7 (July 2015): 075003. http://dx.doi.org/10.1088/1674-4926/36/7/075003.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Han, Jian Bing, Chen He, and Ran Zhen. "FPGA Implementation of High-Speed Memory Efficient Quasi-Cyclic LDPC Decoder." Applied Mechanics and Materials 380-384 (August 2013): 3328–31. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.3328.

Full text
Abstract:
This paper introduces a new kind of decoder structure for FPGA implementation of high-speed memory efficient quasi-cyclic LDPC (QC-LDPC) decoder. The code structure, algorithm and hardware structure all adopt optimization design. The decoder adopts modified Turbo decoding algorithm and achieves a decoding throughput of 223 Mbps and frame size of 3,200 bits. The Xilinx Virtex-4 chip used by the decoder only takes up 71 KB memory and makes it exceeds other decoders in aspects of throughput and memory for FPGA implementation.
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "Turbo decoder"

1

Allala, Prathyusha. "Genetic Optimization of Turbo Decoder." Ohio University / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1293681661.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Padinjare, Sainath. "VLSI implementation of a turbo encoder/decoder /." Internet access available to MUN users only, 2003. http://collections.mun.ca/u?/theses,162832.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Al-Mohandes, Ibrahim. "Energy-Efficient Turbo Decoder for 3G Wireless Terminals." Thesis, University of Waterloo, 2005. http://hdl.handle.net/10012/838.

Full text
Abstract:
Since its introduction in 1993, the turbo coding error-correction technique has generated a tremendous interest due to its near Shannon-limit performance. Two key innovations of turbo codes are parallel concatenated encoding and iterative decoding. In its IMT-2000 initiative, the International Telecommunication Union (ITU) adopted turbo coding as a channel coding standard for Third-Generation (3G) wireless high-speed (up to 2 Mbps) data services (cdma2000 in North America and W-CDMA in Japan and Europe). For battery-powered hand-held wireless terminals, energy consumption is a major concern. In this thesis, a new design for an energy-efficient turbo decoder that is suitable for 3G wireless high-speed data terminals is proposed. The Log-MAP decoding algorithm is selected for implementation of the constituent Soft-Input/Soft-Output (SISO) decoder; the algorithm is approximated by a fixed-point representation that achieves the best performance/complexity tradeoff. To attain energy reduction, a two-stage design approach is adopted. First, a novel dynamic-iterative technique that is appropriate for both good and poor channel conditions is proposed, and then applied to reduce energy consumption of the turbo decoder. Second, a combination of architectural-level techniques is applied to obtain further energy reduction; these techniques also enhance throughput of the turbo decoder and are area-efficient. The turbo decoder design is coded in the VHDL hardware description language, and then synthesized and mapped to a 0. 18μm CMOS technology using the standard-cell approach. The designed turbo decoder has a maximum data rate of 5 Mb/s (at an upper limit of five iterations) and is 3G-compatible. Results show that the adopted two-stage design approach reduces energy consumption of the turbo decoder by about 65%. A prototype for the new turbo codec (encoder/decoder) system is implemented on a Xilinx XC2V6000 FPGA chip; then the FPGA is tested using the CMC Rapid Prototyping Platform (RPP). The test proves correct functionality of the turbo codec implementation, and hence feasibility of the proposed turbo decoder design.
APA, Harvard, Vancouver, ISO, and other styles
4

Fei, Jia. "On a turbo decoder design for low power dissipation." Thesis, Virginia Tech, 2000. http://hdl.handle.net/10919/34090.

Full text
Abstract:
A new coding scheme called "turbo coding" has generated tremendous interest in channel coding of digital communication systems due to its high error correcting capability. Two key innovations in turbo coding are parallel concatenated encoding and iterative decoding. A soft-in soft-out component decoder can be implemented using the maximum a posteriori (MAP) or the maximum likelihood (ML) decoding algorithm. While the MAP algorithm offers better performance than the ML algorithm, the computation is complex and not suitable for hardware implementation. The log-MAP algorithm, which performs necessary computations in the logarithm domain, greatly reduces hardware complexity. With the proliferation of the battery powered devices, power dissipation, along with speed and area, is a major concern in VLSI design. In this thesis, we investigated a low-power design of a turbo decoder based on the log-MAP algorithm. Our turbo decoder has two component log-MAP decoders, which perform the decoding process alternatively. Two major ideas for low-power design are employment of a variable number of iterations during the decoding process and shutdown of inactive component decoders. The number of iterations during decoding is determined dynamically according to the channel condition to save power. When a component decoder is inactive, the clocks and spurious inputs to the decoder are blocked to reduce power dissipation. We followed the standard cell design approach to design the proposed turbo decoder. The decoder was described in VHDL, and then synthesized to measure the performance of the circuit in area, speed and power. Our decoder achieves good performance in terms of bit error rate. The two proposed methods significantly reduce power dissipation and energy consumption.
Master of Science
APA, Harvard, Vancouver, ISO, and other styles
5

Šedý, Jakub. "Turbo konvoluční a turbo blokové kódy." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-219287.

Full text
Abstract:
The aim is to explain the Turbo convolutional and block turbo codes and decoding the secure message. The practical part focuses on the design of a demonstration program in Matlab. The work is divided into four parts. The first two deal with theoretical analysis of coding and decoding. The third section contains a description created a demonstration program that allows you to navigate the process of encoding and decoding. The fourth is devoted to simulation and performance of turbo codes.
APA, Harvard, Vancouver, ISO, and other styles
6

Lindblom, Johannes. "Turbo Decoding With Early State Decisions." Thesis, Linköping University, Department of Electrical Engineering, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-11694.

Full text
Abstract:

Turbo codes was first presented in 1993 by C. Berrou, A. Glavieux and P. Thitimajshima. Since then this class of error correcting codes has become one of the most popular, because of its good properties. The turbo codes are able to come very close to theoretical limit, the Shannon limit. Turbo codes are for example used in the third generation of mobile phone (3G) and in the standard IEEE 802.16 (WiMAX).

There are some drawbacks with the algorithm for decoding turbo codes. The deocoder uses a Maximum A Posteriori (MAP) algorithm, which is a complex algorith. Because of the use of many variables in the decoder the decoding circuit will consume a lot of power due to memory accesses and internal communication. One way in which this can be reduced is to make early decisions.

In this work I have focused on making early decision of the encoder states. One major part of the work was also to be sure that the expressions were written in a way that as few variables as possible are needed. A termination condition is also introduced. Simulations based on estimations of the number of memory accesses, shows that the number of memory accesses will significantly decrease.

APA, Harvard, Vancouver, ISO, and other styles
7

Ahlqvist, Johan. "Evaluation of the Turbo-decoder Coprocessor on a TMS320C64x Digital Signal Processor." Thesis, Linköpings universitet, Kommunikationssystem, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-71656.

Full text
Abstract:
One technique that is used to reduce the errors brought upon signals, when transmitted over noisy channels, is error control coding. One type of such coding, which has a good performance, is turbo coding. In some of the TMS320C64xTM digital signal processors there is a built in coprocessor that performs turbo decoding. This thesis is performed on the account of Communication Developments, within Saab AB and presents an evaluation of this coprocessor. The evaluation deals with both the memory consumption as well as the data rate. The result is also compared to an implementation of turbo coding that does not use the coprocessor.
En teknik som används för att minska de fel som en signal utsätts för vid transmission över en brusig kanal är felrättande kodning. Ett exempel på sådan kodning som ger ett mycket bra resultat är turbokodning. I några digitalsignalprocessorer, av sorten TMS320C64xTM, finns en inbyggd coprocessor som utför turboavkodning. Denna uppsats är utförd åt Communication Development inom Saab AB och presenterar en utvärdering av denna coprocessor. Utvärderingen avser såväl minnesförbrukning som datatakt och innehåller även en jämförelse med en implementering av turbokodning utan att använda coprocessorn.
APA, Harvard, Vancouver, ISO, and other styles
8

Hess, Jason Richard. "Implementation of a Turbo Decoder on a Configurable Computing Platform." Thesis, Virginia Tech, 1999. http://hdl.handle.net/10919/35131.

Full text
Abstract:
Turbo codes are a new class of codes that can achieve exceptional error performance and energy efficiency at low signal-to-noise ratios. Decoding turbo codes is a complicated procedure that often requires custom hardware if it is to be performed at acceptable speeds. Configurable computing machines are able to provide the performance advantages of custom hardware while maintaining the flexibility of general-purpose microprocessors and DSPs. This thesis presents an implementation of a turbo decoder on an FPGA-based configurable computing platform. Portability and flexibility are emphasized in the implementation so that the decoder can be used as part of a configurable software radio. The system presented performs turbo decoding for a variable block size with a variable number of decoding iterations while using only a single FPGA. When six iterations are performed, the decoder operates at an information bit rate greater than 32 kbps.
Master of Science
APA, Harvard, Vancouver, ISO, and other styles
9

Han, Jong Hun. "Turbo decoder VLSI implementations for multi-standards wireless communication systems." Thesis, University of Edinburgh, 2006. http://hdl.handle.net/1842/14977.

Full text
Abstract:
This thesis presents high performance turbo decoder architecture for VLSI implementation in terms of area, power and critical path delay. A Max-Log-MAP (MLMAP) algorithm is used to implement the turbo decoder with sliding window (SW) method to reduce the latency. Low power and area efficient turbo decoder implementation is achieved by reducing memory blocks required to control the SW method and to store the branch metrics used for computing log-likelihood-ratio (LLR). Retiming and reordering method is applied to implementing the units needed to calculate the LLR and the state metrics, to save hardware costs. A novel method is proposed to achieve high speed turbo decoder implementation for high throughput without significant area and power overheads. The proposed method addresses the inherent critical path delay problem in the state metric computation process by normalising the branch metrics. A two-step soft-output Viterbi algorithm (TSOVA) based turbo decoder is implemented exploiting a novel concept for implementing a traceback algorithm (TBA) to achieve low area and power turbo decoder implementations as compared to the MLMAP turbo decoder without any significant BER performance degradation. Two reconfigurable application specific turbo decoders are implemented to support variable constraint length and binary and duo-binary turbo codes for targeting various wireless communication systems. The reconfigurable turbo decoder architectures are realised by a proposed mapping method applied to the process for computing the state metrics and the LLR values. It is found that radix-4 based turbo decoder architecture can be exploited to implement the reconfigurable turbo decoder for binary and duo-binary turbo codes.
APA, Harvard, Vancouver, ISO, and other styles
10

Hussein, Ahmed Refaey Ahmed. "Universal Decoder for Low Density Parity Check, Turbo and Convolutional Codes." Thesis, Université Laval, 2011. http://www.theses.ulaval.ca/2011/28154/28154.pdf.

Full text
APA, Harvard, Vancouver, ISO, and other styles
More sources

Books on the topic "Turbo decoder"

1

Wong, Cheng-Chi, and Hsie-Chia Chang. Turbo Decoder Architecture for Beyond-4G Applications. New York, NY: Springer New York, 2014. http://dx.doi.org/10.1007/978-1-4614-8310-6.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Wong, Cheng-Chi, and Hsie-Chia Chang. Turbo Decoder Architecture for Beyond-4G Applications. Springer, 2013.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
3

Wong, Cheng-Chi, and Hsie-Chia Chang. Turbo Decoder Architecture for Beyond-4G Applications. Springer London, Limited, 2013.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
4

Wong, Cheng-Chi, and Hsie-Chia Chang. Turbo Decoder Architecture for Beyond-4g Applications. Springer New York, 2016.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
5

Investigation of different constituent encoders in a turbo-code scheme for reduced decoder complexity: Technical report. [Washington, DC: National Aeronautics and Space Administration, 1998.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
6

Abbasfar, Aliazam. Turbo-Like Codes: Design for High Speed Decoding. Springer Netherlands, 2010.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
7

Turbo-like Codes: Design for High Speed Decoding. Springer, 2007.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
8

Abbasfar, Aliazam. Turbo-Like Codes: Design for High Speed Decoding. Springer London, Limited, 2007.

Find full text
APA, Harvard, Vancouver, ISO, and other styles

Book chapters on the topic "Turbo decoder"

1

Wong, Cheng-Chi, and Hsie-Chia Chang. "Conventional Architecture of Turbo Decoder." In Turbo Decoder Architecture for Beyond-4G Applications, 33–51. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-8310-6_2.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Wong, Cheng-Chi, and Hsie-Chia Chang. "Turbo Decoder with Parallel Processing." In Turbo Decoder Architecture for Beyond-4G Applications, 53–68. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-8310-6_3.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Seo, Jonghyun, and Jangmyung Lee. "Low Complexity MAP Algorithm for Turbo Decoder." In Intelligent Robotics and Applications, 77–84. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-40852-6_10.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Zakaria, F. F., P. Ehkan, M. N. M. Warip, and M. Elshaikh. "Parallel ASIP Based Design of Turbo Decoder." In Lecture Notes in Electrical Engineering, 481–89. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-07674-4_47.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Beerel, Peter A. "Implementation Issues: A Turbo Decoder Design Case Study." In Iterative Detection, 315–40. Boston, MA: Springer US, 2001. http://dx.doi.org/10.1007/978-1-4615-1699-6_6.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Nair, Gana C., B. Yamuna, Karthi Balasubramanian, and Deepak Mishra. "Hardware Design of a Turbo Product Code Decoder." In Lecture Notes in Electrical Engineering, 249–55. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-33-4866-0_31.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Shivanna, Gautham, B. Yamuna, Karthi Balasubramanian, and Deepak Mishra. "Design of High-Speed Turbo Product Code Decoder." In Lecture Notes in Electrical Engineering, 175–86. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-33-6977-1_15.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Wong, Cheng-Chi, and Hsie-Chia Chang. "Introduction." In Turbo Decoder Architecture for Beyond-4G Applications, 1–31. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-8310-6_1.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Wong, Cheng-Chi, and Hsie-Chia Chang. "Low-Complexity Solution for Highly Parallel Architecture." In Turbo Decoder Architecture for Beyond-4G Applications, 69–79. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-8310-6_4.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Wong, Cheng-Chi, and Hsie-Chia Chang. "High-Efficiency Solution for Highly Parallel Architecture." In Turbo Decoder Architecture for Beyond-4G Applications, 81–96. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-8310-6_5.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "Turbo decoder"

1

Kai Niu and Wei Ling Wu. "Companding turbo decoder." In 2003 IEEE 58th Vehicular Technology Conference. VTC 2003-Fall (IEEE Cat. No.03CH37484). IEEE, 2003. http://dx.doi.org/10.1109/vetecf.2003.1285959.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Kaza and Chakrabarti. "Energy-efficient turbo decoder." In IEEE International Conference on Acoustics Speech and Signal Processing ICASSP-02. IEEE, 2002. http://dx.doi.org/10.1109/icassp.2002.1005341.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Kaza, Jagadeesh, and Chaitali Chakrabarti. "Energy-efficient turbo decoder." In Proceedings of ICASSP '02. IEEE, 2002. http://dx.doi.org/10.1109/icassp.2002.5745303.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Jiang, Yihan, Sreeram Kannan, Hyeji Kim, Sewoong Oh, Himanshu Asnani, and Pramod Viswanath. "DEEPTURBO: Deep Turbo Decoder." In 2019 IEEE 20th International Workshop on Signal Processing Advances in Wireless Communications (SPAWC). IEEE, 2019. http://dx.doi.org/10.1109/spawc.2019.8815400.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Jiang, Xiaobo, Jie Chen, and Yulin Qiu. "A model for turbo decoder." In 2004 9th IEEE Singapore International Conference on Communication Systems (ICCS). IEEE, 2004. http://dx.doi.org/10.1109/iccs.2004.1359422.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Choi, Jaesung, and Jeong Woo Lee. "Study on High Throughput Turbo Decoder." In 2011 IEEE Vehicular Technology Conference (VTC 2011-Spring). IEEE, 2011. http://dx.doi.org/10.1109/vetecs.2011.5956697.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Shaker, Sherif Welsen. "DVB-RCS: Efficiently quantized turbo decoder." In 2014 16th International Conference on Advanced Communication Technology (ICACT). Global IT Research Institute (GIRI), 2014. http://dx.doi.org/10.1109/icact.2014.6779202.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Loo, K. K. "High performance parallelised 3GPP turbo decoder." In 5th European Personal Mobile Communications Conference 2003. IEE, 2003. http://dx.doi.org/10.1049/cp:20030273.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Deetzen, Neele, and Werner Henkel. "Decoder Scheduling of Hybrid Turbo Codes." In 2006 IEEE International Symposium on Information Theory. IEEE, 2006. http://dx.doi.org/10.1109/isit.2006.261968.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Yimin Wei, Tao Yang, and Yi Yao. "New stopping criteria for turbo decoder." In 2011 Second International Conference on Mechanic Automation and Control Engineering (MACE). IEEE, 2011. http://dx.doi.org/10.1109/mace.2011.5987212.

Full text
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic 'Turbo decoder' for particular source types:
Journal articles Dissertations / Theses
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography