Log in

Relevant bibliographies by topics / Turbo decoder

Contents

Journal articles
Dissertations / Theses
Books
Book chapters
Conference papers

Academic literature on the topic 'Turbo decoder'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 July 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'Turbo decoder.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "Turbo decoder"

1

Shafieipour, Mohammad, Heng-Siong Lim, and Teong-Chee Chuah. "Decoding of Turbo Codes in Symmetric Alpha-Stable Noise." ISRN Signal Processing 2011 (March 29, 2011): 1–7. http://dx.doi.org/10.5402/2011/683972.

Full text

Abstract:

This paper investigates the decoding of turbo codes in impulsive symmetric α-stable (SαS) noise. Due to the nonexistence of a closed-form expression for the probability density function (pdf) of α-stable processes, numerical-based SαS pdf is used to derive branch transition probability (btp) for the maximum a posteriori turbo decoder. Results show that in Gaussian noise, the turbo decoder achieves similar performance using both the conventional and the proposed btps, but in impulsive channels, the turbo decoder with the proposed btp substantially outperforms the turbo decoder utilizing the con

APA, Harvard, Vancouver, ISO, and other styles

2

Boudaoud, A., M. El Haroussi, and E. Abdelmounim. "VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based on Majority Logic Codes." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 4 (2017): 1824. http://dx.doi.org/10.11591/ijece.v7i4.pp1824-1832.

Full text

Abstract:

This paper presents the electronic synthesis, VHDL design and implementation on FPGA of turbo decoders for Difference Set Codes (DSC) decoded by the majority logic (ML). The VHDL design is based on the decoding equations that we have simplified, in order to reduce the complexity and is implemented on parallel process to increase the data rate. A co-simulation using the Dsp-Builder tool on a platform designed on Matlab/Simulink, allows the measurement of the performance in terms of BER (Bit Error Rate) as well as the decoder validation. These decoders can be a good choice for future digital tra

APA, Harvard, Vancouver, ISO, and other styles

3

A., Boudaoud, El Haroussi M., and Abdelmounim E. "VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based on Majority Logic Codes." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 4 (2017): 1824–32. https://doi.org/10.11591/ijece.v7i4.pp1824-1832.

Full text

Abstract:

This paper presents the electronic synthesis, VHDL design and implementation on FPGA of turbo decoders for Difference Set Codes (DSC) decoded by the majority logic (ML). The VHDL design is based on the decoding Equations that we have simplified, in order to reduce the complexity and is implemented on parallel process to increase the data rate. A co-simulation using the Dsp-Builder tool on a platform designed on Matlab/Simulink, allows the measurement of the performance in terms of BER (Bit Error Rate) as well as the decoder validation. These decoders can be a good choice for future digital tra

APA, Harvard, Vancouver, ISO, and other styles

4

Krishna, T. Rama, T. Krishna Murthy, N. Vilasrao Sarode, P. Srilakshmi, and V. Geetha Sri. "Verilog HDL using LTE Implementation MAP Algorithm." International Journal of Innovative Research in Computer Science and Technology 10, no. 2 (2022): 611–14. http://dx.doi.org/10.55524/ijircst.2022.10.2.115.

Full text

Abstract:

In many communication systems, turbo coding Techniques for Encoding and Decoding are employed to repair errors. As compared to other error correction codes, turbo codes provide great error correcting capabilities. For the implementation of the Turbo decoder, a Very Large Scale Integration (VLSI) architecture is suggested in this study. The Maximum-a-Posteriori (MAP) algorithm is employed at the decoder side, where soft-in-soft-out decoders, interleaves, and deinterleavers are all used. The usage of the MAP algorithm reduces the quantity of iterations necessary to decode the information bits be

APA, Harvard, Vancouver, ISO, and other styles

5

Islam, MS, MA Quaium, M. Morshed, and RC Roy. "Hardware implementation issues of turbo decoders." Bangladesh Journal of Scientific and Industrial Research 47, no. 3 (2012): 327–32. http://dx.doi.org/10.3329/bjsir.v47i3.13068.

Full text

Abstract:

This paper gives a general overview of the implementation aspects of turbo decoders. Although the parallel architecture of the turbo code is emphasized, the serial concatenated convolutional codes for the turbo decoder are discussed too. Considering the general structure of iterative decoders, the main features of the soft input and soft output algorithm, which are the heart of a turbo decoder, are observed. The efficient parallel architectures of turbo decoders are shown which allow high speed implementation. Apart from these, implementation aspects like quantization issues and stopping rules

APA, Harvard, Vancouver, ISO, and other styles

6

Maity, Niladri Pratap, and Reshmi Maity. "Low Power Design of near Shannon Limit Coding: Turbo Codes." Advanced Materials Research 433-440 (January 2012): 7213–17. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.7213.

Full text

Abstract:

In this paper secure channel coding schemes based on Turbo Codes are suggested and implemented. The design of encoder using Recursive Systematic Code (RSC) with puncturing techniques is presented. Component decoders are implemented by Log-Maximum-a-Posteriori (Log-MAP) algorithm and thereafter implementation of overall turbo decoder is illustrated in detail. Finally we have investigated low power design technique of the turbo decoder design with variable iteration techniques.

APA, Harvard, Vancouver, ISO, and other styles

7

Devrari, Aakanksha, and Adesh Kumar. "Turbo encoder and decoder chip design and FPGA device analysis for communication system." International Journal of Reconfigurable and Embedded Systems (IJRES) 12, no. 2 (2023): 174. http://dx.doi.org/10.11591/ijres.v12.i2.pp174-185.

Full text

Abstract:

<p>Turbo codes are error-correcting codes with performance that is close to the Shannon theoretical limit (SHA). The motivation for using turbo codes is that the codes are an appealing mix of a random appearance on the channel and a physically realizable decoding structure. The communication systems have the problem of latency, fast switching, and reliable data transfer. The objective of the research paper is to design and turbo encoder and decoder hardware chip and analyze its performance. Two convolutional codes are concatenated concurrently and detached by an interleaver or permuter i

APA, Harvard, Vancouver, ISO, and other styles

8

Aakanksha, Devrari, and Kumar Adesh. "Turbo encoder and decoder chip design and FPGA device analysis for communication system." International Journal of Reconfigurable and Embedded Systems (IJRES) 12, no. 2 (2023): 174–85. https://doi.org/10.11591/ijres.v12.i2.pp174-185.

Full text

Abstract:

Turbo codes are error-correcting codes with performance that is close to the Shannon theoretical limit (SHA). The motivation for using turbo codes is that the codes are an appealing mix of a random appearance on the channel and a physically realizable decoding structure. The communication systems have the problem of latency, fast switching, and reliable data transfer. The objective of the research paper is to design and turbo encoder and decoder hardware chip and analyze its performance. Two convolutional codes are concatenated concurrently and detached by an interleaver or permuter in the tur

APA, Harvard, Vancouver, ISO, and other styles

9

Wangrok Oh and Kyungwhoon Cheun. "Turbo decoder." IEEE Communications Letters 4, no. 8 (2000): 255–57. http://dx.doi.org/10.1109/4234.864186.

Full text

APA, Harvard, Vancouver, ISO, and other styles

10

V, S. Sneha, and Joe Nithin. "Implementation of Turbo Coder Using Verilog HDL for LTE." International Journal of Innovative Science and Research Technology 7, no. 7 (2022): 380–83. https://doi.org/10.5281/zenodo.6930806.

Full text

Abstract:

In many communication systems, turbo codesare employed to repair errors. Turbo codes demonstrate high error correction when compared to other error correction methods. A Very Large Scale Integration is suggested in this study. VLSI architecture for the Turbo encoder implementation, Interleaves and de interleaves, and soft-in-soft-out decoders are employed. This study employs a technique that for the encoder portion, includes two recursive systematic convolutional (RSC) encoders , a Block interleaver and the decoder part involve Soft Output Virtebi Algorithm(SOVA) decoder. Aconvolutional code i

APA, Harvard, Vancouver, ISO, and other styles

More sources

Dissertations / Theses on the topic "Turbo decoder"

1

Allala, Prathyusha. "Genetic Optimization of Turbo Decoder." Ohio University / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1293681661.

Full text

APA, Harvard, Vancouver, ISO, and other styles

2

Padinjare, Sainath. "VLSI implementation of a turbo encoder/decoder /." Internet access available to MUN users only, 2003. http://collections.mun.ca/u?/theses,162832.

Full text

APA, Harvard, Vancouver, ISO, and other styles

3

Al-Mohandes, Ibrahim. "Energy-Efficient Turbo Decoder for 3G Wireless Terminals." Thesis, University of Waterloo, 2005. http://hdl.handle.net/10012/838.

Full text

Abstract:

Since its introduction in 1993, the turbo coding error-correction technique has generated a tremendous interest due to its near Shannon-limit performance. Two key innovations of turbo codes are parallel concatenated encoding and iterative decoding. In its IMT-2000 initiative, the International Telecommunication Union (ITU) adopted turbo coding as a channel coding standard for Third-Generation (3G) wireless high-speed (up to 2 Mbps) data services (cdma2000 in North America and W-CDMA in Japan and Europe). For battery-powered hand-held wireless terminals, energy consumption is a major

APA, Harvard, Vancouver, ISO, and other styles

4

Fei, Jia. "On a turbo decoder design for low power dissipation." Thesis, Virginia Tech, 2000. http://hdl.handle.net/10919/34090.

Full text

Abstract:

A new coding scheme called "turbo coding" has generated tremendous interest in channel coding of digital communication systems due to its high error correcting capability. Two key innovations in turbo coding are parallel concatenated encoding and iterative decoding. A soft-in soft-out component decoder can be implemented using the maximum a posteriori (MAP) or the maximum likelihood (ML) decoding algorithm. While the MAP algorithm offers better performance than the ML algorithm, the computation is complex and not suitable for hardware implementation. The log-MAP algorithm, which performs n

APA, Harvard, Vancouver, ISO, and other styles

5

Šedý, Jakub. "Turbo konvoluční a turbo blokové kódy." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-219287.

Full text

Abstract:

The aim is to explain the Turbo convolutional and block turbo codes and decoding the secure message. The practical part focuses on the design of a demonstration program in Matlab. The work is divided into four parts. The first two deal with theoretical analysis of coding and decoding. The third section contains a description created a demonstration program that allows you to navigate the process of encoding and decoding. The fourth is devoted to simulation and performance of turbo codes.

APA, Harvard, Vancouver, ISO, and other styles

6

Lindblom, Johannes. "Turbo Decoding With Early State Decisions." Thesis, Linköping University, Department of Electrical Engineering, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-11694.

Full text

Abstract:

<p>Turbo codes was first presented in 1993 by C. Berrou, A. Glavieux and P. Thitimajshima. Since then this class of error correcting codes has become one of the most popular, because of its good properties. The turbo codes are able to come very close to theoretical limit, the Shannon limit. Turbo codes are for example used in the third generation of mobile phone (3G) and in the standard IEEE 802.16 (WiMAX).</p><p>There are some drawbacks with the algorithm for decoding turbo codes. The deocoder uses a Maximum A Posteriori (MAP) algorithm, which is a complex algorith. Because of the use of many

APA, Harvard, Vancouver, ISO, and other styles

7

Ahlqvist, Johan. "Evaluation of the Turbo-decoder Coprocessor on a TMS320C64x Digital Signal Processor." Thesis, Linköpings universitet, Kommunikationssystem, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-71656.

Full text

Abstract:

One technique that is used to reduce the errors brought upon signals, when transmitted over noisy channels, is error control coding. One type of such coding, which has a good performance, is turbo coding. In some of the TMS320C64xTM digital signal processors there is a built in coprocessor that performs turbo decoding. This thesis is performed on the account of Communication Developments, within Saab AB and presents an evaluation of this coprocessor. The evaluation deals with both the memory consumption as well as the data rate. The result is also compared to an implementation of turbo coding

APA, Harvard, Vancouver, ISO, and other styles

8

Hess, Jason Richard. "Implementation of a Turbo Decoder on a Configurable Computing Platform." Thesis, Virginia Tech, 1999. http://hdl.handle.net/10919/35131.

Full text

Abstract:

Turbo codes are a new class of codes that can achieve exceptional error performance and energy efficiency at low signal-to-noise ratios. Decoding turbo codes is a complicated procedure that often requires custom hardware if it is to be performed at acceptable speeds. Configurable computing machines are able to provide the performance advantages of custom hardware while maintaining the flexibility of general-purpose microprocessors and DSPs. This thesis presents an implementation of a turbo decoder on an FPGA-based configurable computing platform. Portability and flexibility are emphasize

APA, Harvard, Vancouver, ISO, and other styles

9

Han, Jong Hun. "Turbo decoder VLSI implementations for multi-standards wireless communication systems." Thesis, University of Edinburgh, 2006. http://hdl.handle.net/1842/14977.

Full text

Abstract:

This thesis presents high performance turbo decoder architecture for VLSI implementation in terms of area, power and critical path delay. A Max-Log-MAP (MLMAP) algorithm is used to implement the turbo decoder with sliding window (SW) method to reduce the latency. Low power and area efficient turbo decoder implementation is achieved by reducing memory blocks required to control the SW method and to store the branch metrics used for computing log-likelihood-ratio (LLR). Retiming and reordering method is applied to implementing the units needed to calculate the LLR and the state metrics, to save

APA, Harvard, Vancouver, ISO, and other styles

10

Hussein, Ahmed Refaey Ahmed. "Universal Decoder for Low Density Parity Check, Turbo and Convolutional Codes." Thesis, Université Laval, 2011. http://www.theses.ulaval.ca/2011/28154/28154.pdf.

Full text

APA, Harvard, Vancouver, ISO, and other styles

More sources

Books on the topic "Turbo decoder"

1

Wong, Cheng-Chi, and Hsie-Chia Chang. Turbo Decoder Architecture for Beyond-4G Applications. Springer New York, 2014. http://dx.doi.org/10.1007/978-1-4614-8310-6.

Full text

APA, Harvard, Vancouver, ISO, and other styles

2

Wong, Cheng-Chi, and Hsie-Chia Chang. Turbo Decoder Architecture for Beyond-4G Applications. Springer, 2013.

Find full text

APA, Harvard, Vancouver, ISO, and other styles

3

Wong, Cheng-Chi, and Hsie-Chia Chang. Turbo Decoder Architecture for Beyond-4g Applications. Springer New York, 2016.

Find full text

APA, Harvard, Vancouver, ISO, and other styles

4

Wong, Cheng-Chi, and Hsie-Chia Chang. Turbo Decoder Architecture for Beyond-4G Applications. Springer London, Limited, 2013.

Find full text

APA, Harvard, Vancouver, ISO, and other styles

5

Investigation of different constituent encoders in a turbo-code scheme for reduced decoder complexity: Technical report. National Aeronautics and Space Administration, 1998.

Find full text

APA, Harvard, Vancouver, ISO, and other styles

6

Turbo-like Codes: Design for High Speed Decoding. Springer, 2007.

Find full text

APA, Harvard, Vancouver, ISO, and other styles

7

Abbasfar, Aliazam. Turbo-Like Codes: Design for High Speed Decoding. Springer Netherlands, 2010.

Find full text

APA, Harvard, Vancouver, ISO, and other styles

8

Abbasfar, Aliazam. Turbo-Like Codes: Design for High Speed Decoding. Springer London, Limited, 2007.

Find full text

APA, Harvard, Vancouver, ISO, and other styles

Book chapters on the topic "Turbo decoder"

1

Wong, Cheng-Chi, and Hsie-Chia Chang. "Conventional Architecture of Turbo Decoder." In Turbo Decoder Architecture for Beyond-4G Applications. Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-8310-6_2.

Full text

APA, Harvard, Vancouver, ISO, and other styles

2

Wong, Cheng-Chi, and Hsie-Chia Chang. "Turbo Decoder with Parallel Processing." In Turbo Decoder Architecture for Beyond-4G Applications. Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-8310-6_3.

Full text

APA, Harvard, Vancouver, ISO, and other styles

3

Seo, Jonghyun, and Jangmyung Lee. "Low Complexity MAP Algorithm for Turbo Decoder." In Intelligent Robotics and Applications. Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-40852-6_10.

Full text

APA, Harvard, Vancouver, ISO, and other styles

4

Zakaria, F. F., P. Ehkan, M. N. M. Warip, and M. Elshaikh. "Parallel ASIP Based Design of Turbo Decoder." In Lecture Notes in Electrical Engineering. Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-07674-4_47.

Full text

APA, Harvard, Vancouver, ISO, and other styles

5

Wong, Cheng-Chi, and Hsie-Chia Chang. "Introduction." In Turbo Decoder Architecture for Beyond-4G Applications. Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-8310-6_1.

Full text

APA, Harvard, Vancouver, ISO, and other styles

6

Wong, Cheng-Chi, and Hsie-Chia Chang. "Low-Complexity Solution for Highly Parallel Architecture." In Turbo Decoder Architecture for Beyond-4G Applications. Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-8310-6_4.

Full text

APA, Harvard, Vancouver, ISO, and other styles

7

Wong, Cheng-Chi, and Hsie-Chia Chang. "High-Efficiency Solution for Highly Parallel Architecture." In Turbo Decoder Architecture for Beyond-4G Applications. Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-8310-6_5.

Full text

APA, Harvard, Vancouver, ISO, and other styles

8

Beerel, Peter A. "Implementation Issues: A Turbo Decoder Design Case Study." In Iterative Detection. Springer US, 2001. http://dx.doi.org/10.1007/978-1-4615-1699-6_6.

Full text

APA, Harvard, Vancouver, ISO, and other styles

9

Nair, Gana C., B. Yamuna, Karthi Balasubramanian, and Deepak Mishra. "Hardware Design of a Turbo Product Code Decoder." In Lecture Notes in Electrical Engineering. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-33-4866-0_31.

Full text

APA, Harvard, Vancouver, ISO, and other styles

10

Shivanna, Gautham, B. Yamuna, Karthi Balasubramanian, and Deepak Mishra. "Design of High-Speed Turbo Product Code Decoder." In Lecture Notes in Electrical Engineering. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-33-6977-1_15.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "Turbo decoder"

1

Zhang, Yining, Zhe Zheng, and Yang Zhou. "Design of an Efficient Segmented Parallel Turbo Decoder." In 2025 8th World Conference on Computing and Communication Technologies (WCCCT). IEEE, 2025. https://doi.org/10.1109/wccct65447.2025.11028014.

Full text

APA, Harvard, Vancouver, ISO, and other styles

2

Zhou, Tong, Zhen Wang, Jiacheng Zhang, and Jun Zou. "Implementation of Turbo Product Code Decoder with High Throughput." In 2024 7th International Conference on Information Communication and Signal Processing (ICICSP). IEEE, 2024. https://doi.org/10.1109/icicsp62589.2024.10809309.

Full text

APA, Harvard, Vancouver, ISO, and other styles

3

Kai Niu and Wei Ling Wu. "Companding turbo decoder." In 2003 IEEE 58th Vehicular Technology Conference. VTC 2003-Fall (IEEE Cat. No.03CH37484). IEEE, 2003. http://dx.doi.org/10.1109/vetecf.2003.1285959.

Full text

APA, Harvard, Vancouver, ISO, and other styles

4

Kaza and Chakrabarti. "Energy-efficient turbo decoder." In IEEE International Conference on Acoustics Speech and Signal Processing ICASSP-02. IEEE, 2002. http://dx.doi.org/10.1109/icassp.2002.1005341.

Full text

APA, Harvard, Vancouver, ISO, and other styles

5

Kaza, Jagadeesh, and Chaitali Chakrabarti. "Energy-efficient turbo decoder." In Proceedings of ICASSP '02. IEEE, 2002. http://dx.doi.org/10.1109/icassp.2002.5745303.

Full text

APA, Harvard, Vancouver, ISO, and other styles

6

Jiang, Yihan, Sreeram Kannan, Hyeji Kim, Sewoong Oh, Himanshu Asnani, and Pramod Viswanath. "DEEPTURBO: Deep Turbo Decoder." In 2019 IEEE 20th International Workshop on Signal Processing Advances in Wireless Communications (SPAWC). IEEE, 2019. http://dx.doi.org/10.1109/spawc.2019.8815400.

Full text

APA, Harvard, Vancouver, ISO, and other styles

7

Jiang, Xiaobo, Jie Chen, and Yulin Qiu. "A model for turbo decoder." In 2004 9th IEEE Singapore International Conference on Communication Systems (ICCS). IEEE, 2004. http://dx.doi.org/10.1109/iccs.2004.1359422.

Full text

APA, Harvard, Vancouver, ISO, and other styles

8

Choi, Jaesung, and Jeong Woo Lee. "Study on High Throughput Turbo Decoder." In 2011 IEEE Vehicular Technology Conference (VTC 2011-Spring). IEEE, 2011. http://dx.doi.org/10.1109/vetecs.2011.5956697.

Full text

APA, Harvard, Vancouver, ISO, and other styles

9

Shaker, Sherif Welsen. "DVB-RCS: Efficiently quantized turbo decoder." In 2014 16th International Conference on Advanced Communication Technology (ICACT). Global IT Research Institute (GIRI), 2014. http://dx.doi.org/10.1109/icact.2014.6779202.

Full text

APA, Harvard, Vancouver, ISO, and other styles

10

Loo, K. K. "High performance parallelised 3GPP turbo decoder." In 5th European Personal Mobile Communications Conference 2003. IEE, 2003. http://dx.doi.org/10.1049/cp:20030273.

Full text

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!