Relevant bibliographies by topics / Verilog

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Verilog'

Author: Grafiati
Published: 4 June 2021
Last updated: 25 July 2025

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Journal articles on the topic "Verilog"

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Lööw, Andreas. "The Simulation Semantics of Synthesisable Verilog." Proceedings of the ACM on Programming Languages 9, OOPSLA1 (2025): 1295–320. https://doi.org/10.1145/3720484.

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Despite numerous previous formalisation projects targeting Verilog, the semantics of Verilog defined by the Verilog standard -- Verilog's simulation semantics -- has thus far eluded definitive mathematical formalisation. Previous projects on formalising the semantics have made good progress but no previous project provides a formalisation that can be used to execute or formally reason about real-world hardware designs. In this paper, we show that the reason for this is that the Verilog standard is inconsistent both with Verilog practice and itself. We pinpoint a series of problems in the Veril
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Chen, Qinlin, Nairen Zhang, Jinpeng Wang, et al. "The Essence of Verilog: A Tractable and Tested Operational Semantics for Verilog." Proceedings of the ACM on Programming Languages 7, OOPSLA2 (2023): 234–63. http://dx.doi.org/10.1145/3622805.

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With the increasing need to apply modern software techniques to hardware design, Verilog, the most popular Hardware Description Language (HDL), plays an infrastructure role. However, Verilog has several semantic pitfalls that often confuse software and hardware developers. Although prior research on formal semantics for Verilog exists, it is not comprehensive and has not fully addressed these issues. In this work, we present a novel scheme inspired by previous work on defining core languages for software languages like JavaScript and Python. Specifically, we define the formal semantics of Veri
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Blair, G. M. "Verilog: accelerating digital design." Electronics & Communication Engineering Journal 9, no. 2 (1997): 68–72. http://dx.doi.org/10.1049/ecej:19970203.

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Kuthe, Pascal, Markus Muller, and Michael Schroter. "VerilogAE: An Open Source Verilog-A Compiler for Compact Model Parameter Extraction." IEEE Journal of the Electron Devices Society 8 (2020): 1416–23. http://dx.doi.org/10.1109/jeds.2020.3023165.

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Koti, Mr Manjunath, and Dr Basavaraj I. Neelgar. "CAN Tx Frame Implementation using Verilog." Journal of University of Shanghai for Science and Technology 23, no. 07 (2021): 1303–13. http://dx.doi.org/10.51201/jusst/21/07311.

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This article discusses the concept of CAN protocol and its implementation in verilog language. Initially the CAN protocol description is given in brief with the block diagram, later its design, implementation in verilog code is presented. The CAN transmission (Tx) data Frame is realized using verilog code, this is achieved by defining individual sub-blocks verilog codes and combining these to get the CAN transmission of data frame. In the year 1986, CAN data link layer protocol was introduced in SAE conference. In 1993, CAN protocol and high speed physical layer were internationally accredited
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DHARMENDRA, SINGH, SONI UPENDRA, SHOBHANI KARAN, KARKASHE YASH, LIMJE SHUBHAM, and NAYAK AAYUSH. "VERILOG BASED UART SYSTEM DESIGN." i-manager’s Journal on Embedded Systems 6, no. 2 (2018): 34. http://dx.doi.org/10.26634/jes.6.2.14057.

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PEISCHL, BERNHARD, NAVEED RIAZ, and FRANZ WOTAWA. "AUTOMATED DEBUGGING OF VERILOG DESIGNS." International Journal of Software Engineering and Knowledge Engineering 22, no. 05 (2012): 695–723. http://dx.doi.org/10.1142/s0218194012500209.

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In this article we report on novel insights in model-based software debugging of hardware description languages (HDLs). Today's simulation driven working process emphasizes the need for exploiting test suites not only for detecting but also for localizing the root cause of misbehavior. We discuss the modeling approaches for the various artifacts of the Verilog hardware description language (blocking and non-blocking statements, expressions, execution ordering) and present a novel model incorporating test suites. The evaluation of our approach on the well-known ISCAS89 benchmarks concerning sin
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Umidjon, Zaripovich Narziyev. "VERILOG DASTURLASH TILI YORDAMIDA DASTURLASH." GOLDEN BRAIN 1, no. 16 (2023): 9–14. https://doi.org/10.5281/zenodo.8043911.

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<em>Maqolada Quartus II muhitida Verilog HDL dasturlash tili yordamida mantiqiy qurilmalarni dasturlash va boshqarish usullari haqida fikr yuritiladi. Qurilma sifatida Altera Cyclone III 3C16 FPGA ni tanlaymiz. Qurilmaning pinlari va portlarini dastur o&lsquo;zgaruvchilariga ulash orqali ularga uzatiluvchi signallarni o&lsquo;zgartirish va boshqarish usullari yoritiladi.</em>
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Wang, Chao, Yicong Shao, Jiajie Huang, et al. "V2Va +: An Efficient SystemVerilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation." IEEE Open Journal of Circuits and Systems 5 (2024): 387–97. https://doi.org/10.1109/ojcas.2024.3451530.

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Ferrari, F. "Verilog quickstart! a practical guide to simulation and synthesis in verilog, 2nd ed. [Book Review]." IEEE Circuits and Devices Magazine 17, no. 2 (2001): 49–50. http://dx.doi.org/10.1109/mcd.2001.920884.

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Dissertations / Theses on the topic "Verilog"

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Li, Lijun. "Optimization techniques for distributed Verilog simulation." Thesis, McGill University, 2008. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=21936.

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Moore's Law states that computational power will roughly double every 18 months. To the semiconductor designer, this means the never-ending challenge of bringing increasingly larger and more complex ICs (Integrated Circuits) to market. It is well known that the principle bottleneck in circuit design is simulation. Uniprocessor simulators may not be able to keep up with increased demands on them for both speed and memory. This thesis has three main contributions. The first contribution is a distributed Verilog simulation environment which can be executed on a cluster of workstations using a m
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Pace, Gordon G. "Hardware design based on Verilog HDL." Thesis, University of Oxford, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.298555.

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Kononov, Ekaterina (Ekaterina R. ). "Modeling photonic links in Verilog-A." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/85432.

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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (pages 59-60).<br>Integrated photonic links are a promising emerging technology that can relieve the interconnect bottleneck in core-to-core and core-to-memory communications of modern processors. Developing and optimizing photonic link systems requires simulation of integrated photonic devices side-by-side with electronic devices at the device, circuit, and system level. In previous efforts to s
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Skärpe, Anders. "Implementation of an SDR in Verilog." Thesis, Linköpings universitet, Kommunikationssystem, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-132325.

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This report presents an implementation of the software part in a software definedradio. The radio is not entirely implemented in software and therefore there arecertain limitations on the received signal. The parts implemented are oscillator,decimation filter, carrier synchronization, time synchronization, package detection,and demodulation. Different algorithms were tested for the different partsto measure the power consumption. To understand how the number of bits usedto represent the signal affects the power consumption, the number of bits wasreduced from 20 bits to 10 bits. This reduction
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Dirsė, Žygimantas. "Verilog kalbos sintezuojamų kostrukcijų atvaizdavimas SystemC kalboje." Master's thesis, Lithuanian Academic Libraries Network (LABT), 2005. http://vddb.library.lt/obj/LT-eLABa-0001:E.02~2005~D_20050524_183745-16346.

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This master work of the main subject: Developing and analysis of peripheral serial interface microcontroller RISC8 that is similar to PIC 16C57, goes about all phases of developing microcircuits. There are analyzed ways of the developing system on chip, described hardware description languages. The first phase is to develop and model a code with one of HDL (hardware description languages) like a Verilog. For that reason are used such developing tools as Cadence LDV-5.1, that is used for compiling, elaborating and simulating of the design with graphical interface. The second phase - synthesis i
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Huang, Hai 1974. "A partitioning framework for distributed verilog simulation /." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=80291.

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The HDL (Hardware Description Language) helps designers of modern digital systems to compete with the increasing size and complexity of VLSI circuits. Simulation is usually used for verification in the design process, which tends to be a bottleneck. Distributed simulation on a network of workstations tries to provide a cost-effective solution. The partitioning of the circuit is a critical factor to the performance of the distributed simulation.<br>This study presents the design and implementation of a partitioning framework which is incorporated into the DVS (Distribute Verilog Simulato
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Pekofsky, Gregory. "GCS : a framework for distributed verilog simulation." Thesis, McGill University, 2005. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=82404.

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The verification of VLSI circuits, which are ever increasing in size and complexity, is bottlenecked during simulation within the circuit design process. Distributed simulation on a cluster of workstations or a shared memory multiple processor computer attempts a cost-effective solution. The key factor in performance of these simulations is the development of distributed simulation algorithms that make use of the circuits' underlying properties.<br>This study presents the design and implementation of a distributed simulation framework to better produce and test simulation algorithms. Th
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Feng, Zhiming Niu Guofu. "Compact modeling of SiGe HBTs using VERILOG-A." Auburn, Ala., 2006. http://repo.lib.auburn.edu/2006%20Summer/Theses/FENG_ZHIMING_19.pdf.

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Rangoonwala, Sakina. "A Verilog 8051 Soft Core for FPGA Applications." Thesis, University of North Texas, 2009. https://digital.library.unt.edu/ark:/67531/metadc11013/.

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The objective of this thesis was to develop an 8051 microcontroller soft core in the Verilog hardware description language (HDL). Each functional unit of the 8051 microcontroller was developed as a separate module, and tested for functionality using the open-source VHDL Dalton model as benchmark. These modules were then integrated to operate as concurrent processes in the 8051 soft core. The Verilog 8051 soft core was then synthesized in Quartus® II simulation and synthesis environment (Altera Corp., San Jose, CA, www.altera.com) and yielded the expected behavioral response to test programs w
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Rangoonwala, Sakina Kougianos Elias. "A Verilog 8051 soft core for FPGA applications." [Denton, Tex.] : University of North Texas, 2009. http://digital.library.unt.edu/permalink/meta-dc-11013.

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Books on the topic "Verilog"

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Sutherland, Stuart. Verilog — 2001. Springer US, 2002. http://dx.doi.org/10.1007/978-1-4615-1713-9.

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M, Lee James. Verilog Quickstart. Kluwer Academic, 1997.

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Lee, James M. Verilog® Quickstart. Springer US, 1997. http://dx.doi.org/10.1007/978-1-4615-6113-2.

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Lee, James M. Verilog® Quickstart. Springer US, 1997.

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Sutherland, Stuart, and Don Mills. Verilog and SystemVerilog Gotchas. Springer US, 2007. http://dx.doi.org/10.1007/978-0-387-71715-9.

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Padmanabhan, T. R., and B. Bala Tripura Sundari. Design Through Verilog HDL. John Wiley & Sons, Inc., 2003. http://dx.doi.org/10.1002/0471723002.

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Cavanagh, Joseph. Verilog HDL Design Examples. CRC Press, 2017. http://dx.doi.org/10.1201/b22315.

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Sutherland, Stuart. The Verilog PLI Handbook. Springer US, 1999. http://dx.doi.org/10.1007/978-1-4615-5017-4.

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Mittra, Swapnajit. Principles of Verilog PLI. Springer US, 1999. http://dx.doi.org/10.1007/978-1-4615-5161-4.

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Spear, Chris. System Verilog for Verification. Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-76530-3.

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Book chapters on the topic "Verilog"

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Edwards, Stephen A. "Verilog." In Languages for Digital Embedded Systems. Springer US, 2000. http://dx.doi.org/10.1007/978-1-4615-4325-1_3.

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LaMeres, Brock J. "Verilog Constructs." In Quick Start Guide to Verilog. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-10552-5_2.

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LaMeres, Brock J. "Verilog Constructs." In Quick Start Guide to Verilog. Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-44104-2_2.

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Lee, Weng Fook. "Signed Verilog." In Learning from VLSI Design Experience. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-030-03238-8_6.

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Sutherland, Stuart. "Introduction." In Verilog — 2001. Springer US, 2002. http://dx.doi.org/10.1007/978-1-4615-1713-9_1.

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Sutherland, Stuart. "Automatic (recursive) functions." In Verilog — 2001. Springer US, 2002. http://dx.doi.org/10.1007/978-1-4615-1713-9_10.

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Sutherland, Stuart. "Constant functions." In Verilog — 2001. Springer US, 2002. http://dx.doi.org/10.1007/978-1-4615-1713-9_11.

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Sutherland, Stuart. "Comma separated sensitivity lists." In Verilog — 2001. Springer US, 2002. http://dx.doi.org/10.1007/978-1-4615-1713-9_12.

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Sutherland, Stuart. "Combinational logic sensitivity lists." In Verilog — 2001. Springer US, 2002. http://dx.doi.org/10.1007/978-1-4615-1713-9_13.

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Sutherland, Stuart. "Implicit nets for continuous assignments." In Verilog — 2001. Springer US, 2002. http://dx.doi.org/10.1007/978-1-4615-1713-9_14.

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Conference papers on the topic "Verilog"

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Zhang, Yongan, Zhongzhi Yu, Yonggan Fu, Cheng Wan, and Yingyan Celine Lin. "MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generation." In 2024 IEEE LLM Aided Design Workshop (LAD). IEEE, 2024. http://dx.doi.org/10.1109/lad62341.2024.10691738.

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Saravanan, M., J. Saritha, S. Sree Vishnu Varthini, R. Sri Sathya Priya, R. Sri SivaSakthi, and Shiromani Balmukund Rahi. "Performance Analysis of 8/16/32-bit Calculator Using Verilog and System Verilog." In 2024 4th International Conference on Ubiquitous Computing and Intelligent Information Systems (ICUIS). IEEE, 2024. https://doi.org/10.1109/icuis64676.2024.10867037.

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Chopde, Abhay, Balganesh Thombre, Vedant Khodake, and Nikhil Yeware. "Vending Machine Using Verilog (FPGA)." In 2024 4th Asian Conference on Innovation in Technology (ASIANCON). IEEE, 2024. https://doi.org/10.1109/asiancon62057.2024.10838215.

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Ravikumar, P., M. V. Ganeswara Rao, and Vamaraju Nikitha. "Verilog Based Automated Retail System." In 2024 OPJU International Technology Conference (OTCON) on Smart Computing for Innovation and Advancement in Industry 4.0. IEEE, 2024. http://dx.doi.org/10.1109/otcon60325.2024.10687553.

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Himadeep, Thota, Aravind Krishnan, and Rajesh Kannan. "Intelligent Parking System Using Verilog." In 2024 3rd Odisha International Conference on Electrical Power Engineering, Communication and Computing Technology (ODICON). IEEE, 2024. https://doi.org/10.1109/odicon62106.2024.10797543.

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Gunna, Poorna Shashank, Leela Sai Srinivas Ontipuli, and Rajesh Kannan Megalingam. "Verilog Based Efficient Traffic Light System." In 2024 4th Asian Conference on Innovation in Technology (ASIANCON). IEEE, 2024. https://doi.org/10.1109/asiancon62057.2024.10838078.

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Ionici, Cristian-Valentin, Silviu-Dorin Meltiş, and Petru Papazian. "Distance Estimation Using Verilog FPGA Implementation." In 2024 International Symposium on Electronics and Telecommunications (ISETC). IEEE, 2024. https://doi.org/10.1109/isetc63109.2024.10797307.

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Wan, Ziying. "Verilog-based weather broadcasting light design." In 2024 4th International Symposium on Computer Technology and Information Science (ISCTIS). IEEE, 2024. http://dx.doi.org/10.1109/isctis63324.2024.10699223.

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Lu, Yao, Xiaoling Yang, and Yongbo Jin. "Bilinear Interpolation Algorithm Based on Verilog." In 2024 IEEE 7th International Conference on Electronic Information and Communication Technology (ICEICT). IEEE, 2024. http://dx.doi.org/10.1109/iceict61637.2024.10671174.

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Arumilli, Vamsi SriKrishna, Asish Krishna Ghatta, and Rajesh Kannan Megalingam. "FPGA – Controlled Automated Coffee Maker using Verilog." In 2024 Third International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT). IEEE, 2024. http://dx.doi.org/10.1109/iceeict61591.2024.10718631.

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Reports on the topic "Verilog"

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Clarke, Edmund, Himanshu Jain, and Daniel Kroening. Predicate Abstraction and Refinement Techniques for Verifying Verilog. Defense Technical Information Center, 2004. http://dx.doi.org/10.21236/ada457877.

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Jain, Himanshu, Natasha Sharygina, Daniel Kroening, and Edmund Clarke. Word Level Predicate Abstraction and Refinement for Verifying RTL Verilog. Defense Technical Information Center, 2005. http://dx.doi.org/10.21236/ada470547.

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Clarke, Edmund, and Daniel Kroening. Checking Consistency of C and Verilog using Predicate Abstraction and Induction. Defense Technical Information Center, 2004. http://dx.doi.org/10.21236/ada457879.

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Clarke, Edmund, Daniel Kroening, and Karen Yorav. Behavioral Consistency of C and Verilog Programs Using Bounded Model Checking. Defense Technical Information Center, 2003. http://dx.doi.org/10.21236/ada461052.

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Kutlu, İhsan. Türki̇ye’de Sağlıkta Özelleşmenin Sonuçları Sağlık Hı̇zmetlerı̇nı̇n Değişen Arz ve Talep Yapısı. İLKE İlim Kültür Eğitim Vakfı, 2021. http://dx.doi.org/10.26414/pn018.

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1980 yılı sonrasında dünyada ve Türkiye’de ağırlık kazanmaya başlayan neoliberal politikalar sağlık sistemini de kapsayacak şekilde hayatın pek çok alanına nüfuz etmiştir. Bu bağlamda tarihsel kökleri daha eski yıllara dayanmakla birlikte ülkemizde özellikle Sağlıkta Dönüşüm Programı çerçevesinde bu politikalar uygulamaya konulmuş ve zaman içerisinde önemli değişimler yaşanmıştır. Sağlık alanında özel sektörün giderek yaygınlık kazanması da yaşanan bu değişimlerden biri olmuştur. Sağlık sisteminin özelleşmesinin rekabete dayalı olarak sağlık hizmeti kalitesinin artması gibi olumlu bazı sonuçla
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Kramer, Mitchell. Customer Self-Service at Verizon. Patricia Seybold Group, 2006. http://dx.doi.org/10.1571/td8-10-06cc.

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Kramer, Mitchell. Customer Self-Service at Verizon Wireless. Patricia Seybold Group, 2006. http://dx.doi.org/10.1571/td7-27-06cc.

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Marshak, Ronni. Apple and/or Verizon: How Should Partners Provide Customer Support? Patricia Seybold Group, 2013. http://dx.doi.org/10.1571/bp02-14-13cc.

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Carroll, C., and F. Quick. Verizon Wireless Dynamic Mobile IP Key Update for cdma2000(R) Networks. RFC Editor, 2007. http://dx.doi.org/10.17487/rfc4784.

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Chelimo, Ph.D, Sheila, Carmen Cortez, Jessica Jackson, and D'Andre Weaver, Ph.D. Unintended Impact: How the Verizon Innovative Learning Schools Program Affected Its Educators' Job Satisfaction and Career Trajectories. Digital Promise, 2024. http://dx.doi.org/10.51388/20.500.12265/212.

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While the Verizon Innovative Learning Schools program has produced the intended results, such as enhancing how teachers use technology in the classroom to increase student engagement, we have also discovered some unexpected outcomes—teachers and coaches in participating schools have experienced improved job satisfaction and increased opportunities for career advancement. This white paper investigates how the program is resulting in this unintended impact.
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