Relevant bibliographies by topics / Verilog / Dissertations / Theses
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Dissertations / Theses on the topic 'Verilog'

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Published: 4 June 2021
Last updated: 25 July 2025

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1

Li, Lijun. "Optimization techniques for distributed Verilog simulation." Thesis, McGill University, 2008. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=21936.

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Moore's Law states that computational power will roughly double every 18 months. To the semiconductor designer, this means the never-ending challenge of bringing increasingly larger and more complex ICs (Integrated Circuits) to market. It is well known that the principle bottleneck in circuit design is simulation. Uniprocessor simulators may not be able to keep up with increased demands on them for both speed and memory. This thesis has three main contributions. The first contribution is a distributed Verilog simulation environment which can be executed on a cluster of workstations using a m
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2

Pace, Gordon G. "Hardware design based on Verilog HDL." Thesis, University of Oxford, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.298555.

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3

Kononov, Ekaterina (Ekaterina R. ). "Modeling photonic links in Verilog-A." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/85432.

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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (pages 59-60).<br>Integrated photonic links are a promising emerging technology that can relieve the interconnect bottleneck in core-to-core and core-to-memory communications of modern processors. Developing and optimizing photonic link systems requires simulation of integrated photonic devices side-by-side with electronic devices at the device, circuit, and system level. In previous efforts to s
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Skärpe, Anders. "Implementation of an SDR in Verilog." Thesis, Linköpings universitet, Kommunikationssystem, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-132325.

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This report presents an implementation of the software part in a software definedradio. The radio is not entirely implemented in software and therefore there arecertain limitations on the received signal. The parts implemented are oscillator,decimation filter, carrier synchronization, time synchronization, package detection,and demodulation. Different algorithms were tested for the different partsto measure the power consumption. To understand how the number of bits usedto represent the signal affects the power consumption, the number of bits wasreduced from 20 bits to 10 bits. This reduction
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5

Dirsė, Žygimantas. "Verilog kalbos sintezuojamų kostrukcijų atvaizdavimas SystemC kalboje." Master's thesis, Lithuanian Academic Libraries Network (LABT), 2005. http://vddb.library.lt/obj/LT-eLABa-0001:E.02~2005~D_20050524_183745-16346.

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This master work of the main subject: Developing and analysis of peripheral serial interface microcontroller RISC8 that is similar to PIC 16C57, goes about all phases of developing microcircuits. There are analyzed ways of the developing system on chip, described hardware description languages. The first phase is to develop and model a code with one of HDL (hardware description languages) like a Verilog. For that reason are used such developing tools as Cadence LDV-5.1, that is used for compiling, elaborating and simulating of the design with graphical interface. The second phase - synthesis i
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6

Huang, Hai 1974. "A partitioning framework for distributed verilog simulation /." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=80291.

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The HDL (Hardware Description Language) helps designers of modern digital systems to compete with the increasing size and complexity of VLSI circuits. Simulation is usually used for verification in the design process, which tends to be a bottleneck. Distributed simulation on a network of workstations tries to provide a cost-effective solution. The partitioning of the circuit is a critical factor to the performance of the distributed simulation.<br>This study presents the design and implementation of a partitioning framework which is incorporated into the DVS (Distribute Verilog Simulato
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Pekofsky, Gregory. "GCS : a framework for distributed verilog simulation." Thesis, McGill University, 2005. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=82404.

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The verification of VLSI circuits, which are ever increasing in size and complexity, is bottlenecked during simulation within the circuit design process. Distributed simulation on a cluster of workstations or a shared memory multiple processor computer attempts a cost-effective solution. The key factor in performance of these simulations is the development of distributed simulation algorithms that make use of the circuits' underlying properties.<br>This study presents the design and implementation of a distributed simulation framework to better produce and test simulation algorithms. Th
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8

Feng, Zhiming Niu Guofu. "Compact modeling of SiGe HBTs using VERILOG-A." Auburn, Ala., 2006. http://repo.lib.auburn.edu/2006%20Summer/Theses/FENG_ZHIMING_19.pdf.

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9

Rangoonwala, Sakina. "A Verilog 8051 Soft Core for FPGA Applications." Thesis, University of North Texas, 2009. https://digital.library.unt.edu/ark:/67531/metadc11013/.

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The objective of this thesis was to develop an 8051 microcontroller soft core in the Verilog hardware description language (HDL). Each functional unit of the 8051 microcontroller was developed as a separate module, and tested for functionality using the open-source VHDL Dalton model as benchmark. These modules were then integrated to operate as concurrent processes in the 8051 soft core. The Verilog 8051 soft core was then synthesized in Quartus® II simulation and synthesis environment (Altera Corp., San Jose, CA, www.altera.com) and yielded the expected behavioral response to test programs w
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10

Rangoonwala, Sakina Kougianos Elias. "A Verilog 8051 soft core for FPGA applications." [Denton, Tex.] : University of North Texas, 2009. http://digital.library.unt.edu/permalink/meta-dc-11013.

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11

Abrami, Greg. "Magnetic Graphene Memory Circuit Characterization And Verilog-A Modeling." ScholarWorks @ UVM, 2017. http://scholarworks.uvm.edu/graddis/801.

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Memory design plays an important role in modern computer technology in regard to overall performance and reliability. Prior memory technologies, including magneticcore memory, hard disk drives, DRAM, SRAM have limitations in regard to bit density, IC integration, power efficiency, and physical size, respectively. To address these limitations we propose to develop a magnetic graphene random access memory (MGRAM) utilizing graphene Hall effect, which takes advantage of the inherent reliability of magnetic memory and superior electrical properties of graphene (high carrier mobility, zero-band gap
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12

Vummannagari, Akshay. "VERILOG DESIGN AND FPGA PROTOTYPE OF A NANOCONTROLLER SYSTEM." UKnowledge, 2010. http://uknowledge.uky.edu/gradschool_theses/20.

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Many new fabrication technologies, from nanotechnology and MEMS to printed organic semiconductors, center on constructing arrays of large numbers of sensors, actuators, or other devices on a single substrate. The utility of such an array could be greatly enhanced if each device could be managed by a programmable controller and all of these controllers could coordinate their actions as a massively-parallel computer. Kentucky Architecture nanocontroller array with very low per controller circuit complexity can provide efficient control of nanotechnology devices. This thesis provides a detailed d
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13

Mysore, Omar. "Compact modeling of circuits and devices in Verilog-A." Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/77441.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (p. 57-58).<br>The compact model of a circuit or device is a system of linear and/or nonlinear differential equations that effectively models the behavior of the circuit or device. Compact modeling plays a critical role in circuit simulation, because in order to simulate a circuit with a specific component, the compact model of this component is needed in the circuit simulator. Two contributions rela
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Cheng, Tina 1980. "Sieve : an XML-based structural Verilog rules check tool." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/27091.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.<br>Includes bibliographical references (p. 83).<br>The complexity of microprocessor chip designs continues to grow with every generation. At the same time, the amount of manpower needed for these projects also continues to grow, creating the need for a better integration flow. Due to this trend, many design conventions are set before the implementation of the chip commences to aid in the integration. This thesis describes the development of a suite of tools which check various d
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15

COSTA, Caio Alonso da. "Desenvolvimento de Hardware de Criptografia RSA em Linguagem Verilog." reponame:Repositório Institucional da UNIFEI, 2014. http://repositorio.unifei.edu.br:8080/xmlui/handle/123456789/319.

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Submitted by repositorio repositorio (repositorio@unifei.edu.br) on 2016-01-28T17:03:32Z No. of bitstreams: 1 dissertacao_costa1_2014.pdf: 17015318 bytes, checksum: 2e443a7d66b8315c5007fe016f96588e (MD5)<br>Made available in DSpace on 2016-01-28T17:03:32Z (GMT). No. of bitstreams: 1 dissertacao_costa1_2014.pdf: 17015318 bytes, checksum: 2e443a7d66b8315c5007fe016f96588e (MD5) Previous issue date: 2014-07<br>Este trabalho apresenta um modelo e arquitetura de um hardware desenvolvido em linguagem Verilog para exponenciação modular do algoritmo de criptografia assimétrica RSA. Uma breve dis
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RIBEIRO, Leandro Marques. "Central de comunicação em VERILOG para eletrodos ativos de EEG." reponame:Repositório Institucional da UNIFEI, 2018. http://repositorio.unifei.edu.br/xmlui/handle/123456789/1610.

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Submitted by repositorio repositorio (repositorio@unifei.edu.br) on 2018-08-30T18:49:50Z No. of bitstreams: 1 dissertacao_2018119.pdf: 3071595 bytes, checksum: da2451b6bac94e22d3ecb625b1fd5a53 (MD5)<br>Made available in DSpace on 2018-08-30T18:49:50Z (GMT). No. of bitstreams: 1 dissertacao_2018119.pdf: 3071595 bytes, checksum: da2451b6bac94e22d3ecb625b1fd5a53 (MD5) Previous issue date: 2018-07<br>Este estudo apresenta o desenvolvimento de uma central de controle em Verilog para eletrodos ativos, que será utilizado em um aparelho de Eletroencefalograma - EEG com Eletrodos Ativos que está send
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17

Roy, Diana. "Realisierung eines Verilog/VHDL Codegenerators fuer graphisch erfasste Finite State Machines." Master's thesis, Universitätsbibliothek Chemnitz, 1997. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-199700155.

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Es wurden verschieden Kodierungsarten fuer FSMs untersucht, schwerpunktmaessig Gray Code und andere Arten der hazardfreien Kodierung. Ein spezieller Kodierungsalgorithmus zur hazardfreien Kodierung wurde entwickelt und in eine Entwurfsumgebung implementiert. Ein weitere Schwerpunkt der Arbeit sind Codegeneratoren, die eine Verhaltensbeschreibung der FSM in Verilog oder in VHDL erzeugen.
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18

Zheng, Geng. "Layout-accurate Ultra-fast System-level Design Exploration Through Verilog-ams." Thesis, University of North Texas, 2013. https://digital.library.unt.edu/ark:/67531/metadc271923/.

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This research addresses problems in designing analog and mixed-signal (AMS) systems by bridging the gap between system-level and circuit-level simulation by making simulations fast like system-level and accurate like circuit-level. The tools proposed include metamodel integrated Verilog-AMS based design exploration flows. The research involves design centering, metamodel generation flows for creating efficient behavioral models, and Verilog-AMS integration techniques for model realization. The core of the proposed solution is transistor-level and layout-level metamodeling and their incorporati
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19

Roy, Diana. "Realisierung eines Verilog/VHDL Codegenerators für graphisch erfasste Finite State Machines." [S.l. : s.n.], 1997. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB10324519.

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20

Gunasekaren, Shankar. "A synthesizable verilog model of serial protocol engine for USB 1.1 device." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-10182.

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<p>USB has become a popular interface for exchanging data between PC’s and peripherals. An increasing number of portable peripherals are using the USB interface to communicate with the PC.The design and implementation of a synthesizable model of the USB 1.1 protocol engine is presented in this report The PHY is compatible with the USB 1.1 transceiver macrocell interface (UTMI) specification and the simulation test confirmed the successful operation of circuits for both full speed (12 Mbps) and low speed (1.5 Mbps) data transmission. the model is written completely in behavioral verilog with a
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21

Chen, Adam Y. (Adam Yu-Chih). "Implementation of the Intel 486 SX microprocessor in Verilog hardware description language." Thesis, Massachusetts Institute of Technology, 1993. http://hdl.handle.net/1721.1/79470.

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22

Kandala, Aravind. "High-Frequency Oscillator Design and Characterization Using Verilog-ams Modeling and Simulation." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1142011059.

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23

RAGHURAMAN, SRINIVASAN. "IMPLEMENTATION AND PERFORMANCE MEASUREMENTS OF A VERILOG-AMS MODEL OF BSIM3v3.3 TRANSISTOR." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1163711277.

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24

Saripalli, Manjeera. "Mathematical Modeling and Simulation of Colorectal Cancer." OpenSIUC, 2011. https://opensiuc.lib.siu.edu/theses/698.

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Understanding the cancer pathology and develop effective treatment strategies play significant roles in improving cancer survival rates. In this thesis, evaluations of mathematical modeling and simulation were studied and presented. Colorectal system was investigated from gene and cell levels. The Hardware Descriptive Language (HDL) package and codes were developed to simulate the cancer models. Representative codes and figures were illustrated. Results suggest that the HDL is an effective method to conduct the modeling and simulation of cancers. It is essential to develop advanced technology
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25

Park, Sungho. "A verilog-hdl implementation of virtual channels in a network-on-chip router." [College Station, Tex. : Texas A&M University, 2008. http://hdl.handle.net/1969.1/ETD-TAMU-2890.

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26

Lee, Keith. "The DEVBOX development education platform : an environment for introducing Verilog to young students." Thesis, University of British Columbia, 2016. http://hdl.handle.net/2429/56802.

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Hardware description languages are considered to be challenging to learn, as are the logic design concepts required to effectively use them. University logic design courses are considered by many to be much more difficult than their software development counterparts and the subject is not generally addressed by pre-university curricula. Introducing hardware description earlier in a student’s career will improve their chances of success in future logic design courses. The barrier-to-entry faced in introducing hardware description, caused by complex development environments and the learning of f
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27

Stewart, Daryl John. "A uniform semantics for verilog and VHDL suitable for both simulation and verification." Thesis, University of Cambridge, 2002. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.620451.

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28

Kasarabada, Yasaswy. "A Verilog Description and Efficient Hardware Implementation of the Baillie-PSW Primality Test." University of Cincinnati / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1471347471.

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29

Sampath, Kumar Santhiya. "Implementation of Low-Bit Rate Audio Codec, Codec2, in Verilog on Modern FPGAS." Miami University / OhioLINK, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=miami158819886466373.

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30

Alape, Vivekananda Ashish. "Test Generation For Digital Circuits – A Mapping Study On VHDL, Verilog and SystemVerilog." Thesis, Mälardalens högskola, Inbyggda system, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-41201.

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Researchers have proposed different methods for testing digital logic circuits. The need for testing digital logic circuits has become more important than ever due to the growing complexity of such systems. During the development process, testing is focusing on design defects as well as manufacturing and wear out type of defects. Failures in digital systems could be caused by design errors, the use of inherently probabilistic devices, and manufacturing variability. The research in this area has focused also on the design of digital logic circuit for achieving better testability. In addition, a
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31

GURUMURTHY, ARAVIND. "COMPARISON OF BEHAVIOR OF MOSFET TRANSISTORS DESCRIBED IN HARDWARE DESCRIPTION LANGUAGES." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1141363591.

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32

Dimitriov, Jordan. "Developing semantics of Verilog HDL in formal compositional design of mixed hardware/software systems." Thesis, De Montfort University, 2002. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.250766.

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33

SINGH, GUNEET. "HIGH-FREQUENCY CHARGE-PUMP BASED PHASE-LOCKED LOOP DESIGN AND IT'S CHARACTERIZATION USING VERILOG-AMS." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1155077793.

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34

Krishnamurthy, Anush Viswanath. "FPGA BASED CONTROL OF HIGH TEMPERATURE SWITCHED RELUCTANCE MOTOR FOR IMPROVING THE INPUT POWER QUALITY." UKnowledge, 2004. http://uknowledge.uky.edu/gradschool_theses/246.

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This thesis develops a hardware circuit implementation of a novel algorithm for reducing a SRM drives input current ripple or equivalently to improve the SRM drives input power quality. The algorithm requires the SRMs phase current to follow a trapezoidal trajectory relative to the rotors position with the magnitude of the current dependent on the desired average torque. This thesis deals with the generation of the required current command that is the input to a separate analog current regulator that forces the SRMs current to follow the generated current command. The final circuit design must
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Ou, Jen-Chieh. "HARDWARE DESCRIPTION LANGUAGE PROGRAM SLICING AND WAY TO REDUCE BOUNDED MODEL CHECKING SEARCH OVERHEAD." Case Western Reserve University School of Graduate Studies / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=case1159738055.

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36

NARAYANAN, SHRUTHI. "HARDWARE IMPLEMENTATION OF GENETIC ALGORITHM MODULES FOR INTELLIGENT SYSTEMS." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1122909070.

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37

Singh, Guneet. "High-frequency charge-pump based phase-locked loop design and it's characterization using verilog-ams." Cincinnati, Ohio : University of Cincinnati, 2006. http://www.ohiolink.edu/etd/view.cgi?acc%5Fnum=ucin1155077793.

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Thesis (M.S.)--University of Cincinnati, 2006.<br>Title from electronic thesis title page (viewed Nov. 29, 2006). Includes abstract. Keywords: Phase Locked Loops, PLLs, PLL, Verilog-AMS. Includes bibliographical references.
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38

Bäck, Carl. "Evaluation of high-level synthesis tools for generation of Verilog code from MATLAB based environments." Thesis, Luleå tekniska universitet, Institutionen för system- och rymdteknik, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-78738.

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FPGAs are of interest in the signal processing domain as they provide the opportunity to run algorithms at very high speed. One possible use case is to sort incoming data in a measurement system, using e.g. a histogram method. Developing code for FPGA applications usually requires knowledge about special languages, which are not common knowledge in the signal processing domain. High-level synthesis is an approach where high-level languages, as MATLAB or C++, can be used together with a code generation tool, to directly generate an FPGA ready output. This thesis uses the development of a histog
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Aguirre, Morales Jorge Daniel. "Characterization and modeling of graphene-based transistors towards high frequency circuit applications." Thesis, Bordeaux, 2016. http://www.theses.fr/2016BORD0235/document.

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Ce travail présente une évaluation des performances des transistors à effet de champ à base de graphène (GFET) grâce à des simulations électriques des modèles compact dédiés à des applications à haute fréquence. Les transistors à base de graphène sont parmi les nouvelles technologies et sont des candidats prometteurs pour de futures applications à hautes performances dans le cadre du plan d’action « au-delà du transistor CMOS ». Dans ce contexte, cette thèse présente une évaluation complète des transistors à base de graphène tant au niveau du dispositif que du circuit grâce au développement de
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Pampana, Srilaxmi. "FPGA BASED IMPLEMENTATION OF A POSITION ESTIMATOR FOR CONTROLLING A SWITCHED RELUCTANCE MOTOR." UKnowledge, 2004. http://uknowledge.uky.edu/gradschool_theses/254.

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Rotor Position information is essential in the operation of the Switched Reluctance Motor (SRM) for properly controlling its phase currents. This thesis uses Field Programmable Gate Array (FPGA) technology to implement a method to estimate the SRMs rotor position using the inverse inductance value of the SRMs phases. The estimated rotor position is given as input to the Commutator circuit, also implemented in the FPGA, to determine when torque-producing currents should be input in the SRM phase windings. The Estimator and Commutator design is coded using Verilog HDL and is simulated using Xili
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Srinivasan, Vikram. "HDL Descriptions of Artificial Neuron Activation Functions." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1121113992.

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42

Veškrna, Filip. "Návrh digitálního IP bloku pro diskrétní kosinovu transformaci." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2015. http://www.nusl.cz/ntk/nusl-221104.

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Tato diplomová práce se zabývá návrhem IP bloku pro diskrétní kosinovou transformaci. V~teoretické části jsou shrnuty algoritmy pro výpočet diskrétní kosinové transformace a diskutována jejich použitelnost v~hardwaru. Zvolený algoritmus pro hardwarovou implementaci je modelován v jazyce C. Poté je popsán na RTL úrovni, verifikován a je provedena syntéza v~technologii TSMC 65 nm. Hardwarová implementace je poté zhodnocena s ohledem na datovou propustnost, plochu, rychlost and spotřebu.
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Verma, Anshuman. "On the Programmability and Performance of OpenCL Designs for FPGA." Thesis, Virginia Tech, 2018. http://hdl.handle.net/10919/92699.

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Field programmable gate arrays (FPGAs) have been emerging as a promising bedrock to provide opportunities for several types of accelerators that spans across various domains such as finance, web-search, and data center networking, among others. Research interests facilitating the development of accelerators on FPGAs are increasing significantly, in particular, because of their effectiveness with a variety of applications, flexibility, and high performance per watt. However, several key challenges remain that hinder their large-scale deployment. Overcoming these challenges would enable them to
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Nicodemus, Joshua. "An implementation of the usf/ calvo model in verilog-a to enforce charge conservation in applicable fet models." [Tampa, Fla.] : University of South Florida, 2005. http://purl.fcla.edu/fcla/etd/SFE0001107.

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45

Jin, Chuan. "Test implementation of embedded cores-based sequential circuits using Verilog HDL under Altera MAX Plus II development environment." Thesis, University of Ottawa (Canada), 2004. http://hdl.handle.net/10393/26669.

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A Verilog HDL digital circuit fault simulator to detect permanent stuck-at logic faults for embedded cores-based synchronous sequential circuits is proposed in this thesis. The fault simulator can emulate a typical built-in self-testing (BIST) environment that utilizes a test pattern generator that sends its outputs to a module under test (MUT), with the resulting output from the MUT being fed into a test data analyzer. A fault is detected if the module response is different from that of the fault-free MUT. The fault simulator is suitable for testing synchronous sequential circuits described a
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Krencker, Jean-Christophe. "Développement d'outils et de modèles CAO de haut niveau pour la simulation électrothermique de circuits mixtes en technologie 3D." Phd thesis, Université de Strasbourg, 2012. http://tel.archives-ouvertes.fr/tel-00804671.

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Les travaux de cette thèse s'inscrivent dans un projet de grande envergure, le projet 3D-IDEAS, financé par l'ANR. Le but de ce projet est d'établir la chaîne complète de l'intégration de circuits en technologie 3D. Les densités de puissance dans ces circuits sont telles que les problèmes liés à la température - électromigration, désappariement des courants et tensions de polarisation, etc. - sont susceptibles de remettre en cause la conception du circuit. Le coût élevé de la fabrication de ces circuits oblige le concepteur à valider le comportement électrothermique des circuits préalablement
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Carlsson, Mats. "Utilizing FPGAs for data acquisition at high data rates." Thesis, Linköping University, Electronic Devices, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-17820.

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<p>The aim of this thesis was to configure an FPGA with high speed ports to capture data from a prototype 4 bit ΣΔ analogue-to-digital converter sending data at a rate of 2.4 Gbps in four channels and to develop a protocol for transferring the data to a PC for analysis. Data arriving in the four channels should be sorted into 4 bit words with one bit taken successively from each of the channels. A requirement on the data transfer was that the data in the four channels should arrive synchronously to the FPGA. A Virtex-5 FPGA on a LT110X platform was used with <em>Rocket<sup>TM</sup>IO</em> GPT
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48

Moreira, C. V. "Implementação do modelo contínuo estático e dinâmico de nanofios transistores MOS sem junções usando linguagem Verilog-A para projeto de circuitos CMOS/." reponame:Biblioteca Digital de Teses e Dissertações da FEI, 2018. https://doi.org/10.31414/EE.2018.D.130230.

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49

CUI, ZHI. "MODELING AND SIMULATION OF LONG TERM DEGRADATION AND LIFETIME OF DEEP-SUBMICRON MOS DEVICE AND CIRCUIT." Doctoral diss., University of Central Florida, 2005. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2163.

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Long-term hot-carrier induced degradation of MOS devices has become more severe as the device size continues to scale down to submicron range. In our work, a simple yet effective method has been developed to provide the degradation laws with a better predictability. The method can be easily augmented into any of the existing degradation laws without requiring additional algorithm. With more accurate extrapolation method, we present a direct and accurate approach to modeling empirically the 0.18-&igrave;m MOS reliability, which can predict the MOS lifetime as a function of drain voltage and cha
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50

Thakur, Ravi Bhushan. "Low power design implementation of a signal acquisition module." Thesis, Kansas State University, 2010. http://hdl.handle.net/2097/4617.

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Master of Science<br>Department of Electrical and Computer Engineering<br>Don M. Gruenbacher<br>As semiconductor technologies advance, the smallest feature sizes that can be fabricated get smaller. This has led to the development of high density FPGAs capable of supporting high clock speeds, which allows for the implementation of larger more complex designs on a single chip. Over the past decade the technology market has shifted toward mobile devices with low power consumption at or near the top of design considerations. By reducing power consumption in FPGAs we can achieve greater reliability
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