Log in

Relevant bibliographies by topics / Verilog / Journal articles

To see the other types of publications on this topic, follow the link: Verilog.

Journal articles on the topic 'Verilog'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 July 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'Verilog.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

Lööw, Andreas. "The Simulation Semantics of Synthesisable Verilog." Proceedings of the ACM on Programming Languages 9, OOPSLA1 (2025): 1295–320. https://doi.org/10.1145/3720484.

Full text

Abstract:

Despite numerous previous formalisation projects targeting Verilog, the semantics of Verilog defined by the Verilog standard -- Verilog's simulation semantics -- has thus far eluded definitive mathematical formalisation. Previous projects on formalising the semantics have made good progress but no previous project provides a formalisation that can be used to execute or formally reason about real-world hardware designs. In this paper, we show that the reason for this is that the Verilog standard is inconsistent both with Verilog practice and itself. We pinpoint a series of problems in the Veril

APA, Harvard, Vancouver, ISO, and other styles

2

Chen, Qinlin, Nairen Zhang, Jinpeng Wang, et al. "The Essence of Verilog: A Tractable and Tested Operational Semantics for Verilog." Proceedings of the ACM on Programming Languages 7, OOPSLA2 (2023): 234–63. http://dx.doi.org/10.1145/3622805.

Full text

Abstract:

With the increasing need to apply modern software techniques to hardware design, Verilog, the most popular Hardware Description Language (HDL), plays an infrastructure role. However, Verilog has several semantic pitfalls that often confuse software and hardware developers. Although prior research on formal semantics for Verilog exists, it is not comprehensive and has not fully addressed these issues. In this work, we present a novel scheme inspired by previous work on defining core languages for software languages like JavaScript and Python. Specifically, we define the formal semantics of Veri

APA, Harvard, Vancouver, ISO, and other styles

3

Blair, G. M. "Verilog: accelerating digital design." Electronics & Communication Engineering Journal 9, no. 2 (1997): 68–72. http://dx.doi.org/10.1049/ecej:19970203.

Full text

APA, Harvard, Vancouver, ISO, and other styles

4

Kuthe, Pascal, Markus Muller, and Michael Schroter. "VerilogAE: An Open Source Verilog-A Compiler for Compact Model Parameter Extraction." IEEE Journal of the Electron Devices Society 8 (2020): 1416–23. http://dx.doi.org/10.1109/jeds.2020.3023165.

Full text

APA, Harvard, Vancouver, ISO, and other styles

5

Koti, Mr Manjunath, and Dr Basavaraj I. Neelgar. "CAN Tx Frame Implementation using Verilog." Journal of University of Shanghai for Science and Technology 23, no. 07 (2021): 1303–13. http://dx.doi.org/10.51201/jusst/21/07311.

Full text

Abstract:

This article discusses the concept of CAN protocol and its implementation in verilog language. Initially the CAN protocol description is given in brief with the block diagram, later its design, implementation in verilog code is presented. The CAN transmission (Tx) data Frame is realized using verilog code, this is achieved by defining individual sub-blocks verilog codes and combining these to get the CAN transmission of data frame. In the year 1986, CAN data link layer protocol was introduced in SAE conference. In 1993, CAN protocol and high speed physical layer were internationally accredited

APA, Harvard, Vancouver, ISO, and other styles

6

DHARMENDRA, SINGH, SONI UPENDRA, SHOBHANI KARAN, KARKASHE YASH, LIMJE SHUBHAM, and NAYAK AAYUSH. "VERILOG BASED UART SYSTEM DESIGN." i-manager’s Journal on Embedded Systems 6, no. 2 (2018): 34. http://dx.doi.org/10.26634/jes.6.2.14057.

Full text

APA, Harvard, Vancouver, ISO, and other styles

7

PEISCHL, BERNHARD, NAVEED RIAZ, and FRANZ WOTAWA. "AUTOMATED DEBUGGING OF VERILOG DESIGNS." International Journal of Software Engineering and Knowledge Engineering 22, no. 05 (2012): 695–723. http://dx.doi.org/10.1142/s0218194012500209.

Full text

Abstract:

In this article we report on novel insights in model-based software debugging of hardware description languages (HDLs). Today's simulation driven working process emphasizes the need for exploiting test suites not only for detecting but also for localizing the root cause of misbehavior. We discuss the modeling approaches for the various artifacts of the Verilog hardware description language (blocking and non-blocking statements, expressions, execution ordering) and present a novel model incorporating test suites. The evaluation of our approach on the well-known ISCAS89 benchmarks concerning sin

APA, Harvard, Vancouver, ISO, and other styles

8

Umidjon, Zaripovich Narziyev. "VERILOG DASTURLASH TILI YORDAMIDA DASTURLASH." GOLDEN BRAIN 1, no. 16 (2023): 9–14. https://doi.org/10.5281/zenodo.8043911.

Full text

Abstract:

<em>Maqolada Quartus II muhitida Verilog HDL dasturlash tili yordamida mantiqiy qurilmalarni dasturlash va boshqarish usullari haqida fikr yuritiladi. Qurilma sifatida Altera Cyclone III 3C16 FPGA ni tanlaymiz. Qurilmaning pinlari va portlarini dastur o‘zgaruvchilariga ulash orqali ularga uzatiluvchi signallarni o‘zgartirish va boshqarish usullari yoritiladi.</em>

APA, Harvard, Vancouver, ISO, and other styles

9

Wang, Chao, Yicong Shao, Jiajie Huang, et al. "V2Va +: An Efficient SystemVerilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation." IEEE Open Journal of Circuits and Systems 5 (2024): 387–97. https://doi.org/10.1109/ojcas.2024.3451530.

Full text

APA, Harvard, Vancouver, ISO, and other styles

10

Ferrari, F. "Verilog quickstart! a practical guide to simulation and synthesis in verilog, 2nd ed. [Book Review]." IEEE Circuits and Devices Magazine 17, no. 2 (2001): 49–50. http://dx.doi.org/10.1109/mcd.2001.920884.

Full text

APA, Harvard, Vancouver, ISO, and other styles

11

Azmi, Fairuz. "Aplikasi Perancang Abstraksi Verilog Mesin Keadaan Terbatas Otomatis." Semesta Teknika 24, no. 2 (2021): 120–28. http://dx.doi.org/10.18196/st.v24i2.12863.

Full text

Abstract:

Saat ini, hampir semua perangkat elektronik menggunakan prosesor di dalamnya. Dalam sebuah prosesor, terdapat bagian control unit yang berfungsi mengatur operasi dari komponen-komponen di dalam prosesor. Control unit merupakan sebuah mesin keadaan terbatas atau disebut finite state machine (FSM). Rangkaian FSM dapat disintesis secara manual ataupun secara otomatis menggunakan bahasa abstraksi Verilog. Dalam penelitian ini, dibuat sebuah aplikasi yang dapat membantu pengguna merancang FSM dan selanjutnya menyimpannya dalam format Verilog. Aplikasi yang dibuat secara fungsional dapat berjalan de

APA, Harvard, Vancouver, ISO, and other styles

12

M P, Ranganatha. "Implementation of SPI Protocol using Verilog." International Journal for Research in Applied Science and Engineering Technology 13, no. 2 (2025): 1619–30. https://doi.org/10.22214/ijraset.2025.67182.

Full text

Abstract:

The implementation of communication protocols using Verilog presents a novel approach to digital communication system design. This project explores the development and integration of various communication protocols within the Verilog hardware description language (HDL) framework. The primary focus lies in the synthesis of protocols such as SPI (Serial Peripheral Interface). The report begins by discussing the fundamental concepts behind Verilog HDL and its relevance in digital system design. It then explores into the detailed architecture and functionality of each communication protocol target

APA, Harvard, Vancouver, ISO, and other styles

13

Bindal, Kirti, Mukul Sharma, and Rachit Agarwal. "Design and Implementation of SRAM Using Verilog." International Journal for Research in Applied Science and Engineering Technology 12, no. 3 (2024): 117–24. http://dx.doi.org/10.22214/ijraset.2024.58708.

Full text

Abstract:

Abstract: This comprehensive review delves into the intricate realm of the Static Random-Access Memory (SRAM) design and implementation, elucidating its pivotal role in shaping the performance, efficiency, and reliability of contemporary electronic systems, involving applications in ASIC devices. With a primary focus on the integration of Verilog, a hardware description language (HDL), the paper provides an in-depth background on SRAM, meticulously detailing its architecture, operation, and overall significance in electronic systems. The review meticulously addresses challenges inherent in SRA

APA, Harvard, Vancouver, ISO, and other styles

14

Paramahamsa, Prof Mr YRK. "Implementation of Zigbee Transmitter using Verilog." International Journal for Research in Applied Science and Engineering Technology V, no. III (2017): 1010–17. http://dx.doi.org/10.22214/ijraset.2017.3185.

Full text

APA, Harvard, Vancouver, ISO, and other styles

15

Shet, Ganesh Gopal, Jamuna V, Shravani S, Nayana H G, and Pramod Kumar S. "Implementation of AES Algorithm using Verilog." JNNCE Journal of Engineering and Management 4, no. 1 (2020): 17. http://dx.doi.org/10.37314/jjem.2020.040103.

Full text

APA, Harvard, Vancouver, ISO, and other styles

16

Jaya, E., B. Maneesha, G. Sriram, G. Sai, and M. Siddhu. "Design of RISCV processor using verilog." i-manager's Journal on Digital Signal Processing 12, no. 1 (2024): 15. http://dx.doi.org/10.26634/jdp.12.1.20567.

Full text

Abstract:

The main goal of this paper is to develop a 32-bit pipelined processor with several clock domains based on the RISCV (open source RV32I Version 2.0) ISA. To minimize the complexity of the instruction set and speed up the execution time per instruction, a RISC (Reduced Instruction Set Computer) processor that uses less hardware than a CISC (Complex Instruction Set Computer) is used. Furthermore, this paper constructed this processor with five levels of pipelining with the aid of necessary block diagrams, and all of the processes are well described. In this paper, a RISCV processor is designed a

APA, Harvard, Vancouver, ISO, and other styles

17

Palumbo, G. "Design Through Verilog HDL [Book Review]." IEEE Circuits and Devices Magazine 22, no. 4 (2006): 35. http://dx.doi.org/10.1109/mcd.2006.1708385.

Full text

APA, Harvard, Vancouver, ISO, and other styles

18

Tan, Tze Sin, and Bakhtiar Affendi Rosdi. "Verilog HDL Simulator Technology: A Survey." Journal of Electronic Testing 30, no. 3 (2014): 255–69. http://dx.doi.org/10.1007/s10836-014-5449-5.

Full text

APA, Harvard, Vancouver, ISO, and other styles

19

Xu, Ying. "Asynchronous FIFO Design Based on Verilog." Highlights in Science, Engineering and Technology 38 (March 16, 2023): 965–70. http://dx.doi.org/10.54097/hset.v38i.5983.

Full text

Abstract:

With the rapid development of integrated circuits, asynchronous First Input First Output (FIFO) is often used to solve the problem of data transmission across the clock domain. This paper mainly studies the key problem of asynchronous FIFO design - the generation of empty - full signal. To solve this problem, it is necessary to realize the synchronization of signal across the clock domain and convert binary code into gray code to reduce the probability of metastable state. The null and full signals generated by the asynchronous FIFO designed in this paper are false null and false full, but thi

APA, Harvard, Vancouver, ISO, and other styles

20

Wang, Yilin. "Verilog-based digital clock design methodology." Theoretical and Natural Science 14, no. 1 (2023): 102–7. http://dx.doi.org/10.54254/2753-8818/14/20240902.

Full text

Abstract:

A digital electronic clock is a sophisticated instrument that employs digital circuits to render the timehours, minutes, and secondsin a digital format. This paper delves into the intricate design journey of creating a basic digital clock using the powerful Verilog HDL paired with a seven-segment digital tube. The core objective revolves around the realization of the clocks essential features, emphasizing both timing mechanics and its visual display. The architecture of the digital clock circuit is a seamless integration of three pivotal modules: the frequency divider, which ensures accurate t

APA, Harvard, Vancouver, ISO, and other styles

21

Chetan, Bhagwat, and Ramesh K.B. "Design of Three Way Traffic using Verilog HDL." Journal of Advancement in Electronics Design 7, no. 3 (2024): 8–13. https://doi.org/10.5281/zenodo.12899273.

Full text

Abstract:

<em>The topic of this paper focus to the design of traffic light system using the hardware language Verilog HDL. Traffic lights are the road sign devices used to manage traffic in road. These are fixed on the road to control the flow of the traffic at the road to avoid accident. By displaying lights red, yellow and green. The traffic light system has traditionally designed with fixed time slot for each direction. This approach while often leads to not so efficient traffic management especially during non-peak hours or in an emergency condition. The purpose of my paper is to improve the traditi

APA, Harvard, Vancouver, ISO, and other styles

22

Ho, Chia-Tung, Haoxing Ren, and Brucek Khailany. "VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool." Proceedings of the AAAI Conference on Artificial Intelligence 39, no. 1 (2025): 300–307. https://doi.org/10.1609/aaai.v39i1.32007.

Full text

Abstract:

Due to the growing complexity of modern Integrated Circuits (ICs), automating hardware design can prevent a significant amount of human error from the engineering process and result in less errors. Verilog is a popular hardware description language for designing and modeling digital systems; thus, Verilog generation is one of the emerging areas of research to facilitate the design process. In this work, we propose VerilogCoder, a system of multiple Artificial Intelligence (AI) agents for Verilog code generation, to autonomously write Verilog code and fix syntax and functional errors using coll

APA, Harvard, Vancouver, ISO, and other styles

23

Singh, Jagmeet, Hugh Morison, Zhimu Guo, et al. "Neuromorphic photonic circuit modeling in Verilog-A." APL Photonics 7, no. 4 (2022): 046103. http://dx.doi.org/10.1063/5.0079984.

Full text

Abstract:

One of the significant challenges in neuromorphic photonic architectures is the lack of good tools to simulate large-scale photonic integrated circuits. It is crucial to perform simulations on a single platform to capture the circuit’s behavior in the presence of both optical and electrical components. Here, we adopted a Verilog-A based approach to model neuromorphic photonic circuits by considering both the electrical and optical properties. Verilog-A models for the primary optical devices, such as lasers, couplers, waveguides, phase shifters, and photodetectors, are discussed, along with stu

APA, Harvard, Vancouver, ISO, and other styles

24

Kumar, Amit, Shankar Shankar, and Neeraj Sharma. "Verification of Asynchronous FIFO using System Verilog." International Journal of Computer Applications 86, no. 11 (2014): 16–20. http://dx.doi.org/10.5120/15029-3347.

Full text

APA, Harvard, Vancouver, ISO, and other styles

25

Nasir, Nadia Mohamad, Irni Hamiza Hamzah, Azman Ab Malik, Mohd Hanapiah Abdullah, Alhan Farhanah Abd Rahim, and Ahmad Asri ABD Samat. "Electronic combination lock system using verilog HDL." International Journal of Advanced Technology and Engineering Exploration 8, no. 75 (2021): 328–37. http://dx.doi.org/10.19101/ijatee.2020.762169.

Full text

APA, Harvard, Vancouver, ISO, and other styles

26

C V, Aparna, and Mary Joseph. "Double precision floating point core in verilog." International Journal on Cybernetics & Informatics 5, no. 2 (2016): 135–45. http://dx.doi.org/10.5121/ijci.2016.5215.

Full text

APA, Harvard, Vancouver, ISO, and other styles

27

S Nair, Lakshmi, and Arun K.L. "Simulation of BASK,BPSK,BFSKmodulators using verilog." International Journal on Cybernetics & Informatics 5, no. 2 (2016): 365–76. http://dx.doi.org/10.5121/ijci.2016.5239.

Full text

APA, Harvard, Vancouver, ISO, and other styles

28

Flake, Peter, Phil Moorby, Steve Golson, Arturo Salz, and Simon Davidmann. "Verilog HDL and its ancestors and descendants." Proceedings of the ACM on Programming Languages 4, HOPL (2020): 1–90. http://dx.doi.org/10.1145/3386337.

Full text

APA, Harvard, Vancouver, ISO, and other styles

29

Stojcev, M. "Verilog Digital Computer Design: Algorithms into Hardware." Microelectronics Journal 31, no. 5 (2000): 371–72. http://dx.doi.org/10.1016/s0026-2692(00)00004-5.

Full text

APA, Harvard, Vancouver, ISO, and other styles

30

Salama, Cherif, Gregory Malecha, Walid Taha, Jim Grundy, and John O’Leary. "Static consistency checking for Verilog wire interconnects." Higher-Order and Symbolic Computation 24, no. 1-2 (2011): 81–114. http://dx.doi.org/10.1007/s10990-011-9072-1.

Full text

APA, Harvard, Vancouver, ISO, and other styles

31

Reese, Robert B., and Mitchell A. Thornton. "Introduction to Logic Synthesis using Verilog HDL." Synthesis Lectures on Digital Circuits and Systems 1, no. 1 (2006): 1–84. http://dx.doi.org/10.2200/s00060ed1v01y200610dcs006.

Full text

APA, Harvard, Vancouver, ISO, and other styles

32

Usha, Kalluri. "Axi To Apb Interface Design Using Verilog." IOSR Journal of Electronics and Communication Engineering 8, no. 5 (2013): 01–09. http://dx.doi.org/10.9790/2834-0850109.

Full text

APA, Harvard, Vancouver, ISO, and other styles

33

Messaris, Ioannis, Alexander Serb, Spyros Stathopoulos, Ali Khiat, Spyridon Nikolaidis, and Themistoklis Prodromakis. "A Data-Driven Verilog-A ReRAM Model." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, no. 12 (2018): 3151–62. http://dx.doi.org/10.1109/tcad.2018.2791468.

Full text

APA, Harvard, Vancouver, ISO, and other styles

34

Krishna, T. Rama, T. Krishna Murthy, N. Vilasrao Sarode, P. Srilakshmi, and V. Geetha Sri. "Verilog HDL using LTE Implementation MAP Algorithm." International Journal of Innovative Research in Computer Science and Technology 10, no. 2 (2022): 611–14. http://dx.doi.org/10.55524/ijircst.2022.10.2.115.

Full text

Abstract:

In many communication systems, turbo coding Techniques for Encoding and Decoding are employed to repair errors. As compared to other error correction codes, turbo codes provide great error correcting capabilities. For the implementation of the Turbo decoder, a Very Large Scale Integration (VLSI) architecture is suggested in this study. The Maximum-a-Posteriori (MAP) algorithm is employed at the decoder side, where soft-in-soft-out decoders, interleaves, and deinterleavers are all used. The usage of the MAP algorithm reduces the quantity of iterations necessary to decode the information bits be

APA, Harvard, Vancouver, ISO, and other styles

35

Reddy, V. Vittal. "Implementation of Digital Filter Using Verilog HDL." International Journal for Research in Applied Science and Engineering Technology 12, no. 4 (2024): 3293–302. http://dx.doi.org/10.22214/ijraset.2024.60579.

Full text

Abstract:

Abstract: In the context of Very Large Scale Integration technology, where addition is essential, digital filters are essential elements. The performance of the Finite Impulse Response Filter is highly dependent on the speed of its multiplier unit, making itstand out among the others. In order to improve the effectiveness of the FIR filter, we suggest using a Wallace tree multiplier. This novel method offers improvements over conventional multipliers, with a decrease in latency being one of the main advantages. Significant improvements in latency are obtained by using Xilinx tools and implemen

APA, Harvard, Vancouver, ISO, and other styles

36

Wu, Jiang, Zhuo Zhang, Jianjun Xu, et al. "Detraque: Dynamic execution tracing techniques for automatic fault localization of hardware design code." PLOS ONE 17, no. 9 (2022): e0274515. http://dx.doi.org/10.1371/journal.pone.0274515.

Full text

Abstract:

In an error-prone development process, the ability to localize faults is a crucial one. Generally speaking, detecting and repairing errant behavior at an early stage of the development cycle considerably reduces costs and development time. The debugging of the Verilog program takes much time to read the waveform and capture the signal, and in many cases, problem-solving relies heavily on experienced developers. Most existing Verilog fault localization methods utilize the static analysis method to find faults. However, using static analysis methods exclusively may result in some types of faults

APA, Harvard, Vancouver, ISO, and other styles

37

Yan, Ziqi. "The application of Verilog in the development of casual games." Applied and Computational Engineering 76, no. 1 (2024): 245–49. http://dx.doi.org/10.54254/2755-2721/76/20240600.

Full text

Abstract:

Verilog is a hardware description language (HDL) that is widely used in digital circuit design and simulation. Its development is closely related to computer science and electrical engineering. Verilog gained popularity in the early 1980s as digital circuit designs became increasingly complex, requiring more efficient circuit design and verification tools. At the same time, rapid advances in computer hardware also stimulated the demand for digital circuit design languages. Furthermore, the popularity and adoption of Verilog highlight the growing necessity for digitisation, automation, and inte

APA, Harvard, Vancouver, ISO, and other styles

38

Kumar, Dr B. Ravi, Katte Srisha, and Boppana Akhila. "Realization of Advanced Peripheral Bus(APB) Protocol using Verilog." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–9. https://doi.org/10.55041/ijsrem40283.

Full text

Abstract:

This project details the Verilog implementation of the Advanced Peripheral Bus (APB) protocol, focusing on a configuration with one master and multiple slaves. As part of the Advanced Microcontroller Bus Architecture (AMBA), the APB protocol plays a crucial role in facilitating communication between a master, such as a microcontroller, and various peripheral devices (slaves) within System-on-Chip (SoC) designs. The design, created using Verilog—a prominent hardware description language—follows industry standards with an emphasis on modularity and scalability. Key aspects of the APB protocol ar

APA, Harvard, Vancouver, ISO, and other styles

39

Qiu, Mo, Simin Yu, Yuqiong Wen, Jinhu Lü, Jianbin He, and Zhuosheng Lin. "Design and FPGA Implementation of a Universal Chaotic Signal Generator Based on the Verilog HDL Fixed-Point Algorithm and State Machine Control." International Journal of Bifurcation and Chaos 27, no. 03 (2017): 1750040. http://dx.doi.org/10.1142/s0218127417500407.

Full text

Abstract:

In this paper, a novel design methodology and its FPGA hardware implementation for a universal chaotic signal generator is proposed via the Verilog HDL fixed-point algorithm and state machine control. According to continuous-time or discrete-time chaotic equations, a Verilog HDL fixed-point algorithm and its corresponding digital system are first designed. In the FPGA hardware platform, each operation step of Verilog HDL fixed-point algorithm is then controlled by a state machine. The generality of this method is that, for any given chaotic equation, it can be decomposed into four basic operat

APA, Harvard, Vancouver, ISO, and other styles

40

Radu, Valentin, Diana Dranga, Catalin Dumitrescu, Alina Iuliana Tabirca, and Maria Cristina Stefan. "Generative AI Assertions in UVM-Based System Verilog Functional Verification." Systems 12, no. 10 (2024): 390. http://dx.doi.org/10.3390/systems12100390.

Full text

Abstract:

This paper investigates the potential of leveraging artificial intelligence to automate and optimize the verification process, particularly in generating System Verilog assertions for an Advance Peripheral Bus verification environment using Universal Verification Methodology. Generative artificial intelligence, such as ChatGPT, demonstrated its ability to produce accurate and valuable assertions by employing text-based prompts and image-fed inputs, significantly reducing the required manual effort. This research presents a way of generating System Verilog assertions using the ChatGPT prompt, p

APA, Harvard, Vancouver, ISO, and other styles

41

Kwon, Bo-Seung, Sang-Won Jung, Young-Dan Noh, Jong-Sik Lee, and Young-Shin Han. "RTL-DEVS: HDL Design and Simulation Methodology for DEVS Formalism-Based Simulation Tool." Telecom 4, no. 1 (2022): 15–30. http://dx.doi.org/10.3390/telecom4010002.

Full text

Abstract:

DEVS (Discrete Event System Specification) is widely used in modeling and simulation fields to design, validate, and implement complex response systems. DEVS provides a robust formalism for system design using event-driven, state-based models with explicitly defined temporal information. We extend the RTL-DEVS model based on DEVS formalism to enable part of Verilog simulation in DEVS-based simulation tools. The simulation based on RTL-DEVS methodology, which imitates Verilog’s testbench and behavioral module, confirmed through experiments that RTL simulation can be performed sufficiently throu

APA, Harvard, Vancouver, ISO, and other styles

42

Gong, Yue Hong, Min Luo, and Jian Guo Ma. "Digitally Assisted Backend Correction Pipeline ADC Verilog-A Modeling." Advanced Materials Research 457-458 (January 2012): 1122–28. http://dx.doi.org/10.4028/www.scientific.net/amr.457-458.1122.

Full text

Abstract:

In this paper, a 12 bits pipeline ADC (analog to digital converter) based on digitally assisted backend correction is described and behaviorally modeled in Verilog-A language. The Verilog-A model is simulated with Cadence Spectre simulator. In the traditional use of pipeline ADC, the for-end sample and hold amplifier occupies the most power consumption. To decreases the system power consumption, open-loop amplifier is used in the first residual amplify circuit between first and second stage sub-ADC. To correct the nonlinear error introduced by the open-loop amplifier, backend digitally correct

APA, Harvard, Vancouver, ISO, and other styles

43

Zheng, Li Kun, Ya Li Chen, and Zhe Ying Li. "Design and Implementation of USB Transceiver with Verilog." Applied Mechanics and Materials 462-463 (November 2013): 604–8. http://dx.doi.org/10.4028/www.scientific.net/amm.462-463.604.

Full text

Abstract:

The Universal Serial Bus Transceiver is one of the important functional blocks of USB controller, which can transmit and receive data to or from USB devices. In this paper, USB Transceiver is designed and implemented with Verilog HDL, This includes functions such as, data serialization, bit stuffing, NRZI encoding and NRZI decoding, bit destuffing, deserialization. The transceiver is simulated by the modelsim software and the simulation wave is gave.

APA, Harvard, Vancouver, ISO, and other styles

44

Mendoza, Mar Christian, Rhea B. Magabo, Glenlie P. Avelino, Ben Joseph P. Avelino, and Rionel B. Caldo. "SMART TrafGc Control System Designed Using Verilog HDL." IJASC 1, no. 2 (2019): 11–16. http://dx.doi.org/10.22662/ijasc.2019.1.2.011.

Full text

APA, Harvard, Vancouver, ISO, and other styles

45

Mittal, Mayank. "Simulation of 16 bit ALU using Verilog-hdl." International Journal of Trend in Scientific Research and Development Volume-2, Issue-1 (2017): 114–15. http://dx.doi.org/10.31142/ijtsrd5876.

Full text

APA, Harvard, Vancouver, ISO, and other styles

46

Divya, Bejagam. "Design of High Speed Sequence Detector using Verilog." International Journal for Research in Applied Science and Engineering Technology 8, no. 7 (2020): 609–14. http://dx.doi.org/10.22214/ijraset.2020.30290.

Full text

APA, Harvard, Vancouver, ISO, and other styles

47

McAndrew, Colin C., Geoffrey J. Coram, Kiran K. Gullapalli, et al. "Best Practices for Compact Modeling in Verilog-A." IEEE Journal of the Electron Devices Society 3, no. 5 (2015): 383–96. http://dx.doi.org/10.1109/jeds.2015.2455342.

Full text

APA, Harvard, Vancouver, ISO, and other styles

48

Kris Gaj, Chin-Hong Cheah, E. G. Friedman, and M. J. Feldman. "Functional modeling of RSFQ circuits using Verilog HDL." IEEE Transactions on Appiled Superconductivity 7, no. 2 (1997): 3151–54. http://dx.doi.org/10.1109/77.622000.

Full text

APA, Harvard, Vancouver, ISO, and other styles

49

Song, Chunwei, Xianghu Wu, and Yongchao Tao. "FPGA virtual platform based on systemc and verilog." IOP Conference Series: Materials Science and Engineering 768 (March 31, 2020): 072001. http://dx.doi.org/10.1088/1757-899x/768/7/072001.

Full text

APA, Harvard, Vancouver, ISO, and other styles

50

Borrione, D., R. Piloty, D. Hill, K. J. Lieberherr, and P. Moorby. "Three decades of HDLs. II. Conlan through Verilog." IEEE Design & Test of Computers 9, no. 3 (1992): 54–63. http://dx.doi.org/10.1109/54.156158.

Full text

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!