Relevant bibliographies by topics / Circuit optimization

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Circuit optimization'

Author: Grafiati
Published: 4 June 2021
Last updated: 25 July 2025

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Journal articles on the topic "Circuit optimization"

1

Liu, Manqi. "Current Status, Development, And Application of Optimization Methods for Analog Circuits." Highlights in Science, Engineering and Technology 81 (January 26, 2024): 438–43. http://dx.doi.org/10.54097/j4vjfn83.

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The optimization of analog circuits has always relied on the experience and intuition of engineers to find suitable parameters to meet the requirements of the circuit, which is time-consuming and costly. This paper outlines and analyzes the optimization methods for analog circuits in recent years, and draws some summaries that can be used as references for subsequent optimization circuits. The optimization of analog circuits is mainly divided into the optimization of the performance of the hardware in the circuit and the optimization of the circuit structure. Hardware optimization, this paper
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Jim, Ho Joon, and Fazida Hanim Hashim. "An improved ant colony optimization algorithm for wire optimization." Bulletin of Electrical Engineering and Informatics 9, no. 5 (2020): 2170–77. http://dx.doi.org/10.11591/eei.v9i5.2268.

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Wire optimization has become one of the greatest challenges in today’s circuit design. This paper presents a method for wire optimization in circuit routing using an improved ant colony optimization with Steiner nodes (ACOSN) algorithm. Circuit delay and power dissipation are primarily affected by the length of the routed wire. Thus, the main goal of this proposed algorithm is to find the shortest route from one point to another using an algorithm that relies on the artificial behavior of ants. The algorithm is implemented in the JAVA programming language. The proposed ACOSN algorithm is compa
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Ho, Joon Jim, and Hanim Hashim Fazida. "An improved ant colony optimization algorithm for wire optimization." Bulletin of Electrical Engineering and Informatics 9, no. 5 (2020): 2170–77. https://doi.org/10.11591/eei.v9i5.2268.

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Wire optimization has become one of the greatest challenges in today’s circuit design. This paper presents a method for wire optimization in circuit routing using an improved ant colony optimization with Steiner nodes (ACOSN) algorithm. Circuit delay and power dissipation are primarily affected by the length of the routed wire. Thus, the main goal of this proposed algorithm is to find the shortest route from one point to another using an algorithm that relies on the artificial behavior of ants. The algorithm is implemented in the JAVA programming language. The proposed ACOSN algorithm is
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Deng, Jingxi. "Systematic Analysis and Research on Integrated Circuit Design Optimization." Highlights in Science, Engineering and Technology 81 (January 26, 2024): 197–201. http://dx.doi.org/10.54097/q42hbs73.

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After decades of development of integrated circuits, there has been great progress in all aspects. These advances are reflected in the optimization of manufacturing processes and circuits. When designing a circuit, considering the production cost and the performance of the circuit, the optimal design of the circuit is always a very important link. In this paper, two kinds of optimization ideas are introduced. One is from the point of view of the physical design of the circuit, two methods are introduced, which are adjusting the input power and reducing the circuit device. The other is to optim
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Amy, Matthew, and Joseph Lunderville. "Linear and Non-linear Relational Analyses for Quantum Program Optimization." Proceedings of the ACM on Programming Languages 9, POPL (2025): 1072–103. https://doi.org/10.1145/3704873.

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The phase folding optimization is a circuit optimization used in many quantum compilers as a fast and effective way of reducing the number of high-cost gates in a quantum circuit. However, existing formulations of the optimization rely on an exact, linear algebraic representation of the circuit, restricting the optimization to being performed on straightline quantum circuits or basic blocks in a larger quantum program. We show that the phase folding optimization can be re-cast as an affine relation analysis , which allows the direct application of classical techniques for affine relations to e
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Barra, Samir. "Intelligent Optimization of CMOS Operational Amplifier Using 3D Ant Colony Optimization." Electronics ETF 27, no. 2 (2023): 35–42. http://dx.doi.org/10.53314/els2327035b.

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This paper presents the use of an artificial intelligence (AI) tool based on ant colony behavior to design an operational amplifier circuit. The ant colony optimization (ACO) is implemented in a hybrid evolutionary sizing method to automate analog circuit design. This new meta-heuristic approach that combines the artificial intelligence of an ant colony and the 3D matrix method is developed to determine the optimal dimensions and the main influencing performances of fundamental analog circuits and, including operational amplifiers (op-amps). The proposed methodology uses ACO and Cadence Spectr
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Hsiao, Michael S. "Genetic Spot Optimization for Peak Power Estimation in Large VLSI Circuits." VLSI Design 15, no. 1 (2002): 407–16. http://dx.doi.org/10.1080/1065514021000012020.

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Estimating peak power involves optimization of the circuit's switching function. The switching of a given gate is not only dependent on the output capacitance of the node, but also heavily dependent on the gate delays in the circuit, since multiple switching events can result from uneven circuit delay paths in the circuit. Genetic spot expansion and optimization are proposed in this paper to estimate tight peak power bounds for large sequential circuits. The optimization spot shifts and expands dynamically based on the maximum power potential (MPP) of the nodes under optimization. Four genetic
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Aizik, Yoni, and Avinoam Kolodny. "Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints." VLSI Design 2011 (April 7, 2011): 1–13. http://dx.doi.org/10.1155/2011/845957.

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A design scenario examined in this paper assumes that a circuit has been designed initially for high speed, and it is redesigned for low power by downsizing of the gates. In recent years, as power consumption has become a dominant issue, new optimizations of circuits are required for saving energy. This is done by trading off some speed in exchange for reduced power. For each feasible speed, an optimization problem is solved in this paper, finding new sizes for the gates such that the circuit satisfies the speed goal while dissipating minimal power. Energy/delay gain (EDG) is defined as a metr
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Purushottam Kumar Maurya. "Smart Circuit Design Machine Learning-Driven Optimization for Enhanced Performance in Electronics and Computer Engineering." Tuijin Jishu/Journal of Propulsion Technology 45, no. 02 (2024): 2794–805. http://dx.doi.org/10.52783/tjjpt.v45.i02.6339.

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In the realm of Electronics and Computer engineering, achieving optimal performance of circuits amidst escalating complexity poses significant challenges. Traditional manual optimization techniques are often inadequate to navigate the intricacies of modern electronic systems. This paper advocates for the adoption of machine learning-driven optimization as a transformative approach to smart circuit design. By leveraging machine learning algorithms, engineers can systematically explore the expansive design space, discern complex relationships between circuit parameters and performance metrics, a
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He, Xinyu. "Design of CMOS circuits through transistor sizing techniques." Applied and Computational Engineering 12, no. 1 (2023): 1–12. http://dx.doi.org/10.54254/2755-2721/12/20230279.

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With the increasingly diverse functional requirements of contemporary electronic products, the complexity of CMOS circuits often used in chips becomes higher and the number of transistors used increases. To solve the resulting performance problems of CMOS circuits, researchers have searched for many transistor sizing technologies. This paper summarizes three methods of CMOS circuit optimization. The paper introduces these three methods in terms of principle, effect, and application scenarios, and compares them respectively. Through analysis and simulation, it can be found that the use of these
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Dissertations / Theses on the topic "Circuit optimization"

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Markle, Kendra L. (Kendra Lys). "Methodology for circuit optimization." Thesis, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/37001.

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Manthe, Alicia Louise. "Symbolic circuit analysis : DDD optimization and nonlinearity analysis /." Thesis, Connect to this title online; UW restricted, 2003. http://hdl.handle.net/1773/6082.

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Aggarwal, Varun. "Analog circuit optimization using evolutionary algorithms and convex optimization." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/40525.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.<br>Includes bibliographical references (p. 83-88).<br>In this thesis, we analyze state-of-art techniques for analog circuit sizing and compare them on various metrics. We ascertain that a methodology which improves the accuracy of sizing without increasing the run time or the designer effort is a contribution. We argue that the accuracy of geometric programming can be improved without adversely influencing the run time or increasing the designer's effort. This is facilitated by dec
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Mitros, Piotr 1979. "A framework for analog circuit optimization." Thesis, Massachusetts Institute of Technology, 2004. http://hdl.handle.net/1721.1/28447.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.<br>Includes bibliographical references (p. 49-50).<br>This thesis presents a system for optimization of analog circuit topologies and component values. The topology is optimized using simulated annealing, while the component values are optimized using gradient descent. Local minima are avoided and constraints are kept through the use of coordinate transformations, as well as the use of default starting points for component values. The system is targeted for use in 3D integrated
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Lui, Siu-hong. "Analog circuit design by nonconvex polynomial optimization two design examples /." Click to view the E-thesis via HKUTO, 2007. http://sunzi.lib.hku.hk/HKUTO/record/B39557418.

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Agnihotri, Ameya Ramesh. "Combinatorial optimization techniques for VLSI placement." Diss., Online access via UMI:, 2007.

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Bhattacharya, Sambuddha. "Template-driven parasitic-aware optimization of analog/RF IC layouts /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6121.

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Thakral, Garima. "Process-Voltage-Temperature Aware Nanoscale Circuit Optimization." Thesis, University of North Texas, 2010. https://digital.library.unt.edu/ark:/67531/metadc67943/.

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Embedded systems which are targeted towards portable applications are required to have low power consumption because such portable devices are typically powered by batteries. During the memory accesses of such battery operated portable systems, including laptops, cell phones and other devices, a significant amount of power or energy is consumed which significantly affects the battery life. Therefore, efficient and leakage power saving cache designs are needed for longer operation of battery powered applications. Design engineers have limited control over many design parameters of the circuit a
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Lui, Siu-hong, and 呂小康. "Analog circuit design by nonconvex polynomial optimization: two design examples." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B39557418.

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Lehmann, Peter W. "Printed circuit board manufacturing process improvement drill optimization." Menomonie, WI : University of Wisconsin--Stout, 2005. http://www.uwstout.edu/lib/thesis/2005/2005lehmannp.pdf.

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Books on the topic "Circuit optimization"

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Litovski, V. VLSI circuit simulation and optimization. Chapman & Hall, 1997.

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Hochet, Bertrand, Antonio J. Acosta, and Manuel J. Bellido, eds. Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-45716-x.

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Liu, Hsiao-Hsuan, and Francky Catthoor. Circuit-Technology Co-Optimization of SRAM Design in Advanced CMOS Nodes. Springer Nature Switzerland, 2025. https://doi.org/10.1007/978-3-031-76109-6.

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Tlelo-Cuautle, Esteban, Mourad Fakhfakh, and Maria Helena Fino. Performance optimization techniques in analog mixed-signal, and radio-frequency circuit design. Engineering Science Reference, and imprint of IGI Global, 2015.

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Kourtev, Ivan S. Timing optimization through clock skew scheduling. Kluwer Academic, 2000.

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Paliouras, Vassilis, Johan Vounckx, and Diederik Verkest, eds. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11556930.

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Azémard, Nadine, and Lars Svensson, eds. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. Springer Berlin Heidelberg, 2007. http://dx.doi.org/10.1007/978-3-540-74442-9.

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Ayala, José L., Braulio García-Cámara, Manuel Prieto, Martino Ruggiero, and Gilles Sicard, eds. Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-24154-3.

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Ayala, José L., Delong Shang, and Alex Yakovlev, eds. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-36157-9.

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van Leuken, René, and Gilles Sicard, eds. Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-17752-1.

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Book chapters on the topic "Circuit optimization"

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Marković, Dejan, Robert W. Brodersen, and Borivoje Nikolić. "Circuit Optimization." In DSP Architecture Design Essentials. Springer US, 2012. http://dx.doi.org/10.1007/978-1-4419-9660-2_2.

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Chan, Tony F., Jason Cong, Tim Tianming Kong, and Joseph R. Shinnerl. "Multilevel Circuit Placement." In Combinatorial Optimization. Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3748-6_4.

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Iman, Sasan, and Massoud Pedram. "Combinational Circuit Optimization." In Low Power Design in Deep Submicron Electronics. Springer US, 1997. http://dx.doi.org/10.1007/978-1-4615-5685-5_9.

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Weber, Stephan, and Cândido Duarte. "Optimization Techniques for Circuit Design." In Circuit Design. River Publishers, 2022. http://dx.doi.org/10.1201/9781003337539-12.

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Dadush, Daniel, Zhuan Khye Koh, Bento Natura, and László A. Végh. "On Circuit Diameter Bounds via Circuit Imbalances." In Integer Programming and Combinatorial Optimization. Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-06901-7_11.

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Zhang, J. C., and M. A. Styblinski. "Multi-Objective Circuit Optimization." In Yield and Variability Optimization of Integrated Circuits. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2225-6_7.

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Dua, Anahita, Sara Rose-Sauld, and Lindsey Ferraro. "Circuit Maintenance and Optimization." In The Massachusetts General Hospital Approach to Transcatheter Arterialization of the Deep Veins for Advanced Limb Salvage. Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-37510-1_13.

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Golanbari, Mohammad Saber, Mojtaba Ebrahimi, Saman Kiamehr, and Mehdi B. Tahoori. "Selective Flip-Flop Optimization for Circuit Reliability." In Dependable Embedded Systems. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_14.

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AbstractThis chapter proposes a selective flip-flop optimization method (Golanbari et al., IEEE Trans Very Large Scale Integr VLSI Syst 39(7):1484–1497, 2020; Golanbari et al., Aging guardband reduction through selective flip-flop optimization. In: IEEE European Test Symposium (ETS) (2015)), in which the timing and reliability of the VLSI circuits are improved by optimizing the timing-critical components under severe impact of runtime variations. As flip-flops are vulnerable to aging and supply voltage fluctuation, it is necessary to address these reliability issues in order to improve the ove
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Lengauer, Thomas. "Optimization Problems." In Combinatorial Algorithms for Integrated Circuit Layout. Vieweg+Teubner Verlag, 1990. http://dx.doi.org/10.1007/978-3-322-92106-2_2.

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Guenin, Bertrand. "Circuit Mengerian Directed Graphs." In Integer Programming and Combinatorial Optimization. Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/3-540-45535-3_15.

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Conference papers on the topic "Circuit optimization"

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Bodoh, Alexander, and Ashiq A. Sakib. "ASCEND: Advanced Synthesis, Circuit Exploration, and Design Optimization for NCL Circuits." In 2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS). IEEE, 2024. https://doi.org/10.1109/icecs61496.2024.10849171.

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Ramakrishnan, Ranjith Kumar. "Genetic Algorithm Optimization in Circuit Design." In 2025 1st International Conference on AIML-Applications for Engineering & Technology (ICAET). IEEE, 2025. https://doi.org/10.1109/icaet63349.2025.10932253.

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Odonnat, Ambroise, Wassim Bouaziz, and Vivien Cabannes. "Easing Optimization Paths: a Circuit Perspective." In ICASSP 2025 - 2025 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP). IEEE, 2025. https://doi.org/10.1109/icassp49660.2025.10888894.

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Dawood, Kamran, and Güven Kömürgöz Kırış. "Assessment of Electromagnetic Forces in Transformers Under Open-Circuit and Short-Circuit Conditions." In 2025 7th International Congress on Human-Computer Interaction, Optimization and Robotic Applications (ICHORA). IEEE, 2025. https://doi.org/10.1109/ichora65333.2025.11017322.

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Oh, Youngmin, Doyun Kim, Yoon Hyeok Lee, and Bosun Hwang. "CRONuS: Circuit Rapid Optimization with Neural Simulator." In 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2024. http://dx.doi.org/10.23919/date58400.2024.10546592.

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YILIN, YANG. "AI-based automated circuit design optimization technology." In International Conference on Electronics. Electrical and Information Engineering, edited by Shengqing Li and Bin Hu. SPIE, 2024. https://doi.org/10.1117/12.3052159.

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Li, Xinpeng, Vinooth Rao Kulkarni, Jai Nana, et al. "Quantum Circuit Optimization for Protein Structure Prediction." In 2025 55th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W). IEEE, 2025. https://doi.org/10.1109/dsn-w65791.2025.00065.

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He, Songxuan, Wangyong Chen, Ling Xiong, and Linlin Cai. "Co-Optimization Design Method of Temperature Variation and Circuit Aging in Digital Circuits." In 2024 IEEE 17th International Conference on Solid-State & Integrated Circuit Technology (ICSICT). IEEE, 2024. https://doi.org/10.1109/icsict62049.2024.10832040.

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Lokanathan, Arun, and Jay Brockman. "Process multi-circuit optimization." In the 35th annual conference. ACM Press, 1998. http://dx.doi.org/10.1145/277044.277149.

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Wang, Baohua, and Pinaki Mazumder. "Optimization of circuit trajectories." In the 2006 conference. ACM Press, 2006. http://dx.doi.org/10.1145/1118299.1118401.

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Reports on the topic "Circuit optimization"

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Chuang, Wei-Tong. Timing and Area Optimization for VLSI Circuit and Layout. Defense Technical Information Center, 1994. http://dx.doi.org/10.21236/ada281081.

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S.R. Harker, C.R. Vogel, and T. Gedeon. Analysis of Constrained Optimization Variants of the Map-Seeking Circuit Algorithm. Office of Scientific and Technical Information (OSTI), 2005. http://dx.doi.org/10.2172/891009.

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S. K. Kawatra, T. C. Eisele, T. Weldum, D. Larsen, R. Mariani, and J. Pletka. Optimization of Comminution Circuit Throughput and Product Size Distribution by Simulation and Control. Michigan Technological Univ, 2005. http://dx.doi.org/10.2172/899458.

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Kawatra, S. K., T. C. Eisele, and H. J. Walqui. OPTIMIZATION OF COMMINUTION CIRCUIT THROUGHPUT AND PRODUCT SIZE DISTRIBUTION BY SIMULATION AND CONTROL. Office of Scientific and Technical Information (OSTI), 2001. http://dx.doi.org/10.2172/792074.

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Kawatra, S. K., T. C. Eisele, and H. J. Walqui. OPTIMIZATION OF COMMINUTION CIRCUIT THROUGHPUT AND PRODUCT SIZE DISTRIBUTION BY SIMULATION AND CONTROL. Office of Scientific and Technical Information (OSTI), 2001. http://dx.doi.org/10.2172/792077.

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Kawatra, S. K., T. C. Eisele, and H. J. Walqui. OPTIMIZATION OF COMMINUTION CIRCUIT THROUGHPUT AND PRODUCT SIZE DISTRIBUTION BY SIMULATION AND CONTROL. Office of Scientific and Technical Information (OSTI), 2001. http://dx.doi.org/10.2172/792079.

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Kawatra, S. K., T. C. Eisele, and H. J. Walqui. OPTIMIZATION OF COMMINUTION CIRCUIT THROUGHPUT AND PRODUCT SIZE DISTRIBUTION BY SIMULATION AND CONTROL. Office of Scientific and Technical Information (OSTI), 2002. http://dx.doi.org/10.2172/792080.

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S.K. Kawatra, T.C. Eisele, T. Weldum, D. Larsen, R. Mariani, and J. Pletka. Optimization of Comminution Circuit Throughput and Product Size Distribution by Simulation and Control. Office of Scientific and Technical Information (OSTI), 2005. http://dx.doi.org/10.2172/887498.

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T.C. Eisele, S.K. Kawatra, and H.J. Walqui. OPTIMIZATION OF COMMINUTION CIRCUIT THROUGHPUT AND PRODUCT SIZE DISTRIBUTION BY SIMULATION AND CONTROL. Office of Scientific and Technical Information (OSTI), 2004. http://dx.doi.org/10.2172/835514.

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S.K. Kawatra, T.C. Eisele, T. Weldum, D. Larsen, R. Mariani, and J. Pletka. OPTIMIZATION OF COMMINUTION CIRCUIT THROUGHPUT AND PRODUCT SIZE DISTRIBUTION BY SIMULATION AND CONTROL. Office of Scientific and Technical Information (OSTI), 2005. http://dx.doi.org/10.2172/837186.

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